The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/mv_pci.c

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    1 /*-
    2  * Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
    3  * Copyright (c) 2010 The FreeBSD Foundation
    4  * All rights reserved.
    5  *
    6  * Developed by Semihalf.
    7  *
    8  * Portions of this software were developed by Semihalf
    9  * under sponsorship from the FreeBSD Foundation.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. Neither the name of MARVELL nor the names of contributors
   20  *    may be used to endorse or promote products derived from this software
   21  *    without specific prior written permission.
   22  *
   23  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   26  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   27  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   29  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   33  * SUCH DAMAGE.
   34  */
   35 
   36 /*
   37  * Marvell integrated PCI/PCI-Express controller driver.
   38  */
   39 
   40 #include <sys/cdefs.h>
   41 __FBSDID("$FreeBSD: releng/9.0/sys/arm/mv/mv_pci.c 218228 2011-02-03 18:07:05Z marcel $");
   42 
   43 #include <sys/param.h>
   44 #include <sys/systm.h>
   45 #include <sys/kernel.h>
   46 #include <sys/lock.h>
   47 #include <sys/malloc.h>
   48 #include <sys/module.h>
   49 #include <sys/mutex.h>
   50 #include <sys/queue.h>
   51 #include <sys/bus.h>
   52 #include <sys/rman.h>
   53 #include <sys/endian.h>
   54 
   55 #include <vm/vm.h>
   56 #include <vm/pmap.h>
   57 
   58 #include <dev/fdt/fdt_common.h>
   59 #include <dev/ofw/ofw_bus.h>
   60 #include <dev/ofw/ofw_bus_subr.h>
   61 #include <dev/pci/pcivar.h>
   62 #include <dev/pci/pcireg.h>
   63 #include <dev/pci/pcib_private.h>
   64 
   65 #include "ofw_bus_if.h"
   66 #include "pcib_if.h"
   67 
   68 #include <machine/resource.h>
   69 #include <machine/bus.h>
   70 
   71 #include <arm/mv/mvreg.h>
   72 #include <arm/mv/mvvar.h>
   73 #include <arm/mv/mvwin.h>
   74 
   75 #define PCI_CFG_ENA             (1 << 31)
   76 #define PCI_CFG_BUS(bus)        (((bus) & 0xff) << 16)
   77 #define PCI_CFG_DEV(dev)        (((dev) & 0x1f) << 11)
   78 #define PCI_CFG_FUN(fun)        (((fun) & 0x7) << 8)
   79 #define PCI_CFG_PCIE_REG(reg)   ((reg) & 0xfc)
   80 
   81 #define PCI_REG_CFG_ADDR        0x0C78
   82 #define PCI_REG_CFG_DATA        0x0C7C
   83 #define PCI_REG_P2P_CONF        0x1D14
   84 
   85 #define PCIE_REG_CFG_ADDR       0x18F8
   86 #define PCIE_REG_CFG_DATA       0x18FC
   87 #define PCIE_REG_CONTROL        0x1A00
   88 #define   PCIE_CTRL_LINK1X      0x00000001
   89 #define PCIE_REG_STATUS         0x1A04
   90 #define PCIE_REG_IRQ_MASK       0x1910
   91 
   92 #define STATUS_LINK_DOWN        1
   93 #define STATUS_BUS_OFFS         8
   94 #define STATUS_BUS_MASK         (0xFF << STATUS_BUS_OFFS)
   95 #define STATUS_DEV_OFFS         16
   96 #define STATUS_DEV_MASK         (0x1F << STATUS_DEV_OFFS)
   97 
   98 #define P2P_CONF_BUS_OFFS       16
   99 #define P2P_CONF_BUS_MASK       (0xFF << P2P_CONF_BUS_OFFS)
  100 #define P2P_CONF_DEV_OFFS       24
  101 #define P2P_CONF_DEV_MASK       (0x1F << P2P_CONF_DEV_OFFS)
  102 
  103 #define PCI_VENDORID_MRVL       0x11AB
  104 
  105 struct mv_pcib_softc {
  106         device_t        sc_dev;
  107 
  108         struct rman     sc_mem_rman;
  109         bus_addr_t      sc_mem_base;
  110         bus_addr_t      sc_mem_size;
  111         bus_addr_t      sc_mem_alloc;           /* Next allocation. */
  112         int             sc_mem_win_target;
  113         int             sc_mem_win_attr;
  114 
  115         struct rman     sc_io_rman;
  116         bus_addr_t      sc_io_base;
  117         bus_addr_t      sc_io_size;
  118         bus_addr_t      sc_io_alloc;            /* Next allocation. */
  119         int             sc_io_win_target;
  120         int             sc_io_win_attr;
  121 
  122         struct resource *sc_res;
  123         bus_space_handle_t sc_bsh;
  124         bus_space_tag_t sc_bst;
  125         int             sc_rid;
  126 
  127         int             sc_busnr;               /* Host bridge bus number */
  128         int             sc_devnr;               /* Host bridge device number */
  129         int             sc_type;
  130 
  131         struct fdt_pci_intr     sc_intr_info;
  132 };
  133 
  134 /* Local forward prototypes */
  135 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *);
  136 static void mv_pcib_hw_cfginit(void);
  137 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int,
  138     u_int, u_int, int);
  139 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int,
  140     u_int, u_int, uint32_t, int);
  141 static int mv_pcib_init(struct mv_pcib_softc *, int, int);
  142 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int);
  143 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int);
  144 static int mv_pcib_intr_info(phandle_t, struct mv_pcib_softc *);
  145 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t);
  146 
  147 
  148 /* Forward prototypes */
  149 static int mv_pcib_probe(device_t);
  150 static int mv_pcib_attach(device_t);
  151 
  152 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *,
  153     u_long, u_long, u_long, u_int);
  154 static int mv_pcib_release_resource(device_t, device_t, int, int,
  155     struct resource *);
  156 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
  157 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t);
  158 
  159 static int mv_pcib_maxslots(device_t);
  160 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
  161 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
  162     uint32_t, int);
  163 static int mv_pcib_route_interrupt(device_t, device_t, int);
  164 
  165 /*
  166  * Bus interface definitions.
  167  */
  168 static device_method_t mv_pcib_methods[] = {
  169         /* Device interface */
  170         DEVMETHOD(device_probe,                 mv_pcib_probe),
  171         DEVMETHOD(device_attach,                mv_pcib_attach),
  172 
  173         /* Bus interface */
  174         DEVMETHOD(bus_print_child,              bus_generic_print_child),
  175         DEVMETHOD(bus_read_ivar,                mv_pcib_read_ivar),
  176         DEVMETHOD(bus_write_ivar,               mv_pcib_write_ivar),
  177         DEVMETHOD(bus_alloc_resource,           mv_pcib_alloc_resource),
  178         DEVMETHOD(bus_release_resource,         mv_pcib_release_resource),
  179         DEVMETHOD(bus_activate_resource,        bus_generic_activate_resource),
  180         DEVMETHOD(bus_deactivate_resource,      bus_generic_deactivate_resource),
  181         DEVMETHOD(bus_setup_intr,               bus_generic_setup_intr),
  182         DEVMETHOD(bus_teardown_intr,            bus_generic_teardown_intr),
  183 
  184         /* pcib interface */
  185         DEVMETHOD(pcib_maxslots,                mv_pcib_maxslots),
  186         DEVMETHOD(pcib_read_config,             mv_pcib_read_config),
  187         DEVMETHOD(pcib_write_config,            mv_pcib_write_config),
  188         DEVMETHOD(pcib_route_interrupt,         mv_pcib_route_interrupt),
  189 
  190         /* OFW bus interface */
  191         DEVMETHOD(ofw_bus_get_compat,   ofw_bus_gen_get_compat),
  192         DEVMETHOD(ofw_bus_get_model,    ofw_bus_gen_get_model),
  193         DEVMETHOD(ofw_bus_get_name,     ofw_bus_gen_get_name),
  194         DEVMETHOD(ofw_bus_get_node,     ofw_bus_gen_get_node),
  195         DEVMETHOD(ofw_bus_get_type,     ofw_bus_gen_get_type),
  196 
  197         { 0, 0 }
  198 };
  199 
  200 static driver_t mv_pcib_driver = {
  201         "pcib",
  202         mv_pcib_methods,
  203         sizeof(struct mv_pcib_softc),
  204 };
  205 
  206 devclass_t pcib_devclass;
  207 
  208 DRIVER_MODULE(pcib, fdtbus, mv_pcib_driver, pcib_devclass, 0, 0);
  209 
  210 static struct mtx pcicfg_mtx;
  211 
  212 static int
  213 mv_pcib_probe(device_t self)
  214 {
  215         phandle_t node;
  216 
  217         node = ofw_bus_get_node(self);
  218         if (!fdt_is_type(node, "pci"))
  219                 return (ENXIO);
  220 
  221         if (!(fdt_is_compatible(node, "mrvl,pcie") ||
  222             fdt_is_compatible(node, "mrvl,pci")))
  223                 return (ENXIO);
  224 
  225         device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller");
  226         return (BUS_PROBE_DEFAULT);
  227 }
  228 
  229 static int
  230 mv_pcib_attach(device_t self)
  231 {
  232         struct mv_pcib_softc *sc;
  233         phandle_t node, parnode;
  234         uint32_t val;
  235         int err;
  236 
  237         sc = device_get_softc(self);
  238         sc->sc_dev = self;
  239 
  240         node = ofw_bus_get_node(self);
  241         parnode = OF_parent(node);
  242         if (fdt_is_compatible(node, "mrvl,pcie")) {
  243                 sc->sc_type = MV_TYPE_PCIE;
  244                 sc->sc_mem_win_target = MV_WIN_PCIE_MEM_TARGET;
  245                 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR;
  246                 sc->sc_io_win_target = MV_WIN_PCIE_IO_TARGET;
  247                 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR;
  248 #ifdef SOC_MV_ORION
  249         } else if (fdt_is_compatible(node, "mrvl,pci")) {
  250                 sc->sc_type = MV_TYPE_PCI;
  251                 sc->sc_mem_win_target = MV_WIN_PCI_MEM_TARGET;
  252                 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR;
  253                 sc->sc_io_win_target = MV_WIN_PCI_IO_TARGET;
  254                 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR;
  255 #endif
  256         } else
  257                 return (ENXIO);
  258 
  259         /*
  260          * Get PCI interrupt info.
  261          */
  262         if (mv_pcib_intr_info(node, sc) != 0) {
  263                 device_printf(self, "could not retrieve interrupt info\n");
  264                 return (ENXIO);
  265         }
  266 
  267         /*
  268          * Retrieve our mem-mapped registers range.
  269          */
  270         sc->sc_rid = 0;
  271         sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid,
  272             RF_ACTIVE);
  273         if (sc->sc_res == NULL) {
  274                 device_printf(self, "could not map memory\n");
  275                 return (ENXIO);
  276         }
  277         sc->sc_bst = rman_get_bustag(sc->sc_res);
  278         sc->sc_bsh = rman_get_bushandle(sc->sc_res);
  279 
  280         /*
  281          * Configure decode windows for PCI(E) access.
  282          */
  283         if (mv_pcib_decode_win(node, sc) != 0)
  284                 return (ENXIO);
  285 
  286         mv_pcib_hw_cfginit();
  287 
  288         /*
  289          * Enable PCI bridge.
  290          */
  291         val = mv_pcib_hw_cfgread(sc, sc->sc_busnr, sc->sc_devnr, 0,
  292             PCIR_COMMAND, 2);
  293         val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
  294             PCIM_CMD_PORTEN;
  295         mv_pcib_hw_cfgwrite(sc, sc->sc_busnr, sc->sc_devnr, 0,
  296             PCIR_COMMAND, val, 2);
  297 
  298         sc->sc_mem_alloc = sc->sc_mem_base;
  299         sc->sc_io_alloc = sc->sc_io_base;
  300 
  301         sc->sc_mem_rman.rm_type = RMAN_ARRAY;
  302         err = rman_init(&sc->sc_mem_rman);
  303         if (err)
  304                 return (err);
  305 
  306         sc->sc_io_rman.rm_type = RMAN_ARRAY;
  307         err = rman_init(&sc->sc_io_rman);
  308         if (err) {
  309                 rman_fini(&sc->sc_mem_rman);
  310                 return (err);
  311         }
  312 
  313         err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base,
  314             sc->sc_mem_base + sc->sc_mem_size - 1);
  315         if (err)
  316                 goto error;
  317 
  318         err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base,
  319             sc->sc_io_base + sc->sc_io_size - 1);
  320         if (err)
  321                 goto error;
  322 
  323         err = mv_pcib_init(sc, sc->sc_busnr, mv_pcib_maxslots(sc->sc_dev));
  324         if (err)
  325                 goto error;
  326 
  327         device_add_child(self, "pci", -1);
  328         return (bus_generic_attach(self));
  329 
  330 error:
  331         /* XXX SYS_RES_ should be released here */
  332         rman_fini(&sc->sc_mem_rman);
  333         rman_fini(&sc->sc_io_rman);
  334         return (err);
  335 }
  336 
  337 static int
  338 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func,
  339     int barno)
  340 {
  341         bus_addr_t *allocp, limit;
  342         uint32_t addr, bar, mask, size;
  343         int reg, width;
  344 
  345         reg = PCIR_BAR(barno);
  346         bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
  347         if (bar == 0)
  348                 return (1);
  349 
  350         /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
  351         width = ((bar & 7) == 4) ? 2 : 1;
  352 
  353         mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
  354         size = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
  355 
  356         /* Get BAR type and size */
  357         if (bar & 1) {
  358                 /* I/O port */
  359                 allocp = &sc->sc_io_alloc;
  360                 limit = sc->sc_io_base + sc->sc_io_size;
  361                 size &= ~0x3;
  362                 if ((size & 0xffff0000) == 0)
  363                         size |= 0xffff0000;
  364         } else {
  365                 /* Memory */
  366                 allocp = &sc->sc_mem_alloc;
  367                 limit = sc->sc_mem_base + sc->sc_mem_size;
  368                 size &= ~0xF;
  369         }
  370         mask = ~size;
  371         size = mask + 1;
  372 
  373         /* Sanity check (must be a power of 2) */
  374         if (size & mask)
  375                 return (width);
  376 
  377         addr = (*allocp + mask) & ~mask;
  378         if ((*allocp = addr + size) > limit)
  379                 return (-1);
  380 
  381         if (bootverbose)
  382                 printf("PCI %u:%u:%u: reg %x: size=%08x: addr=%08x\n",
  383                     bus, slot, func, reg, size, addr);
  384 
  385         mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
  386         if (width == 2)
  387                 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
  388                     0, 4);
  389 
  390         return (width);
  391 }
  392 
  393 static void
  394 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func)
  395 {
  396         bus_addr_t io_base, mem_base;
  397         uint32_t io_limit, mem_limit;
  398         int secbus;
  399 
  400         io_base = sc->sc_io_base;
  401         io_limit = io_base + sc->sc_io_size - 1;
  402         mem_base = sc->sc_mem_base;
  403         mem_limit = mem_base + sc->sc_mem_size - 1;
  404 
  405         /* Configure I/O decode registers */
  406         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1,
  407             io_base >> 8, 1);
  408         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1,
  409             io_base >> 16, 2);
  410         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1,
  411             io_limit >> 8, 1);
  412         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1,
  413             io_limit >> 16, 2);
  414 
  415         /* Configure memory decode registers */
  416         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1,
  417             mem_base >> 16, 2);
  418         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1,
  419             mem_limit >> 16, 2);
  420 
  421         /* Disable memory prefetch decode */
  422         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1,
  423             0x10, 2);
  424         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1,
  425             0x0, 4);
  426         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1,
  427             0xF, 2);
  428         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1,
  429             0x0, 4);
  430 
  431         secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func,
  432             PCIR_SECBUS_1, 1);
  433 
  434         /* Configure buses behind the bridge */
  435         mv_pcib_init(sc, secbus, PCI_SLOTMAX);
  436 }
  437 
  438 static int
  439 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot)
  440 {
  441         int slot, func, maxfunc, error;
  442         uint8_t hdrtype, command, class, subclass;
  443 
  444         for (slot = 0; slot <= maxslot; slot++) {
  445                 maxfunc = 0;
  446                 for (func = 0; func <= maxfunc; func++) {
  447                         hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot,
  448                             func, PCIR_HDRTYPE, 1);
  449 
  450                         if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
  451                                 continue;
  452 
  453                         if (func == 0 && (hdrtype & PCIM_MFDEV))
  454                                 maxfunc = PCI_FUNCMAX;
  455 
  456                         command = mv_pcib_read_config(sc->sc_dev, bus, slot,
  457                             func, PCIR_COMMAND, 1);
  458                         command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
  459                         mv_pcib_write_config(sc->sc_dev, bus, slot, func,
  460                             PCIR_COMMAND, command, 1);
  461 
  462                         error = mv_pcib_init_all_bars(sc, bus, slot, func,
  463                             hdrtype);
  464 
  465                         if (error)
  466                                 return (error);
  467 
  468                         command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
  469                             PCIM_CMD_PORTEN;
  470                         mv_pcib_write_config(sc->sc_dev, bus, slot, func,
  471                             PCIR_COMMAND, command, 1);
  472 
  473                         /* Handle PCI-PCI bridges */
  474                         class = mv_pcib_read_config(sc->sc_dev, bus, slot,
  475                             func, PCIR_CLASS, 1);
  476                         subclass = mv_pcib_read_config(sc->sc_dev, bus, slot,
  477                             func, PCIR_SUBCLASS, 1);
  478 
  479                         if (class != PCIC_BRIDGE ||
  480                             subclass != PCIS_BRIDGE_PCI)
  481                                 continue;
  482 
  483                         mv_pcib_init_bridge(sc, bus, slot, func);
  484                 }
  485         }
  486 
  487         /* Enable all ABCD interrupts */
  488         pcib_write_irq_mask(sc, (0xF << 24));
  489 
  490         return (0);
  491 }
  492 
  493 static int
  494 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot,
  495     int func, int hdrtype)
  496 {
  497         int maxbar, bar, i;
  498 
  499         maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
  500         bar = 0;
  501 
  502         /* Program the base address registers */
  503         while (bar < maxbar) {
  504                 i = mv_pcib_init_bar(sc, bus, slot, func, bar);
  505                 bar += i;
  506                 if (i < 0) {
  507                         device_printf(sc->sc_dev,
  508                             "PCI IO/Memory space exhausted\n");
  509                         return (ENOMEM);
  510                 }
  511         }
  512 
  513         return (0);
  514 }
  515 
  516 static struct resource *
  517 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
  518     u_long start, u_long end, u_long count, u_int flags)
  519 {
  520         struct mv_pcib_softc *sc = device_get_softc(dev);
  521         struct rman *rm = NULL;
  522         struct resource *res;
  523 
  524         switch (type) {
  525         case SYS_RES_IOPORT:
  526                 rm = &sc->sc_io_rman;
  527                 break;
  528         case SYS_RES_MEMORY:
  529                 rm = &sc->sc_mem_rman;
  530                 break;
  531         default:
  532                 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
  533                     type, rid, start, end, count, flags));
  534         };
  535 
  536         res = rman_reserve_resource(rm, start, end, count, flags, child);
  537         if (res == NULL)
  538                 return (NULL);
  539 
  540         rman_set_rid(res, *rid);
  541         rman_set_bustag(res, fdtbus_bs_tag);
  542         rman_set_bushandle(res, start);
  543 
  544         if (flags & RF_ACTIVE)
  545                 if (bus_activate_resource(child, type, *rid, res)) {
  546                         rman_release_resource(res);
  547                         return (NULL);
  548                 }
  549 
  550         return (res);
  551 }
  552 
  553 static int
  554 mv_pcib_release_resource(device_t dev, device_t child, int type, int rid,
  555     struct resource *res)
  556 {
  557 
  558         if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY)
  559                 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
  560                     type, rid, res));
  561 
  562         return (rman_release_resource(res));
  563 }
  564 
  565 static int
  566 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
  567 {
  568         struct mv_pcib_softc *sc = device_get_softc(dev);
  569 
  570         switch (which) {
  571         case PCIB_IVAR_BUS:
  572                 *result = sc->sc_busnr;
  573                 return (0);
  574         case PCIB_IVAR_DOMAIN:
  575                 *result = device_get_unit(dev);
  576                 return (0);
  577         }
  578 
  579         return (ENOENT);
  580 }
  581 
  582 static int
  583 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
  584 {
  585         struct mv_pcib_softc *sc = device_get_softc(dev);
  586 
  587         switch (which) {
  588         case PCIB_IVAR_BUS:
  589                 sc->sc_busnr = value;
  590                 return (0);
  591         }
  592 
  593         return (ENOENT);
  594 }
  595 
  596 static inline void
  597 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask)
  598 {
  599 
  600         if (!sc->sc_type != MV_TYPE_PCI)
  601                 return;
  602 
  603         bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask);
  604 }
  605 
  606 static void
  607 mv_pcib_hw_cfginit(void)
  608 {
  609         static int opened = 0;
  610 
  611         if (opened)
  612                 return;
  613 
  614         mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
  615         opened = 1;
  616 }
  617 
  618 static uint32_t
  619 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot,
  620     u_int func, u_int reg, int bytes)
  621 {
  622         uint32_t addr, data, ca, cd;
  623 
  624         ca = (sc->sc_type != MV_TYPE_PCI) ?
  625             PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
  626         cd = (sc->sc_type != MV_TYPE_PCI) ?
  627             PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
  628         addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
  629             PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
  630 
  631         mtx_lock_spin(&pcicfg_mtx);
  632         bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
  633 
  634         data = ~0;
  635         switch (bytes) {
  636         case 1:
  637                 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
  638                     cd + (reg & 3));
  639                 break;
  640         case 2:
  641                 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
  642                     cd + (reg & 2)));
  643                 break;
  644         case 4:
  645                 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
  646                     cd));
  647                 break;
  648         }
  649         mtx_unlock_spin(&pcicfg_mtx);
  650         return (data);
  651 }
  652 
  653 static void
  654 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot,
  655     u_int func, u_int reg, uint32_t data, int bytes)
  656 {
  657         uint32_t addr, ca, cd;
  658 
  659         ca = (sc->sc_type != MV_TYPE_PCI) ?
  660             PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
  661         cd = (sc->sc_type != MV_TYPE_PCI) ?
  662             PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
  663         addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
  664             PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
  665 
  666         mtx_lock_spin(&pcicfg_mtx);
  667         bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
  668 
  669         switch (bytes) {
  670         case 1:
  671                 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
  672                     cd + (reg & 3), data);
  673                 break;
  674         case 2:
  675                 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
  676                     cd + (reg & 2), htole16(data));
  677                 break;
  678         case 4:
  679                 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
  680                     cd, htole32(data));
  681                 break;
  682         }
  683         mtx_unlock_spin(&pcicfg_mtx);
  684 }
  685 
  686 static int
  687 mv_pcib_maxslots(device_t dev)
  688 {
  689         struct mv_pcib_softc *sc = device_get_softc(dev);
  690 
  691         return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX);
  692 }
  693 
  694 static uint32_t
  695 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
  696     u_int reg, int bytes)
  697 {
  698         struct mv_pcib_softc *sc = device_get_softc(dev);
  699 
  700         /* Skip self */
  701         if (bus == sc->sc_busnr && slot == sc->sc_devnr)
  702                 return (~0U);
  703 
  704         return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes));
  705 }
  706 
  707 static void
  708 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
  709     u_int reg, uint32_t val, int bytes)
  710 {
  711         struct mv_pcib_softc *sc = device_get_softc(dev);
  712 
  713         /* Skip self */
  714         if (bus == sc->sc_busnr && slot == sc->sc_devnr)
  715                 return;
  716 
  717         mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);
  718 }
  719 
  720 static int
  721 mv_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
  722 {
  723         struct mv_pcib_softc *sc;
  724         int err, interrupt;
  725 
  726         sc = device_get_softc(pcib);
  727 
  728         err = fdt_pci_route_intr(pci_get_bus(dev), pci_get_slot(dev),
  729             pci_get_function(dev), pin, &sc->sc_intr_info, &interrupt);
  730         if (err == 0)
  731                 return (interrupt);
  732 
  733         device_printf(pcib, "could not route pin %d for device %d.%d\n",
  734             pin, pci_get_slot(dev), pci_get_function(dev));
  735         return (PCI_INVALID_IRQ);
  736 }
  737 
  738 static int
  739 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc)
  740 {
  741         struct fdt_pci_range io_space, mem_space;
  742         device_t dev;
  743         int error;
  744 
  745         dev = sc->sc_dev;
  746 
  747         if ((error = fdt_pci_ranges(node, &io_space, &mem_space)) != 0) {
  748                 device_printf(dev, "could not retrieve 'ranges' data\n");
  749                 return (error);
  750         }
  751 
  752         /* Configure CPU decoding windows */
  753         error = decode_win_cpu_set(sc->sc_io_win_target,
  754             sc->sc_io_win_attr, io_space.base_parent, io_space.len, -1);
  755         if (error < 0) {
  756                 device_printf(dev, "could not set up CPU decode "
  757                     "window for PCI IO\n");
  758                 return (ENXIO);
  759         }
  760         error = decode_win_cpu_set(sc->sc_mem_win_target,
  761             sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, -1);
  762         if (error < 0) {
  763                 device_printf(dev, "could not set up CPU decode "
  764                     "windows for PCI MEM\n");
  765                 return (ENXIO);
  766         }
  767 
  768         sc->sc_io_base = io_space.base_parent;
  769         sc->sc_io_size = io_space.len;
  770 
  771         sc->sc_mem_base = mem_space.base_parent;
  772         sc->sc_mem_size = mem_space.len;
  773 
  774         return (0);
  775 }
  776 
  777 static int
  778 mv_pcib_intr_info(phandle_t node, struct mv_pcib_softc *sc)
  779 {
  780         int error;
  781 
  782         if ((error = fdt_pci_intr_info(node, &sc->sc_intr_info)) != 0)
  783                 return (error);
  784 
  785         return (0);
  786 }
  787 
  788 #if 0
  789                 control = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
  790                     PCIE_REG_CONTROL);
  791 
  792                 /*
  793                  * If this PCI-E port (controller) is configured (by the
  794                  * underlying firmware) with lane width other than 1x, there
  795                  * are auxiliary resources defined for aggregating more width
  796                  * on our lane. Skip all such entries as they are not
  797                  * standalone ports and must not have a device object
  798                  * instantiated.
  799                  */
  800                 if ((control & PCIE_CTRL_LINK1X) == 0)
  801                         while (info->op_base &&
  802                             info->op_type == MV_TYPE_PCIE_AGGR_LANE)
  803                                 info++;
  804 
  805                 mv_pcib_add_child(driver, parent, sc);
  806 #endif

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