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sys/arm/mv/mvebu_gpio.c
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1 /*- 2 * Copyright (c) 2020 Michal Meloun <mmel@FreeBSD.org> 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 /* 30 * ARMADA 8040 GPIO driver. 31 */ 32 #include "opt_platform.h" 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/gpio.h> 37 #include <sys/kernel.h> 38 #include <sys/proc.h> 39 #include <sys/rman.h> 40 #include <sys/lock.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 #include <machine/resource.h> 47 48 #include <dev/extres/syscon/syscon.h> 49 50 #include <dev/gpio/gpiobusvar.h> 51 52 #include <dev/ofw/openfirm.h> 53 #include <dev/ofw/ofw_bus.h> 54 #include <dev/ofw/ofw_bus_subr.h> 55 56 #include "pic_if.h" 57 #include "syscon_if.h" 58 59 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx) 60 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 61 #define GPIO_LOCK_INIT(_sc) mtx_init(&_sc->mtx, \ 62 device_get_nameunit(_sc->dev), "mvebu_gpio", MTX_DEF) 63 #define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx); 64 #define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED); 65 #define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED); 66 67 #define GPIO_DATA_OUT 0x00 68 #define GPIO_CONTROL 0x04 69 #define GPIO_BLINK_ENA 0x08 70 #define GPIO_DATA_IN_POL 0x0C 71 #define GPIO_DATA_IN 0x10 72 #define GPIO_INT_CAUSE 0x14 73 #define GPIO_INT_MASK 0x18 74 #define GPIO_INT_LEVEL_MASK 0x1C 75 #define GPIO_CONTROL_SET 0x28 76 #define GPIO_CONTROL_CLR 0x2C 77 #define GPIO_DATA_SET 0x30 78 #define GPIO_DATA_CLR 0x34 79 80 #define GPIO_BIT(_p) ((_p) % 32) 81 #define GPIO_REGNUM(_p) ((_p) / 32) 82 83 #define MV_GPIO_MAX_NIRQS 4 84 #define MV_GPIO_MAX_NPINS 32 85 86 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) 87 #define WR4(sc, reg, val) SYSCON_WRITE_4((sc)->syscon, (reg), (val)) 88 89 struct mvebu_gpio_irqsrc { 90 struct intr_irqsrc isrc; 91 u_int irq; 92 bool is_level; 93 bool is_inverted; 94 }; 95 96 struct mvebu_gpio_softc; 97 struct mvebu_gpio_irq_cookie { 98 struct mvebu_gpio_softc *sc; 99 int bank_num; 100 }; 101 102 struct mvebu_gpio_softc { 103 device_t dev; 104 device_t busdev; 105 struct mtx mtx; 106 struct syscon *syscon; 107 uint32_t offset; 108 struct resource *irq_res[MV_GPIO_MAX_NIRQS]; 109 void *irq_ih[MV_GPIO_MAX_NIRQS]; 110 struct mvebu_gpio_irq_cookie irq_cookies[MV_GPIO_MAX_NIRQS]; 111 int gpio_npins; 112 struct gpio_pin gpio_pins[MV_GPIO_MAX_NPINS]; 113 struct mvebu_gpio_irqsrc *isrcs; 114 }; 115 116 static struct ofw_compat_data compat_data[] = { 117 {"marvell,armada-8k-gpio", 1}, 118 {NULL, 0} 119 }; 120 121 /* -------------------------------------------------------------------------- 122 * 123 * GPIO 124 * 125 */ 126 static inline void 127 gpio_write(struct mvebu_gpio_softc *sc, bus_size_t reg, 128 struct gpio_pin *pin, uint32_t val) 129 { 130 uint32_t tmp; 131 int bit; 132 133 bit = GPIO_BIT(pin->gp_pin); 134 tmp = 0x100 << bit; /* mask */ 135 tmp |= (val & 1) << bit; /* value */ 136 SYSCON_WRITE_4(sc->syscon, sc->offset + GPIO_REGNUM(pin->gp_pin) + reg, 137 tmp); 138 } 139 140 static inline uint32_t 141 gpio_read(struct mvebu_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin) 142 { 143 int bit; 144 uint32_t val; 145 146 bit = GPIO_BIT(pin->gp_pin); 147 val = SYSCON_READ_4(sc->syscon, 148 sc->offset + GPIO_REGNUM(pin->gp_pin) + reg); 149 return (val >> bit) & 1; 150 } 151 152 static void 153 mvebu_gpio_pin_configure(struct mvebu_gpio_softc *sc, struct gpio_pin *pin, 154 unsigned int flags) 155 { 156 157 if ((flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) == 0) 158 return; 159 160 /* Manage input/output */ 161 pin->gp_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 162 if (flags & GPIO_PIN_OUTPUT) { 163 pin->gp_flags |= GPIO_PIN_OUTPUT; 164 gpio_write(sc, GPIO_CONTROL_SET, pin, 1); 165 } else { 166 pin->gp_flags |= GPIO_PIN_INPUT; 167 gpio_write(sc, GPIO_CONTROL_CLR, pin, 1); 168 } 169 } 170 171 static device_t 172 mvebu_gpio_get_bus(device_t dev) 173 { 174 struct mvebu_gpio_softc *sc; 175 176 sc = device_get_softc(dev); 177 return (sc->busdev); 178 } 179 180 static int 181 mvebu_gpio_pin_max(device_t dev, int *maxpin) 182 { 183 struct mvebu_gpio_softc *sc; 184 185 sc = device_get_softc(dev); 186 *maxpin = sc->gpio_npins - 1; 187 return (0); 188 } 189 190 static int 191 mvebu_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 192 { 193 struct mvebu_gpio_softc *sc; 194 195 sc = device_get_softc(dev); 196 if (pin >= sc->gpio_npins) 197 return (EINVAL); 198 199 *caps = sc->gpio_pins[pin].gp_caps; 200 201 return (0); 202 } 203 204 static int 205 mvebu_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 206 { 207 struct mvebu_gpio_softc *sc; 208 209 sc = device_get_softc(dev); 210 if (pin >= sc->gpio_npins) 211 return (EINVAL); 212 213 *flags = sc->gpio_pins[pin].gp_flags; 214 215 return (0); 216 } 217 218 static int 219 mvebu_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 220 { 221 struct mvebu_gpio_softc *sc; 222 223 sc = device_get_softc(dev); 224 if (pin >= sc->gpio_npins) 225 return (EINVAL); 226 227 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME); 228 229 return (0); 230 } 231 232 static int 233 mvebu_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 234 { 235 struct mvebu_gpio_softc *sc; 236 237 sc = device_get_softc(dev); 238 if (pin >= sc->gpio_npins) 239 return (EINVAL); 240 241 242 mvebu_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags); 243 244 return (0); 245 } 246 247 static int 248 mvebu_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 249 { 250 struct mvebu_gpio_softc *sc; 251 252 sc = device_get_softc(dev); 253 if (pin >= sc->gpio_npins) 254 return (EINVAL); 255 256 if (value != 0) 257 gpio_write(sc, GPIO_DATA_SET, &sc->gpio_pins[pin], 1); 258 else 259 gpio_write(sc, GPIO_DATA_CLR, &sc->gpio_pins[pin], 1); 260 261 return (0); 262 } 263 264 static int 265 mvebu_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 266 { 267 struct mvebu_gpio_softc *sc; 268 269 sc = device_get_softc(dev); 270 if (pin >= sc->gpio_npins) 271 return (EINVAL); 272 273 GPIO_LOCK(sc); 274 *val = gpio_read(sc, GPIO_DATA_IN, &sc->gpio_pins[pin]); 275 *val ^= gpio_read(sc, GPIO_DATA_IN_POL, &sc->gpio_pins[pin]); 276 GPIO_UNLOCK(sc); 277 278 return (0); 279 } 280 281 static int 282 mvebu_gpio_pin_toggle(device_t dev, uint32_t pin) 283 { 284 struct mvebu_gpio_softc *sc; 285 uint32_t val; 286 287 sc = device_get_softc(dev); 288 if (pin >= sc->gpio_npins) 289 return (EINVAL); 290 291 GPIO_LOCK(sc); 292 mvebu_gpio_pin_get(sc->dev, pin, &val); 293 if (val != 0) 294 gpio_write(sc, GPIO_DATA_CLR, &sc->gpio_pins[pin], 1); 295 else 296 gpio_write(sc, GPIO_DATA_SET, &sc->gpio_pins[pin], 1); 297 GPIO_UNLOCK(sc); 298 299 return (0); 300 } 301 302 303 /* -------------------------------------------------------------------------- 304 * 305 * Interrupts 306 * 307 */ 308 static inline void 309 intr_modify(struct mvebu_gpio_softc *sc, bus_addr_t reg, 310 struct mvebu_gpio_irqsrc *mgi, uint32_t val, uint32_t mask) 311 { 312 int bit; 313 314 bit = GPIO_BIT(mgi->irq); 315 GPIO_LOCK(sc); 316 val = SYSCON_MODIFY_4(sc->syscon, 317 sc->offset + GPIO_REGNUM(mgi->irq) + reg, val, mask); 318 GPIO_UNLOCK(sc); 319 } 320 321 static inline void 322 mvebu_gpio_isrc_mask(struct mvebu_gpio_softc *sc, 323 struct mvebu_gpio_irqsrc *mgi, uint32_t val) 324 { 325 326 if (mgi->is_level) 327 intr_modify(sc, GPIO_INT_LEVEL_MASK, mgi, val, 1); 328 else 329 intr_modify(sc, GPIO_INT_MASK, mgi, val, 1); 330 } 331 332 static inline void 333 mvebu_gpio_isrc_eoi(struct mvebu_gpio_softc *sc, 334 struct mvebu_gpio_irqsrc *mgi) 335 { 336 337 if (!mgi->is_level) 338 intr_modify(sc, GPIO_INT_CAUSE, mgi, 1, 1); 339 } 340 341 342 static int 343 mvebu_gpio_pic_attach(struct mvebu_gpio_softc *sc) 344 { 345 int rv; 346 uint32_t irq; 347 const char *name; 348 349 sc->isrcs = malloc(sizeof(*sc->isrcs) * sc->gpio_npins, M_DEVBUF, 350 M_WAITOK | M_ZERO); 351 352 name = device_get_nameunit(sc->dev); 353 for (irq = 0; irq < sc->gpio_npins; irq++) { 354 sc->isrcs[irq].irq = irq; 355 sc->isrcs[irq].is_level = false; 356 sc->isrcs[irq].is_inverted = false; 357 rv = intr_isrc_register(&sc->isrcs[irq].isrc, 358 sc->dev, 0, "%s,%u", name, irq); 359 if (rv != 0) 360 return (rv); /* XXX deregister ISRCs */ 361 } 362 if (intr_pic_register(sc->dev, 363 OF_xref_from_node(ofw_bus_get_node(sc->dev))) == NULL) 364 return (ENXIO); 365 366 return (0); 367 } 368 369 static int 370 mvebu_gpio_pic_detach(struct mvebu_gpio_softc *sc) 371 { 372 373 /* 374 * There has not been established any procedure yet 375 * how to detach PIC from living system correctly. 376 */ 377 device_printf(sc->dev, "%s: not implemented yet\n", __func__); 378 return (EBUSY); 379 } 380 381 382 static void 383 mvebu_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 384 { 385 struct mvebu_gpio_softc *sc; 386 struct mvebu_gpio_irqsrc *mgi; 387 388 sc = device_get_softc(dev); 389 mgi = (struct mvebu_gpio_irqsrc *)isrc; 390 mvebu_gpio_isrc_mask(sc, mgi, 0); 391 } 392 393 static void 394 mvebu_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 395 { 396 struct mvebu_gpio_softc *sc; 397 struct mvebu_gpio_irqsrc *mgi; 398 399 sc = device_get_softc(dev); 400 mgi = (struct mvebu_gpio_irqsrc *)isrc; 401 mvebu_gpio_isrc_mask(sc, mgi, 1); 402 } 403 404 static int 405 mvebu_gpio_pic_map_fdt(struct mvebu_gpio_softc *sc, u_int ncells, 406 pcell_t *cells, u_int *irqp, bool *invertedp, bool *levelp) 407 { 408 bool inverted, level; 409 410 /* 411 * The first cell is the interrupt number. 412 * The second cell is used to specify flags: 413 * bits[3:0] trigger type and level flags: 414 * 1 = low-to-high edge triggered. 415 * 2 = high-to-low edge triggered. 416 * 4 = active high level-sensitive. 417 * 8 = active low level-sensitive. 418 */ 419 if (ncells != 2 || cells[0] >= sc->gpio_npins) 420 return (EINVAL); 421 422 423 switch (cells[1]) { 424 case 1: 425 inverted = false; 426 level = false; 427 break; 428 case 2: 429 inverted = true; 430 level = false; 431 break; 432 case 4: 433 inverted = false; 434 level = true; 435 break; 436 case 8: 437 inverted = true; 438 level = true; 439 break; 440 default: 441 return (EINVAL); 442 } 443 *irqp = cells[0]; 444 if (invertedp != NULL) 445 *invertedp = inverted; 446 if (levelp != NULL) 447 *levelp = level; 448 return (0); 449 } 450 451 452 static int 453 mvebu_gpio_pic_map_gpio(struct mvebu_gpio_softc *sc, u_int gpio_pin_num, 454 u_int gpio_pin_flags, u_int intr_mode, u_int *irqp, bool *invertedp, 455 bool *levelp) 456 { 457 bool inverted, level; 458 459 if (gpio_pin_num >= sc->gpio_npins) 460 return (EINVAL); 461 462 switch (intr_mode) { 463 case GPIO_INTR_LEVEL_LOW: 464 inverted = true; 465 level = true; 466 break; 467 case GPIO_INTR_LEVEL_HIGH: 468 inverted = false; 469 level = true; 470 break; 471 case GPIO_INTR_CONFORM: 472 case GPIO_INTR_EDGE_RISING: 473 inverted = false; 474 level = false; 475 break; 476 case GPIO_INTR_EDGE_FALLING: 477 inverted = true; 478 level = false; 479 break; 480 default: 481 return (EINVAL); 482 } 483 *irqp = gpio_pin_num; 484 if (invertedp != NULL) 485 *invertedp = inverted; 486 if (levelp != NULL) 487 *levelp = level; 488 return (0); 489 } 490 491 static int 492 mvebu_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 493 struct intr_irqsrc **isrcp) 494 { 495 int rv; 496 u_int irq; 497 struct mvebu_gpio_softc *sc; 498 499 sc = device_get_softc(dev); 500 501 if (data->type == INTR_MAP_DATA_FDT) { 502 struct intr_map_data_fdt *daf; 503 504 daf = (struct intr_map_data_fdt *)data; 505 rv = mvebu_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq, 506 NULL, NULL); 507 } else if (data->type == INTR_MAP_DATA_GPIO) { 508 struct intr_map_data_gpio *dag; 509 510 dag = (struct intr_map_data_gpio *)data; 511 rv = mvebu_gpio_pic_map_gpio(sc, dag->gpio_pin_num, 512 dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, NULL, NULL); 513 } else 514 return (ENOTSUP); 515 516 if (rv == 0) 517 *isrcp = &sc->isrcs[irq].isrc; 518 return (rv); 519 } 520 521 static void 522 mvebu_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 523 { 524 struct mvebu_gpio_softc *sc; 525 struct mvebu_gpio_irqsrc *mgi; 526 527 sc = device_get_softc(dev); 528 mgi = (struct mvebu_gpio_irqsrc *)isrc; 529 if (mgi->is_level) 530 mvebu_gpio_isrc_eoi(sc, mgi); 531 } 532 533 static void 534 mvebu_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 535 { 536 struct mvebu_gpio_softc *sc; 537 struct mvebu_gpio_irqsrc *mgi; 538 539 sc = device_get_softc(dev); 540 mgi = (struct mvebu_gpio_irqsrc *)isrc; 541 mvebu_gpio_isrc_mask(sc, mgi, 1); 542 } 543 544 static void 545 mvebu_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 546 { 547 struct mvebu_gpio_softc *sc; 548 struct mvebu_gpio_irqsrc *mgi; 549 550 sc = device_get_softc(dev); 551 mgi = (struct mvebu_gpio_irqsrc *)isrc; 552 553 mvebu_gpio_isrc_mask(sc, mgi, 0); 554 if (mgi->is_level) 555 mvebu_gpio_isrc_eoi(sc, mgi); 556 } 557 558 static int 559 mvebu_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 560 struct resource *res, struct intr_map_data *data) 561 { 562 u_int irq; 563 bool inverted, level; 564 int rv; 565 struct mvebu_gpio_softc *sc; 566 struct mvebu_gpio_irqsrc *mgi; 567 568 sc = device_get_softc(dev); 569 mgi = (struct mvebu_gpio_irqsrc *)isrc; 570 571 if (data == NULL) 572 return (ENOTSUP); 573 574 /* Get and check config for an interrupt. */ 575 if (data->type == INTR_MAP_DATA_FDT) { 576 struct intr_map_data_fdt *daf; 577 578 daf = (struct intr_map_data_fdt *)data; 579 rv = mvebu_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq, 580 &inverted, &level); 581 } else if (data->type == INTR_MAP_DATA_GPIO) { 582 struct intr_map_data_gpio *dag; 583 584 dag = (struct intr_map_data_gpio *)data; 585 rv = mvebu_gpio_pic_map_gpio(sc, dag->gpio_pin_num, 586 dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, 587 &inverted, &level); 588 } else 589 return (ENOTSUP); 590 591 if (rv != 0) 592 return (EINVAL); 593 594 /* 595 * If this is a setup for another handler, 596 * only check that its configuration match. 597 */ 598 if (isrc->isrc_handlers != 0) 599 return ( 600 mgi->is_level == level && mgi->is_inverted == inverted ? 601 0 : EINVAL); 602 603 mgi->is_level = level; 604 mgi->is_inverted = inverted; 605 intr_modify(sc, GPIO_DATA_IN_POL, mgi, inverted ? 1 : 0, 1); 606 mvebu_gpio_pic_enable_intr(dev, isrc); 607 608 return (0); 609 } 610 611 static int 612 mvebu_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 613 struct resource *res, struct intr_map_data *data) 614 { 615 struct mvebu_gpio_softc *sc; 616 struct mvebu_gpio_irqsrc *mgi; 617 618 sc = device_get_softc(dev); 619 mgi = (struct mvebu_gpio_irqsrc *)isrc; 620 621 if (isrc->isrc_handlers == 0) 622 mvebu_gpio_isrc_mask(sc, mgi, 0); 623 return (0); 624 } 625 626 /* -------------------------------------------------------------------------- 627 * 628 * Bus 629 * 630 */ 631 632 static int 633 mvebu_gpio_intr(void *arg) 634 { 635 u_int i, lvl, edge; 636 struct mvebu_gpio_softc *sc; 637 struct trapframe *tf; 638 struct mvebu_gpio_irqsrc *mgi; 639 struct mvebu_gpio_irq_cookie *cookie; 640 641 642 cookie = (struct mvebu_gpio_irq_cookie *)arg; 643 sc = cookie->sc; 644 tf = curthread->td_intr_frame; 645 646 for (i = 0; i < sc->gpio_npins; i++) { 647 lvl = gpio_read(sc, GPIO_DATA_IN, &sc->gpio_pins[i]); 648 lvl &= gpio_read(sc, GPIO_INT_LEVEL_MASK, &sc->gpio_pins[i]); 649 edge = gpio_read(sc, GPIO_DATA_IN, &sc->gpio_pins[i]); 650 edge &= gpio_read(sc, GPIO_INT_LEVEL_MASK, &sc->gpio_pins[i]); 651 if (edge == 0 || lvl == 0) 652 continue; 653 654 mgi = &sc->isrcs[i]; 655 if (!mgi->is_level) 656 mvebu_gpio_isrc_eoi(sc, mgi); 657 if (intr_isrc_dispatch(&mgi->isrc, tf) != 0) { 658 mvebu_gpio_isrc_mask(sc, mgi, 0); 659 if (mgi->is_level) 660 mvebu_gpio_isrc_eoi(sc, mgi); 661 device_printf(sc->dev, 662 "Stray irq %u disabled\n", mgi->irq); 663 } 664 } 665 return (FILTER_HANDLED); 666 } 667 668 static int 669 mvebu_gpio_probe(device_t dev) 670 { 671 672 if (!ofw_bus_status_okay(dev)) 673 return (ENXIO); 674 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 675 return (ENXIO); 676 677 device_set_desc(dev, "Marvell Integrated GPIO Controller"); 678 return (0); 679 } 680 681 static int 682 mvebu_gpio_detach(device_t dev) 683 { 684 struct mvebu_gpio_softc *sc; 685 int i; 686 687 sc = device_get_softc(dev); 688 689 KASSERT(mtx_initialized(&sc->mtx), ("gpio mutex not initialized")); 690 691 for (i = 0; i < MV_GPIO_MAX_NIRQS; i++) { 692 if (sc->irq_ih[i] != NULL) 693 bus_teardown_intr(dev, sc->irq_res[i], sc->irq_ih[i]); 694 } 695 696 if (sc->isrcs != NULL) 697 mvebu_gpio_pic_detach(sc); 698 699 gpiobus_detach_bus(dev); 700 701 for (i = 0; i < MV_GPIO_MAX_NIRQS; i++) { 702 if (sc->irq_res[i] != NULL) 703 bus_release_resource(dev, SYS_RES_IRQ, 0, 704 sc->irq_res[i]); 705 } 706 GPIO_LOCK_DESTROY(sc); 707 708 return(0); 709 } 710 711 static int 712 mvebu_gpio_attach(device_t dev) 713 { 714 struct mvebu_gpio_softc *sc; 715 phandle_t node; 716 struct gpio_pin *pin; 717 pcell_t pincnt; 718 int i, rv, rid; 719 720 sc = device_get_softc(dev); 721 sc->dev = dev; 722 node = ofw_bus_get_node(dev); 723 724 GPIO_LOCK_INIT(sc); 725 726 pincnt = 0; 727 rv = OF_getencprop(node, "ngpios", &pincnt, sizeof(pcell_t)); 728 if (rv < 0) { 729 device_printf(dev, 730 "ERROR: no pin-count or ngpios entry found!\n"); 731 return (ENXIO); 732 } 733 734 sc->gpio_npins = MIN(pincnt, MV_GPIO_MAX_NPINS); 735 if (bootverbose) 736 device_printf(dev, 737 "%d pins available\n", sc->gpio_npins); 738 739 rv = OF_getencprop(node, "offset", &sc->offset, sizeof(sc->offset)); 740 if (rv == -1) { 741 device_printf(dev, "ERROR: no 'offset' property found!\n"); 742 return (ENXIO); 743 } 744 745 if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 || 746 sc->syscon == NULL) { 747 device_printf(dev, "ERROR: cannot get syscon handle!\n"); 748 return (ENXIO); 749 } 750 751 /* Allocate interrupts. */ 752 for (i = 0; i < MV_GPIO_MAX_NIRQS; i++) { 753 sc->irq_cookies[i].sc = sc; 754 sc->irq_cookies[i].bank_num = i; 755 rid = i; 756 sc->irq_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ, 757 &rid, RF_ACTIVE); 758 if (sc->irq_res[i] == NULL) 759 break; 760 if ((bus_setup_intr(dev, sc->irq_res[i], 761 INTR_TYPE_MISC | INTR_MPSAFE, mvebu_gpio_intr, NULL, 762 &sc->irq_cookies[i], &sc->irq_ih[i]))) { 763 device_printf(dev, 764 "WARNING: unable to register interrupt handler\n"); 765 mvebu_gpio_detach(dev); 766 return (ENXIO); 767 } 768 } 769 770 /* Init GPIO pins */ 771 for (i = 0; i < sc->gpio_npins; i++) { 772 pin = sc->gpio_pins + i; 773 pin->gp_pin = i; 774 if (sc->irq_res[0] != NULL) 775 pin->gp_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 776 GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | 777 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING; 778 else 779 pin->gp_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 780 pin->gp_flags = 781 gpio_read(sc, GPIO_CONTROL, &sc->gpio_pins[i]) != 0 ? 782 GPIO_PIN_OUTPUT : GPIO_PIN_INPUT; 783 snprintf(pin->gp_name, GPIOMAXNAME, "gpio%d", i); 784 785 /* Init HW */ 786 gpio_write(sc, GPIO_INT_MASK, pin, 0); 787 gpio_write(sc, GPIO_INT_LEVEL_MASK, pin, 0); 788 gpio_write(sc, GPIO_INT_CAUSE, pin, 1); 789 gpio_write(sc, GPIO_DATA_IN_POL, pin, 1); 790 gpio_write(sc, GPIO_BLINK_ENA, pin, 0); 791 } 792 793 if (sc->irq_res[0] != NULL) { 794 rv = mvebu_gpio_pic_attach(sc); 795 if (rv != 0) { 796 device_printf(dev, "WARNING: unable to attach PIC\n"); 797 mvebu_gpio_detach(dev); 798 return (rv); 799 } 800 } 801 802 sc->busdev = gpiobus_attach_bus(dev); 803 if (sc->busdev == NULL) { 804 mvebu_gpio_detach(dev); 805 return (ENXIO); 806 } 807 808 return (bus_generic_attach(dev)); 809 } 810 811 static int 812 mvebu_gpio_map_gpios(device_t dev, phandle_t pdev, phandle_t gparent, 813 int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags) 814 { 815 816 if (gcells != 2) 817 return (ERANGE); 818 *pin = gpios[0]; 819 *flags= gpios[1]; 820 return (0); 821 } 822 823 static phandle_t 824 mvebu_gpio_get_node(device_t bus, device_t dev) 825 { 826 827 /* We only have one child, the GPIO bus, which needs our own node. */ 828 return (ofw_bus_get_node(bus)); 829 } 830 831 static device_method_t mvebu_gpio_methods[] = { 832 DEVMETHOD(device_probe, mvebu_gpio_probe), 833 DEVMETHOD(device_attach, mvebu_gpio_attach), 834 DEVMETHOD(device_detach, mvebu_gpio_detach), 835 836 /* Interrupt controller interface */ 837 DEVMETHOD(pic_disable_intr, mvebu_gpio_pic_disable_intr), 838 DEVMETHOD(pic_enable_intr, mvebu_gpio_pic_enable_intr), 839 DEVMETHOD(pic_map_intr, mvebu_gpio_pic_map_intr), 840 DEVMETHOD(pic_setup_intr, mvebu_gpio_pic_setup_intr), 841 DEVMETHOD(pic_teardown_intr, mvebu_gpio_pic_teardown_intr), 842 DEVMETHOD(pic_post_filter, mvebu_gpio_pic_post_filter), 843 DEVMETHOD(pic_post_ithread, mvebu_gpio_pic_post_ithread), 844 DEVMETHOD(pic_pre_ithread, mvebu_gpio_pic_pre_ithread), 845 846 /* GPIO protocol */ 847 DEVMETHOD(gpio_get_bus, mvebu_gpio_get_bus), 848 DEVMETHOD(gpio_pin_max, mvebu_gpio_pin_max), 849 DEVMETHOD(gpio_pin_getname, mvebu_gpio_pin_getname), 850 DEVMETHOD(gpio_pin_getflags, mvebu_gpio_pin_getflags), 851 DEVMETHOD(gpio_pin_getcaps, mvebu_gpio_pin_getcaps), 852 DEVMETHOD(gpio_pin_setflags, mvebu_gpio_pin_setflags), 853 DEVMETHOD(gpio_pin_get, mvebu_gpio_pin_get), 854 DEVMETHOD(gpio_pin_set, mvebu_gpio_pin_set), 855 DEVMETHOD(gpio_pin_toggle, mvebu_gpio_pin_toggle), 856 DEVMETHOD(gpio_map_gpios, mvebu_gpio_map_gpios), 857 858 /* ofw_bus interface */ 859 DEVMETHOD(ofw_bus_get_node, mvebu_gpio_get_node), 860 861 DEVMETHOD_END 862 }; 863 864 static devclass_t mvebu_gpio_devclass; 865 static DEFINE_CLASS_0(gpio, mvebu_gpio_driver, mvebu_gpio_methods, 866 sizeof(struct mvebu_gpio_softc)); 867 EARLY_DRIVER_MODULE(mvebu_gpio, simplebus, mvebu_gpio_driver, 868 mvebu_gpio_devclass, NULL, NULL, 869 BUS_PASS_TIMER + BUS_PASS_ORDER_LAST);
Cache object: 9a2153708ac4de721d94f5738d5db95e
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