The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/mvreg.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-3-Clause
    3  *
    4  * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
    5  * All rights reserved.
    6  *
    7  * Developed by Semihalf.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. Neither the name of MARVELL nor the names of contributors
   18  *    may be used to endorse or promote products derived from this software
   19  *    without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   24  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   31  * SUCH DAMAGE.
   32  *
   33  * $FreeBSD: releng/12.0/sys/arm/mv/mvreg.h 332024 2018-04-04 13:20:29Z mw $
   34  */
   35 
   36 #ifndef _MVREG_H_
   37 #define _MVREG_H_
   38 
   39 #include <arm/mv/mvwin.h>
   40 
   41 #if defined(SOC_MV_DISCOVERY)
   42 #define IRQ_CAUSE_ERROR         0x0
   43 #define IRQ_CAUSE               0x4
   44 #define IRQ_CAUSE_HI            0x8
   45 #define IRQ_MASK_ERROR          0xC
   46 #define IRQ_MASK                0x10
   47 #define IRQ_MASK_HI             0x14
   48 #define IRQ_CAUSE_SELECT        0x18
   49 #define FIQ_MASK_ERROR          0x1C
   50 #define FIQ_MASK                0x20
   51 #define FIQ_MASK_HI             0x24
   52 #define FIQ_CAUSE_SELECT        0x28
   53 #define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C
   54 #define ENDPOINT_IRQ_MASK(n)    0x30
   55 #define ENDPOINT_IRQ_MASK_HI(n) 0x34
   56 #define ENDPOINT_IRQ_CAUSE_SELECT 0x38
   57 #else
   58 #define IRQ_CAUSE               0x0
   59 #define IRQ_MASK                0x4
   60 #define FIQ_MASK                0x8
   61 #define ENDPOINT_IRQ_MASK(n)    0xC
   62 #define IRQ_CAUSE_HI            0x10
   63 #define IRQ_MASK_HI             0x14
   64 #define FIQ_MASK_HI             0x18
   65 #define ENDPOINT_IRQ_MASK_HI(n) 0x1C
   66 #define ENDPOINT_IRQ_MASK_ERROR(n) (-1)
   67 #define IRQ_CAUSE_ERROR         (-1)            /* Fake defines for unified */
   68 #define IRQ_MASK_ERROR          (-1)            /* interrupt controller code */
   69 #endif
   70 
   71 #define MAIN_IRQ_NUM            116
   72 #define ERR_IRQ_NUM             32
   73 #define ERR_IRQ                 (MAIN_IRQ_NUM)
   74 #define MSI_IRQ                 (ERR_IRQ + ERR_IRQ_NUM)
   75 
   76 #define MSI_IRQ_NUM             32
   77 
   78 #define IRQ_CPU_SELF            0x00000001
   79 #define BRIDGE_IRQ_CAUSE_ARMADAXP       0x68
   80 #define IRQ_TIMER0_ARMADAXP             0x00000001
   81 #define IRQ_TIMER1_ARMADAXP             0x00000002
   82 #define IRQ_TIMER_WD_ARMADAXP           0x00000004
   83 
   84 #define BRIDGE_IRQ_CAUSE        0x10
   85 #define IRQ_CPU_SELF            0x00000001
   86 #define IRQ_TIMER0              0x00000002
   87 #define IRQ_TIMER1              0x00000004
   88 #define IRQ_TIMER_WD            0x00000008
   89 
   90 #define BRIDGE_IRQ_MASK         0x14
   91 #define IRQ_CPU_MASK            0x00000001
   92 #define IRQ_TIMER0_MASK         0x00000002
   93 #define IRQ_TIMER1_MASK         0x00000004
   94 #define IRQ_TIMER_WD_MASK       0x00000008
   95 
   96 #define IRQ_CPU_SELF_CLR        (~IRQ_CPU_SELF)
   97 #define IRQ_TIMER0_CLR          (~IRQ_TIMER0)
   98 #define IRQ_TIMER_WD_CLR        (~IRQ_TIMER_WD)
   99 
  100 #define IRQ_TIMER0_CLR_ARMADAXP         (~IRQ_TIMER0_ARMADAXP)
  101 #define IRQ_TIMER_WD_CLR_ARMADAXP       (~IRQ_TIMER_WD_ARMADAXP)
  102 
  103 /*
  104  * System reset
  105  */
  106 #define RSTOUTn_MASK_ARMV7      0x60
  107 #define SYSTEM_SOFT_RESET_ARMV7 0x64
  108 #define SOFT_RST_OUT_EN_ARMV7   0x00000001
  109 #define SYS_SOFT_RST_ARMV7      0x00000001
  110 
  111 #define RSTOUTn_MASK            0x8
  112 #define SOFT_RST_OUT_EN         0x00000004
  113 #define SYSTEM_SOFT_RESET       0xc
  114 #define SYS_SOFT_RST            0x00000001
  115 #define RSTOUTn_MASK_WD         0x400
  116 #define WD_RSTOUTn_MASK         0x4
  117 #define WD_GLOBAL_MASK          0x00000100
  118 #define WD_CPU0_MASK            0x00000001
  119 #define WD_RST_OUT_EN           0x00000002
  120 
  121 /*
  122  * Power Control
  123  */
  124 #if defined(SOC_MV_KIRKWOOD)
  125 #define CPU_PM_CTRL             0x18
  126 #else
  127 #define CPU_PM_CTRL             0x1C
  128 #endif
  129 #define CPU_PM_CTRL_NONE        0
  130 #define CPU_PM_CTRL_ALL         ~0x0
  131 
  132 #if defined(SOC_MV_KIRKWOOD)
  133 #define CPU_PM_CTRL_GE0         (1 << 0)
  134 #define CPU_PM_CTRL_PEX0_PHY    (1 << 1)
  135 #define CPU_PM_CTRL_PEX0        (1 << 2)
  136 #define CPU_PM_CTRL_USB0        (1 << 3)
  137 #define CPU_PM_CTRL_SDIO        (1 << 4)
  138 #define CPU_PM_CTRL_TSU         (1 << 5)
  139 #define CPU_PM_CTRL_DUNIT       (1 << 6)
  140 #define CPU_PM_CTRL_RUNIT       (1 << 7)
  141 #define CPU_PM_CTRL_XOR0        (1 << 8)
  142 #define CPU_PM_CTRL_AUDIO       (1 << 9)
  143 #define CPU_PM_CTRL_SATA0       (1 << 14)
  144 #define CPU_PM_CTRL_SATA1       (1 << 15)
  145 #define CPU_PM_CTRL_XOR1        (1 << 16)
  146 #define CPU_PM_CTRL_CRYPTO      (1 << 17)
  147 #define CPU_PM_CTRL_GE1         (1 << 19)
  148 #define CPU_PM_CTRL_TDM         (1 << 20)
  149 #define CPU_PM_CTRL_XOR         (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1)
  150 #define CPU_PM_CTRL_USB(u)      (CPU_PM_CTRL_USB0)
  151 #define CPU_PM_CTRL_SATA        (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1)
  152 #define CPU_PM_CTRL_GE(u)       (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \
  153                                 (1 - (u)))
  154 #define CPU_PM_CTRL_IDMA        (CPU_PM_CTRL_NONE)
  155 #elif defined(SOC_MV_DISCOVERY)
  156 #define CPU_PM_CTRL_GE0         (1 << 1)
  157 #define CPU_PM_CTRL_GE1         (1 << 2)
  158 #define CPU_PM_CTRL_PEX00       (1 << 5)
  159 #define CPU_PM_CTRL_PEX01       (1 << 6)
  160 #define CPU_PM_CTRL_PEX02       (1 << 7)
  161 #define CPU_PM_CTRL_PEX03       (1 << 8)
  162 #define CPU_PM_CTRL_PEX10       (1 << 9)
  163 #define CPU_PM_CTRL_PEX11       (1 << 10)
  164 #define CPU_PM_CTRL_PEX12       (1 << 11)
  165 #define CPU_PM_CTRL_PEX13       (1 << 12)
  166 #define CPU_PM_CTRL_SATA0_PHY   (1 << 13)
  167 #define CPU_PM_CTRL_SATA0       (1 << 14)
  168 #define CPU_PM_CTRL_SATA1_PHY   (1 << 15)
  169 #define CPU_PM_CTRL_SATA1       (1 << 16)
  170 #define CPU_PM_CTRL_USB0        (1 << 17)
  171 #define CPU_PM_CTRL_USB1        (1 << 18)
  172 #define CPU_PM_CTRL_USB2        (1 << 19)
  173 #define CPU_PM_CTRL_IDMA        (1 << 20)
  174 #define CPU_PM_CTRL_XOR         (1 << 21)
  175 #define CPU_PM_CTRL_CRYPTO      (1 << 22)
  176 #define CPU_PM_CTRL_DEVICE      (1 << 23)
  177 #define CPU_PM_CTRL_USB(u)      (1 << (17 + (u)))
  178 #define CPU_PM_CTRL_SATA        (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1)
  179 #define CPU_PM_CTRL_GE(u)       (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \
  180                                 (1 - (u)))
  181 #else
  182 #define CPU_PM_CTRL_CRYPTO      (CPU_PM_CTRL_NONE)
  183 #define CPU_PM_CTRL_IDMA        (CPU_PM_CTRL_NONE)
  184 #define CPU_PM_CTRL_XOR         (CPU_PM_CTRL_NONE)
  185 #define CPU_PM_CTRL_SATA        (CPU_PM_CTRL_NONE)
  186 #define CPU_PM_CTRL_USB(u)      (CPU_PM_CTRL_NONE)
  187 #define CPU_PM_CTRL_GE(u)       (CPU_PM_CTRL_NONE)
  188 #endif
  189 
  190 /*
  191  * Timers
  192  */
  193 #define CPU_TIMERS_BASE         0x300
  194 #define CPU_TIMER_CONTROL       0x0
  195 #define CPU_TIMER0_EN           0x00000001
  196 #define CPU_TIMER0_AUTO         0x00000002
  197 #define CPU_TIMER1_EN           0x00000004
  198 #define CPU_TIMER1_AUTO         0x00000008
  199 #define CPU_TIMER2_EN           0x00000010
  200 #define CPU_TIMER2_AUTO         0x00000020
  201 #define CPU_TIMER_WD_EN         0x00000100
  202 #define CPU_TIMER_WD_AUTO       0x00000200
  203 /* 25MHz mode is Armada XP - specific */
  204 #define CPU_TIMER_WD_25MHZ_EN   0x00000400
  205 #define CPU_TIMER0_25MHZ_EN     0x00000800
  206 #define CPU_TIMER1_25MHZ_EN     0x00001000
  207 #define CPU_TIMER0_REL          0x10
  208 #define CPU_TIMER0              0x14
  209 
  210 /*
  211  * SATA
  212  */
  213 #define SATA_CHAN_NUM                   2
  214 
  215 #define EDMA_REGISTERS_OFFSET           0x2000
  216 #define EDMA_REGISTERS_SIZE             0x2000
  217 #define SATA_EDMA_BASE(ch)              (EDMA_REGISTERS_OFFSET + \
  218     ((ch) * EDMA_REGISTERS_SIZE))
  219 
  220 /* SATAHC registers */
  221 #define SATA_CR                         0x000 /* Configuration Reg. */
  222 #define SATA_CR_NODMABS                 (1 << 8)
  223 #define SATA_CR_NOEDMABS                (1 << 9)
  224 #define SATA_CR_NOPRDPBS                (1 << 10)
  225 #define SATA_CR_COALDIS(ch)             (1 << (24 + ch))
  226 
  227 /* Interrupt Coalescing Threshold Reg. */
  228 #define SATA_ICTR                       0x00C
  229 #define SATA_ICTR_MAX                   ((1 << 8) - 1)
  230 
  231 /* Interrupt Time Threshold Reg. */
  232 #define SATA_ITTR                       0x010
  233 #define SATA_ITTR_MAX                   ((1 << 24) - 1)
  234 
  235 #define SATA_ICR                        0x014 /* Interrupt Cause Reg. */
  236 #define SATA_ICR_DMADONE(ch)            (1 << (ch))
  237 #define SATA_ICR_COAL                   (1 << 4)
  238 #define SATA_ICR_DEV(ch)                (1 << (8 + ch))
  239 
  240 #define SATA_MICR                       0x020 /* Main Interrupt Cause Reg. */
  241 #define SATA_MICR_ERR(ch)               (1 << (2 * ch))
  242 #define SATA_MICR_DONE(ch)              (1 << ((2 * ch) + 1))
  243 #define SATA_MICR_DMADONE(ch)           (1 << (4 + ch))
  244 #define SATA_MICR_COAL                  (1 << 8)
  245 
  246 #define SATA_MIMR                       0x024 /*  Main Interrupt Mask Reg. */
  247 
  248 /* Shadow registers */
  249 #define SATA_SHADOWR_BASE(ch)           (SATA_EDMA_BASE(ch) + 0x100)
  250 #define SATA_SHADOWR_CONTROL(ch)        (SATA_EDMA_BASE(ch) + 0x120)
  251 
  252 /* SATA registers */
  253 #define SATA_SATA_SSTATUS(ch)           (SATA_EDMA_BASE(ch) + 0x300)
  254 #define SATA_SATA_SERROR(ch)            (SATA_EDMA_BASE(ch) + 0x304)
  255 #define SATA_SATA_SCONTROL(ch)          (SATA_EDMA_BASE(ch) + 0x308)
  256 #define SATA_SATA_FISICR(ch)            (SATA_EDMA_BASE(ch) + 0x364)
  257 
  258 /* EDMA registers */
  259 #define SATA_EDMA_CFG(ch)               (SATA_EDMA_BASE(ch) + 0x000)
  260 #define SATA_EDMA_CFG_QL128             (1 << 19)
  261 #define SATA_EDMA_CFG_HQCACHE           (1 << 22)
  262 
  263 #define SATA_EDMA_IECR(ch)              (SATA_EDMA_BASE(ch) + 0x008)
  264 
  265 #define SATA_EDMA_IEMR(ch)              (SATA_EDMA_BASE(ch) + 0x00C)
  266 #define SATA_EDMA_REQBAHR(ch)           (SATA_EDMA_BASE(ch) + 0x010)
  267 #define SATA_EDMA_REQIPR(ch)            (SATA_EDMA_BASE(ch) + 0x014)
  268 #define SATA_EDMA_REQOPR(ch)            (SATA_EDMA_BASE(ch) + 0x018)
  269 #define SATA_EDMA_RESBAHR(ch)           (SATA_EDMA_BASE(ch) + 0x01C)
  270 #define SATA_EDMA_RESIPR(ch)            (SATA_EDMA_BASE(ch) + 0x020)
  271 #define SATA_EDMA_RESOPR(ch)            (SATA_EDMA_BASE(ch) + 0x024)
  272 
  273 #define SATA_EDMA_CMD(ch)               (SATA_EDMA_BASE(ch) + 0x028)
  274 #define SATA_EDMA_CMD_ENABLE            (1 << 0)
  275 #define SATA_EDMA_CMD_DISABLE           (1 << 1)
  276 #define SATA_EDMA_CMD_RESET             (1 << 2)
  277 
  278 #define SATA_EDMA_STATUS(ch)            (SATA_EDMA_BASE(ch) + 0x030)
  279 #define SATA_EDMA_STATUS_IDLE           (1 << 7)
  280 
  281 /* Offset to extract input slot from REQIPR register */
  282 #define SATA_EDMA_REQIS_OFS             5
  283 
  284 /* Offset to extract input slot from RESOPR register */
  285 #define SATA_EDMA_RESOS_OFS             3
  286 
  287 /*
  288  * GPIO
  289  */
  290 #define GPIO_DATA_OUT           0x00
  291 #define GPIO_DATA_OUT_EN_CTRL   0x04
  292 #define GPIO_BLINK_EN           0x08
  293 #define GPIO_DATA_IN_POLAR      0x0c
  294 #define GPIO_DATA_IN            0x10
  295 #define GPIO_INT_CAUSE          0x14
  296 #define GPIO_INT_EDGE_MASK      0x18
  297 #define GPIO_INT_LEV_MASK       0x1c
  298 
  299 #define GPIO(n)                 (1 << (n))
  300 #define MV_GPIO_MAX_NPINS       64
  301 
  302 #define MV_GPIO_IN_NONE                 0x0
  303 #define MV_GPIO_IN_POL_LOW              (1 << 16)
  304 #define MV_GPIO_IN_IRQ_EDGE             (2 << 16)
  305 #define MV_GPIO_IN_IRQ_LEVEL            (4 << 16)
  306 #define MV_GPIO_IN_IRQ_DOUBLE_EDGE      (8 << 16)
  307 #define MV_GPIO_IN_DEBOUNCE             (16 << 16)
  308 #define MV_GPIO_OUT_NONE                0x0
  309 #define MV_GPIO_OUT_BLINK               0x1
  310 #define MV_GPIO_OUT_OPEN_DRAIN          0x2
  311 #define MV_GPIO_OUT_OPEN_SRC            0x4
  312 
  313 #define IS_GPIO_IRQ(irq)        ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS)
  314 #define GPIO2IRQ(gpio)          ((gpio) + NIRQ)
  315 #define IRQ2GPIO(irq)           ((irq) - NIRQ)
  316 
  317 #if defined(SOC_MV_ORION)
  318 #define SAMPLE_AT_RESET         0x10
  319 #elif defined(SOC_MV_KIRKWOOD)
  320 #define SAMPLE_AT_RESET         0x30
  321 #endif
  322 #define SAMPLE_AT_RESET_ARMADA38X       0x400
  323 #define SAMPLE_AT_RESET_LO              0x30
  324 #define SAMPLE_AT_RESET_HI              0x34
  325 
  326 /*
  327  * Clocks
  328  */
  329 #if defined(SOC_MV_ORION)
  330 #define TCLK_MASK               0x00000300
  331 #define TCLK_SHIFT              0x08
  332 #elif defined(SOC_MV_DISCOVERY)
  333 #define TCLK_MASK               0x00000180
  334 #define TCLK_SHIFT              0x07
  335 #endif
  336 
  337 #define TCLK_MASK_ARMADA38X             0x00008000
  338 #define TCLK_SHIFT_ARMADA38X            15
  339 
  340 #define TCLK_100MHZ             100000000
  341 #define TCLK_125MHZ             125000000
  342 #define TCLK_133MHZ             133333333
  343 #define TCLK_150MHZ             150000000
  344 #define TCLK_166MHZ             166666667
  345 #define TCLK_200MHZ             200000000
  346 #define TCLK_250MHZ             250000000
  347 #define TCLK_300MHZ             300000000
  348 #define TCLK_667MHZ             667000000
  349 
  350 #define A38X_CPU_DDR_CLK_MASK   0x00007c00
  351 #define A38X_CPU_DDR_CLK_SHIFT  10
  352 
  353 /*
  354  * CPU Cache Configuration
  355  */
  356 
  357 #define CPU_CONFIG              0x00000000
  358 #define CPU_CONFIG_IC_PREF      0x00010000
  359 #define CPU_CONFIG_DC_PREF      0x00020000
  360 #define CPU_CONTROL             0x00000004
  361 #define CPU_CONTROL_L2_SIZE     0x00200000      /* Only on Discovery */
  362 #define CPU_CONTROL_L2_MODE     0x00020000      /* Only on Discovery */
  363 #define CPU_L2_CONFIG           0x00000028      /* Only on Kirkwood */
  364 #define CPU_L2_CONFIG_MODE      0x00000010      /* Only on Kirkwood */
  365 
  366 /*
  367  * PCI Express port control (CPU Control registers)
  368  */
  369 #define CPU_CONTROL_PCIE_DISABLE(n)     (1 << (3 * (n)))
  370 
  371 /*
  372  * Vendor ID
  373  */
  374 #define PCI_VENDORID_MRVL       0x11AB
  375 #define PCI_VENDORID_MRVL2      0x1B4B
  376 
  377 /*
  378  * Chip ID
  379  */
  380 #define MV_DEV_88F5181          0x5181
  381 #define MV_DEV_88F5182          0x5182
  382 #define MV_DEV_88F5281          0x5281
  383 #define MV_DEV_88F6281          0x6281
  384 #define MV_DEV_88F6282          0x6282
  385 #define MV_DEV_88F6781          0x6781
  386 #define MV_DEV_88F6828          0x6828
  387 #define MV_DEV_88F6820          0x6820
  388 #define MV_DEV_88F6810          0x6810
  389 #define MV_DEV_MV78100_Z0       0x6381
  390 #define MV_DEV_MV78100          0x7810
  391 #define MV_DEV_MV78130          0x7813
  392 #define MV_DEV_MV78160          0x7816
  393 #define MV_DEV_MV78230          0x7823
  394 #define MV_DEV_MV78260          0x7826
  395 #define MV_DEV_MV78460          0x7846
  396 #define MV_DEV_88RC8180         0x8180
  397 #define MV_DEV_88RC9480         0x9480
  398 #define MV_DEV_88RC9580         0x9580
  399 
  400 #define MV_DEV_FAMILY_MASK      0xff00
  401 #define MV_DEV_DISCOVERY        0x7800
  402 #define MV_DEV_ARMADA38X        0x6800
  403 
  404 /*
  405  * Doorbell register control
  406  */
  407 #define MV_DRBL_PCIE_TO_CPU     0
  408 #define MV_DRBL_CPU_TO_PCIE     1
  409 
  410 #define MV_DRBL_CAUSE(d,u)      (0x10 * (u) + 0x8 * (d))
  411 #define MV_DRBL_MASK(d,u)       (0x10 * (u) + 0x8 * (d) + 0x4)
  412 #define MV_DRBL_MSG(m,d,u)      (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30)
  413 
  414 /*
  415  * SCU
  416  */
  417 #define MV_SCU_BASE             (MV_BASE + 0xc000)
  418 #define MV_SCU_REGS_LEN         0x100
  419 #define MV_SCU_REG_CTRL         0x00
  420 #define MV_SCU_REG_CONFIG       0x04
  421 #define MV_SCU_ENABLE           (1 << 0)
  422 #define MV_SCU_SL_L2_ENABLE     (1 << 3)
  423 #define SCU_CFG_REG_NCPU_MASK   0x3
  424 
  425 /*
  426  * PMSU
  427  */
  428 #define MV_PMSU_BASE            (MV_BASE + 0x22000)
  429 #define MV_PMSU_REGS_LEN        0x1000
  430 #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu)     (((cpu) * 0x100) + 0x124)
  431 
  432 /*
  433  * CPU RESET
  434  */
  435 #define MV_CPU_RESET_BASE       (MV_BASE + 0x20800)
  436 #define MV_CPU_RESET_REGS_LEN   0x8
  437 #define CPU_RESET_OFFSET(cpu)   ((cpu) * 0x8)
  438 #define CPU_RESET_ASSERT        0x1
  439 
  440 #define MV_MBUS_CTRL_BASE       (MV_BASE + 0x20420)
  441 #define MV_MBUS_CTRL_REGS_LEN   0x10
  442 
  443 #endif /* _MVREG_H_ */

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