The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/mvreg.h

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    1 /*-
    2  * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
    3  * All rights reserved.
    4  *
    5  * Developed by Semihalf.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. Neither the name of MARVELL nor the names of contributors
   16  *    may be used to endorse or promote products derived from this software
   17  *    without specific prior written permission.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  *
   31  * $FreeBSD: releng/8.3/sys/arm/mv/mvreg.h 197251 2009-09-16 12:07:58Z raj $
   32  */
   33 
   34 #ifndef _MVREG_H_
   35 #define _MVREG_H_
   36 
   37 /*
   38  * Interrupt sources
   39  */
   40 #if defined(SOC_MV_ORION)
   41 
   42 #define MV_INT_BRIDGE           0       /* AHB-MBus Bridge Interrupt */
   43 #define MV_INT_UART0            3       /* UART0 Interrupt */
   44 #define MV_INT_UART1            4
   45 #define MV_INT_GPIO7_0          6       /* GPIO[7:0] Interrupt */
   46 #define MV_INT_GPIO15_8         7       /* GPIO[15:8] Interrupt */
   47 #define MV_INT_GPIO23_16        8       /* GPIO[23:16] Interrupt */
   48 #define MV_INT_GPIO31_24        9       /* GPIO[31:24] Interrupt */
   49 #define MV_INT_PEX0_ERR         10      /* PCI Express Error */
   50 #define MV_INT_PEX0             11      /* PCI Express INTA,B,C,D Message */
   51 #define MV_INT_PCI_ERR          15      /* PCI Error */
   52 #define MV_INT_USB_BERR         16      /* USB Bridge Error */
   53 #define MV_INT_USB_CI           17      /* USB Controller interrupt */
   54 #define MV_INT_GBERX            18      /* GbE receive interrupt */
   55 #define MV_INT_GBETX            19      /* GbE transmit interrupt */
   56 #define MV_INT_GBEMISC          20      /* GbE misc. interrupt */
   57 #define MV_INT_GBESUM           21      /* GbE summary interrupt */
   58 #define MV_INT_GBEERR           22      /* GbE error interrupt */
   59 #define MV_INT_IDMA_ERR         23      /* DMA error interrupt */
   60 #define MV_INT_IDMA0            24      /* IDMA chan. 0 completion interrupt */
   61 #define MV_INT_IDMA1            25      /* IDMA chan. 1 completion interrupt */
   62 #define MV_INT_IDMA2            26      /* IDMA chan. 2 completion interrupt */
   63 #define MV_INT_IDMA3            27      /* IDMA chan. 3 completion interrupt */
   64 #define MV_INT_SATA             29      /* Serial-ATA Interrupt */
   65 
   66 #elif defined(SOC_MV_KIRKWOOD)
   67 
   68 #define MV_INT_BRIDGE           1       /* AHB-MBus Bridge Interrupt */
   69 #define MV_INT_XOR0_CHAN0       5       /* XOR engine 0 channel 0 Interrupt */
   70 #define MV_INT_XOR0_CHAN1       6       /* XOR engine 0 channel 1 Interrupt */
   71 #define MV_INT_XOR1_CHAN0       7       /* XOR engine 1 channel 0 Interrupt */
   72 #define MV_INT_XOR1_CHAN1       8       /* XOR engine 1 channel 1 Interrupt */
   73 #define MV_INT_PEX0             9       /* PCI Express INTA,B,C,D Message */
   74 #define MV_INT_GBESUM           11      /* GbE0 summary interrupt */
   75 #define MV_INT_GBERX            12      /* GbE0 receive interrupt */
   76 #define MV_INT_GBETX            13      /* GbE0 transmit interrupt */
   77 #define MV_INT_GBEMISC          14      /* GbE0 misc. interrupt */
   78 #define MV_INT_GBE1SUM          15      /* GbE1 summary interrupt */
   79 #define MV_INT_GBE1RX           16      /* GbE1 receive interrupt */
   80 #define MV_INT_GBE1TX           17      /* GbE1 transmit interrupt */
   81 #define MV_INT_GBE1MISC         18      /* GbE1 misc. interrupt */
   82 #define MV_INT_USB_CI           19      /* USB Controller interrupt */
   83 #define MV_INT_SATA             21      /* Serial-ATA Interrupt */
   84 #define MV_INT_CESA             22      /* Security engine completion int. */
   85 #define MV_INT_IDMA_ERR         23      /* DMA error interrupt */
   86 #define MV_INT_UART0            33      /* UART0 Interrupt */
   87 #define MV_INT_UART1            34
   88 #define MV_INT_GPIO7_0          35      /* GPIO[7:0] Interrupt */
   89 #define MV_INT_GPIO15_8         36      /* GPIO[15:8] Interrupt */
   90 #define MV_INT_GPIO23_16        37      /* GPIO[23:16] Interrupt */
   91 #define MV_INT_GPIO31_24        38      /* GPIO[31:24] Interrupt */
   92 #define MV_INT_GPIOHI7_0        39      /* GPIOHI[7:0] Interrupt */
   93 #define MV_INT_GPIOHI15_8       40      /* GPIOHI[15:8] Interrupt */
   94 #define MV_INT_GPIOHI23_16      41      /* GPIOHI[23:16] Interrupt */
   95 #define MV_INT_XOR0_ERR         42      /* XOR engine 0 error Interrupt */
   96 #define MV_INT_XOR1_ERR         43      /* XOR engine 1 error Interrupt */
   97 #define MV_INT_PEX0_ERR         44      /* PCI Express Error */
   98 #define MV_INT_GBEERR           46      /* GbE0 error interrupt */
   99 #define MV_INT_GBE1ERR          47      /* GbE1 error interrupt */
  100 #define MV_INT_USB_BERR         48      /* USB Bridge Error */
  101 
  102 #elif defined(SOC_MV_DISCOVERY)
  103 
  104 #define MV_INT_ERRSUM           0       /* Summary of error interrupts */
  105 #define MV_INT_SPI              1       /* SPI interrupt */
  106 #define MV_INT_TWSI0            2       /* TWSI0 interrupt */
  107 #define MV_INT_TWSI1            3       /* TWSI1 interrupt */
  108 #define MV_INT_IDMA0            4       /* IDMA Channel0 completion */
  109 #define MV_INT_IDMA1            5       /* IDMA Channel0 completion */
  110 #define MV_INT_IDMA2            6       /* IDMA Channel0 completion */
  111 #define MV_INT_IDMA3            7       /* IDMA Channel0 completion */
  112 #define MV_INT_TIMER0           8       /* Timer0 interrupt */
  113 #define MV_INT_TIMER1           9       /* Timer1 interrupt */
  114 #define MV_INT_TIMER2           10      /* Timer2 interrupt */
  115 #define MV_INT_TIMER3           11      /* Timer3 interrupt */
  116 #define MV_INT_UART0            12      /* UART0 interrupt */
  117 #define MV_INT_UART1            13      /* UART1 interrupt */
  118 #define MV_INT_UART2            14      /* UART2 interrupt */
  119 #define MV_INT_UART3            15      /* UART3 interrupt */
  120 #define MV_INT_USB0             16      /* USB0 interrupt */
  121 #define MV_INT_USB1             17      /* USB1 interrupt */
  122 #define MV_INT_USB2             18      /* USB2 interrupt */
  123 #define MV_INT_CESA             19      /* Crypto engine completion interrupt */
  124 #define MV_INT_XOR0             22      /* XOR engine 0 completion interrupt */
  125 #define MV_INT_XOR1             23      /* XOR engine 1 completion interrupt */
  126 #define MV_INT_SATA             26      /* SATA interrupt */
  127 #define MV_INT_PEX00            32      /* PCI Express port 0.0 INTA/B/C/D */
  128 #define MV_INT_PEX01            33      /* PCI Express port 0.1 INTA/B/C/D */
  129 #define MV_INT_PEX02            34      /* PCI Express port 0.2 INTA/B/C/D */
  130 #define MV_INT_PEX03            35      /* PCI Express port 0.3 INTA/B/C/D */
  131 #define MV_INT_PEX10            36      /* PCI Express port 1.0 INTA/B/C/D */
  132 #define MV_INT_PEX11            37      /* PCI Express port 1.1 INTA/B/C/D */
  133 #define MV_INT_PEX12            38      /* PCI Express port 1.2 INTA/B/C/D */
  134 #define MV_INT_PEX13            39      /* PCI Express port 1.3 INTA/B/C/D */
  135 #define MV_INT_GBESUM           40      /* Gigabit Ethernet Port 0 summary */
  136 #define MV_INT_GBERX            41      /* Gigabit Ethernet Port 0 Rx summary */
  137 #define MV_INT_GBETX            42      /* Gigabit Ethernet Port 0 Tx summary */
  138 #define MV_INT_GBEMISC          43      /* Gigabit Ethernet Port 0 Misc summ. */
  139 #define MV_INT_GBE1SUM          44      /* Gigabit Ethernet Port 1 summary */
  140 #define MV_INT_GBE1RX           45      /* Gigabit Ethernet Port 1 Rx summary */
  141 #define MV_INT_GBE1TX           46      /* Gigabit Ethernet Port 1 Tx summary */
  142 #define MV_INT_GBE1MISC         47      /* Gigabit Ethernet Port 1 Misc summ. */
  143 #define MV_INT_GPIO7_0          56      /* GPIO[7:0] Interrupt */
  144 #define MV_INT_GPIO15_8         57      /* GPIO[15:8] Interrupt */
  145 #define MV_INT_GPIO23_16        58      /* GPIO[23:16] Interrupt */
  146 #define MV_INT_GPIO31_24        59      /* GPIO[31:24] Interrupt */
  147 #define MV_INT_DB_IN            60      /* Inbound Doorbell Cause reg Summary */
  148 #define MV_INT_DB_OUT           61      /* Outbound Doorbell Cause reg Summ. */
  149 #define MV_INT_CRYPT_ERR        64      /* Crypto engine error */
  150 #define MV_INT_DEV_ERR          65      /* Device bus error */
  151 #define MV_INT_IDMA_ERR         66      /* DMA error */
  152 #define MV_INT_CPU_ERR          67      /* CPU error */
  153 #define MV_INT_PEX0_ERR         68      /* PCI-Express port0 error */
  154 #define MV_INT_PEX1_ERR         69      /* PCI-Express port1 error */
  155 #define MV_INT_GBE_ERR          70      /* Gigabit Ethernet error */
  156 #define MV_INT_USB_ERR          72      /* USB error */
  157 #define MV_INT_DRAM_ERR         73      /* DRAM ECC error */
  158 #define MV_INT_XOR_ERR          74      /* XOR engine error */
  159 #define MV_INT_WD               79      /* WD Timer interrupt */
  160 
  161 #endif /* SOC_MV_ORION */
  162 
  163 #define BRIDGE_IRQ_CAUSE        0x10
  164 #define BRIGDE_IRQ_MASK         0x14
  165 
  166 #if defined(SOC_MV_DISCOVERY)
  167 #define IRQ_CAUSE_ERROR         0x0
  168 #define IRQ_CAUSE               0x4
  169 #define IRQ_CAUSE_HI            0x8
  170 #define IRQ_MASK_ERROR          0xC
  171 #define IRQ_MASK                0x10
  172 #define IRQ_MASK_HI             0x14
  173 #define IRQ_CAUSE_SELECT        0x18
  174 #define FIQ_MASK_ERROR          0x1C
  175 #define FIQ_MASK                0x20
  176 #define FIQ_MASK_HI             0x24
  177 #define FIQ_CAUSE_SELECT        0x28
  178 #define ENDPOINT_IRQ_MASK_ERROR 0x2C
  179 #define ENDPOINT_IRQ_MASK       0x30
  180 #define ENDPOINT_IRQ_MASK_HI    0x34
  181 #define ENDPOINT_IRQ_CAUSE_SELECT 0x38
  182 #else /* !SOC_MV_DISCOVERY */
  183 #define IRQ_CAUSE               0x0
  184 #define IRQ_MASK                0x4
  185 #define FIQ_MASK                0x8
  186 #define ENDPOINT_IRQ_MASK       0xC
  187 #define IRQ_CAUSE_HI            0x10
  188 #define IRQ_MASK_HI             0x14
  189 #define FIQ_MASK_HI             0x18
  190 #define ENDPOINT_IRQ_MASK_HI    0x1C
  191 #define IRQ_CAUSE_ERROR         (-1)            /* Fake defines for unified */
  192 #define IRQ_MASK_ERROR          (-1)            /* interrupt controller code */
  193 #endif
  194 
  195 #define BRIDGE_IRQ_CAUSE        0x10
  196 #define IRQ_CPU_SELF            0x00000001
  197 #define IRQ_TIMER0              0x00000002
  198 #define IRQ_TIMER1              0x00000004
  199 #define IRQ_TIMER_WD            0x00000008
  200 
  201 #define BRIDGE_IRQ_MASK         0x14
  202 #define IRQ_CPU_MASK            0x00000001
  203 #define IRQ_TIMER0_MASK         0x00000002
  204 #define IRQ_TIMER1_MASK         0x00000004
  205 #define IRQ_TIMER_WD_MASK       0x00000008
  206 
  207 /*
  208  * System reset
  209  */
  210 #define RSTOUTn_MASK            0x8
  211 #define WD_RST_OUT_EN           0x00000002
  212 #define SOFT_RST_OUT_EN         0x00000004
  213 #define SYSTEM_SOFT_RESET       0xc
  214 #define SYS_SOFT_RST            0x00000001
  215 
  216 /*
  217  * Power Control
  218  */
  219 #define CPU_PM_CTRL             0x1C
  220 #define CPU_PM_CTRL_NONE        0
  221 #define CPU_PM_CTRL_ALL         ~0x0
  222 
  223 #if defined(SOC_MV_KIRKWOOD)
  224 #define CPU_PM_CTRL_GE0         (1 << 0)
  225 #define CPU_PM_CTRL_PEX0_PHY    (1 << 1)
  226 #define CPU_PM_CTRL_PEX0        (1 << 2)
  227 #define CPU_PM_CTRL_USB0        (1 << 3)
  228 #define CPU_PM_CTRL_SDIO        (1 << 4)
  229 #define CPU_PM_CTRL_TSU         (1 << 5)
  230 #define CPU_PM_CTRL_DUNIT       (1 << 6)
  231 #define CPU_PM_CTRL_RUNIT       (1 << 7)
  232 #define CPU_PM_CTRL_XOR0        (1 << 8)
  233 #define CPU_PM_CTRL_AUDIO       (1 << 9)
  234 #define CPU_PM_CTRL_SATA0       (1 << 14)
  235 #define CPU_PM_CTRL_SATA1       (1 << 15)
  236 #define CPU_PM_CTRL_XOR1        (1 << 16)
  237 #define CPU_PM_CTRL_CRYPTO      (1 << 17)
  238 #define CPU_PM_CTRL_GE1         (1 << 19)
  239 #define CPU_PM_CTRL_TDM         (1 << 20)
  240 #define CPU_PM_CTRL_XOR         (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1)
  241 #define CPU_PM_CTRL_USB(u)      (CPU_PM_CTRL_USB0)
  242 #define CPU_PM_CTRL_SATA        (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1)
  243 #elif defined(SOC_MV_DISCOVERY)
  244 #define CPU_PM_CTRL_GE0         (1 << 1)
  245 #define CPU_PM_CTRL_GE1         (1 << 2)
  246 #define CPU_PM_CTRL_PEX00       (1 << 5)
  247 #define CPU_PM_CTRL_PEX01       (1 << 6)
  248 #define CPU_PM_CTRL_PEX02       (1 << 7)
  249 #define CPU_PM_CTRL_PEX03       (1 << 8)
  250 #define CPU_PM_CTRL_PEX10       (1 << 9)
  251 #define CPU_PM_CTRL_PEX11       (1 << 10)
  252 #define CPU_PM_CTRL_PEX12       (1 << 11)
  253 #define CPU_PM_CTRL_PEX13       (1 << 12)
  254 #define CPU_PM_CTRL_SATA0_PHY   (1 << 13)
  255 #define CPU_PM_CTRL_SATA0       (1 << 14)
  256 #define CPU_PM_CTRL_SATA1_PHY   (1 << 15)
  257 #define CPU_PM_CTRL_SATA1       (1 << 16)
  258 #define CPU_PM_CTRL_USB0        (1 << 17)
  259 #define CPU_PM_CTRL_USB1        (1 << 18)
  260 #define CPU_PM_CTRL_USB2        (1 << 19)
  261 #define CPU_PM_CTRL_IDMA        (1 << 20)
  262 #define CPU_PM_CTRL_XOR         (1 << 21)
  263 #define CPU_PM_CTRL_CRYPTO      (1 << 22)
  264 #define CPU_PM_CTRL_DEVICE      (1 << 23)
  265 #define CPU_PM_CTRL_USB(u)      (1 << (17 + (u)))
  266 #define CPU_PM_CTRL_SATA        (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1)
  267 #else
  268 #define CPU_PM_CTRL_CRYPTO      (CPU_PM_CTRL_NONE)
  269 #define CPU_PM_CTRL_IDMA        (CPU_PM_CTRL_NONE)
  270 #define CPU_PM_CTRL_XOR         (CPU_PM_CTRL_NONE)
  271 #define CPU_PM_CTRL_SATA        (CPU_PM_CTRL_NONE)
  272 #define CPU_PM_CTRL_USB(u)      (CPU_PM_CTRL_NONE)
  273 #endif
  274 
  275 /*
  276  * Timers
  277  */
  278 #define CPU_TIMER_CONTROL       0x0
  279 #define CPU_TIMER0_EN           0x00000001
  280 #define CPU_TIMER0_AUTO         0x00000002
  281 #define CPU_TIMER1_EN           0x00000004
  282 #define CPU_TIMER1_AUTO         0x00000008
  283 #define CPU_TIMER_WD_EN         0x00000010
  284 #define CPU_TIMER_WD_AUTO       0x00000020
  285 #define CPU_TIMER0_REL          0x10
  286 #define CPU_TIMER0              0x14
  287 
  288 /*
  289  * SATA
  290  */
  291 #define SATA_CHAN_NUM                   2
  292 
  293 #define EDMA_REGISTERS_OFFSET           0x2000
  294 #define EDMA_REGISTERS_SIZE             0x2000
  295 #define SATA_EDMA_BASE(ch)              (EDMA_REGISTERS_OFFSET + \
  296     ((ch) * EDMA_REGISTERS_SIZE))
  297 
  298 /* SATAHC registers */
  299 #define SATA_CR                         0x000 /* Configuration Reg. */
  300 #define SATA_CR_NODMABS                 (1 << 8)
  301 #define SATA_CR_NOEDMABS                (1 << 9)
  302 #define SATA_CR_NOPRDPBS                (1 << 10)
  303 #define SATA_CR_COALDIS(ch)             (1 << (24 + ch))
  304 
  305 #define SATA_ICR                        0x014 /* Interrupt Cause Reg. */
  306 #define SATA_ICR_DMADONE(ch)            (1 << (ch))
  307 #define SATA_ICR_COAL                   (1 << 4)
  308 #define SATA_ICR_DEV(ch)                (1 << (8 + ch))
  309 
  310 #define SATA_MICR                       0x020 /* Main Interrupt Cause Reg. */
  311 #define SATA_MICR_ERR(ch)               (1 << (2 * ch))
  312 #define SATA_MICR_DONE(ch)              (1 << ((2 * ch) + 1))
  313 #define SATA_MICR_DMADONE(ch)           (1 << (4 + ch))
  314 #define SATA_MICR_COAL                  (1 << 8)
  315 
  316 #define SATA_MIMR                       0x024 /*  Main Interrupt Mask Reg. */
  317 
  318 /* Shadow registers */
  319 #define SATA_SHADOWR_BASE(ch)           (SATA_EDMA_BASE(ch) + 0x100)
  320 #define SATA_SHADOWR_CONTROL(ch)        (SATA_EDMA_BASE(ch) + 0x120)
  321 
  322 /* SATA registers */
  323 #define SATA_SATA_SSTATUS(ch)           (SATA_EDMA_BASE(ch) + 0x300)
  324 #define SATA_SATA_SERROR(ch)            (SATA_EDMA_BASE(ch) + 0x304)
  325 #define SATA_SATA_SCONTROL(ch)          (SATA_EDMA_BASE(ch) + 0x308)
  326 #define SATA_SATA_FISICR(ch)            (SATA_EDMA_BASE(ch) + 0x364)
  327 
  328 /* EDMA registers */
  329 #define SATA_EDMA_CFG(ch)               (SATA_EDMA_BASE(ch) + 0x000)
  330 #define SATA_EDMA_CFG_QL128             (1 << 19)
  331 #define SATA_EDMA_CFG_HQCACHE           (1 << 22)
  332 
  333 #define SATA_EDMA_IECR(ch)              (SATA_EDMA_BASE(ch) + 0x008)
  334 
  335 #define SATA_EDMA_IEMR(ch)              (SATA_EDMA_BASE(ch) + 0x00C)
  336 #define SATA_EDMA_REQBAHR(ch)           (SATA_EDMA_BASE(ch) + 0x010)
  337 #define SATA_EDMA_REQIPR(ch)            (SATA_EDMA_BASE(ch) + 0x014)
  338 #define SATA_EDMA_REQOPR(ch)            (SATA_EDMA_BASE(ch) + 0x018)
  339 #define SATA_EDMA_RESBAHR(ch)           (SATA_EDMA_BASE(ch) + 0x01C)
  340 #define SATA_EDMA_RESIPR(ch)            (SATA_EDMA_BASE(ch) + 0x020)
  341 #define SATA_EDMA_RESOPR(ch)            (SATA_EDMA_BASE(ch) + 0x024)
  342 
  343 #define SATA_EDMA_CMD(ch)               (SATA_EDMA_BASE(ch) + 0x028)
  344 #define SATA_EDMA_CMD_ENABLE            (1 << 0)
  345 #define SATA_EDMA_CMD_DISABLE           (1 << 1)
  346 #define SATA_EDMA_CMD_RESET             (1 << 2)
  347 
  348 #define SATA_EDMA_STATUS(ch)            (SATA_EDMA_BASE(ch) + 0x030)
  349 #define SATA_EDMA_STATUS_IDLE           (1 << 7)
  350 
  351 /* Offset to extract input slot from REQIPR register */
  352 #define SATA_EDMA_REQIS_OFS             5
  353 
  354 /* Offset to extract input slot from RESOPR register */
  355 #define SATA_EDMA_RESOS_OFS             3
  356 
  357 /*
  358  * GPIO
  359  */
  360 #define GPIO_DATA_OUT           0x00
  361 #define GPIO_DATA_OUT_EN_CTRL   0x04
  362 #define GPIO_BLINK_EN           0x08
  363 #define GPIO_DATA_IN_POLAR      0x0c
  364 #define GPIO_DATA_IN            0x10
  365 #define GPIO_INT_CAUSE          0x14
  366 #define GPIO_INT_EDGE_MASK      0x18
  367 #define GPIO_INT_LEV_MASK       0x1c
  368 
  369 #define GPIO_HI_DATA_OUT                0x40
  370 #define GPIO_HI_DATA_OUT_EN_CTRL        0x44
  371 #define GPIO_HI_BLINK_EN                0x48
  372 #define GPIO_HI_DATA_IN_POLAR           0x4c
  373 #define GPIO_HI_DATA_IN                 0x50
  374 #define GPIO_HI_INT_CAUSE               0x54
  375 #define GPIO_HI_INT_EDGE_MASK           0x58
  376 #define GPIO_HI_INT_LEV_MASK            0x5c
  377 
  378 #define GPIO(n)                 (1 << (n))
  379 #define MV_GPIO_MAX_NPINS       64
  380 
  381 #define MV_GPIO_BLINK           0x1
  382 #define MV_GPIO_POLAR_LOW       0x2
  383 #define MV_GPIO_EDGE            0x4
  384 #define MV_GPIO_LEVEL           0x8
  385 
  386 #define IS_GPIO_IRQ(irq)        ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS)
  387 #define GPIO2IRQ(gpio)          ((gpio) + NIRQ)
  388 #define IRQ2GPIO(irq)           ((irq) - NIRQ)
  389 
  390 /*
  391  * MPP
  392  */
  393 #if defined(SOC_MV_ORION)
  394 #define MPP_CONTROL0            0x00
  395 #define MPP_CONTROL1            0x04
  396 #define MPP_CONTROL2            0x50
  397 #elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
  398 #define MPP_CONTROL0            0x00
  399 #define MPP_CONTROL1            0x04
  400 #define MPP_CONTROL2            0x08
  401 #define MPP_CONTROL3            0x0C
  402 #define MPP_CONTROL4            0x10
  403 #define MPP_CONTROL5            0x14
  404 #define MPP_CONTROL6            0x18
  405 #else
  406 #error SOC_MV_XX not defined
  407 #endif
  408 
  409 #if defined(SOC_MV_ORION)
  410 #define SAMPLE_AT_RESET         0x10
  411 #elif defined(SOC_MV_KIRKWOOD)
  412 #define SAMPLE_AT_RESET         0x30
  413 #elif defined(SOC_MV_DISCOVERY)
  414 #define SAMPLE_AT_RESET_LO      0x30
  415 #define SAMPLE_AT_RESET_HI      0x34
  416 #else
  417 #error SOC_MV_XX not defined
  418 #endif
  419 
  420 /*
  421  * Clocks
  422  */
  423 #if defined(SOC_MV_ORION)
  424 #define TCLK_MASK               0x00000300
  425 #define TCLK_SHIFT              0x08
  426 #elif defined(SOC_MV_DISCOVERY)
  427 #define TCLK_MASK               0x00000180
  428 #define TCLK_SHIFT              0x07
  429 #endif
  430 
  431 #define TCLK_100MHZ             100000000
  432 #define TCLK_125MHZ             125000000
  433 #define TCLK_133MHZ             133333333
  434 #define TCLK_150MHZ             150000000
  435 #define TCLK_166MHZ             166666667
  436 #define TCLK_200MHZ             200000000
  437 
  438 /*
  439  * Chip ID
  440  */
  441 #define MV_DEV_88F5181          0x5181
  442 #define MV_DEV_88F5182          0x5182
  443 #define MV_DEV_88F5281          0x5281
  444 #define MV_DEV_88F6281          0x6281
  445 #define MV_DEV_MV78100_Z0       0x6381
  446 #define MV_DEV_MV78100          0x7810
  447 
  448 #endif /* _MVREG_H_ */

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