FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/mvwin.h
1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
5 * All rights reserved.
6 *
7 * Developed by Semihalf.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of MARVELL nor the names of contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD$
34 */
35
36 #ifndef _MVWIN_H_
37 #define _MVWIN_H_
38
39 /*
40 * Decode windows addresses.
41 *
42 * All decoding windows must be aligned to their size, which has to be
43 * a power of 2.
44 */
45
46 /*
47 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA)
48 */
49
50 /* SoC Regs */
51 #define MV_PHYS_BASE 0xF1000000
52 #define MV_SIZE (1024 * 1024) /* 1 MB */
53
54 /* SRAM */
55 #define MV_CESA_SRAM_BASE 0xF1100000
56
57 /*
58 * External devices: 0x80000000, 1 GB (VA == PA)
59 * Includes Device Bus, PCI and PCIE.
60 */
61 #if defined(SOC_MV_ORION)
62 #define MV_PCI_PORTS 2 /* 1x PCI + 1x PCIE */
63 #elif defined(SOC_MV_KIRKWOOD)
64 #define MV_PCI_PORTS 1 /* 1x PCIE */
65 #elif defined(SOC_MV_DISCOVERY)
66 #define MV_PCI_PORTS 8 /* 8x PCIE */
67 #else
68 #define MV_PCI_PORTS 1 /* 1x PCIE -> worst case */
69 #endif
70
71 /* PCI/PCIE Memory */
72 #define MV_PCI_MEM_PHYS_BASE 0x80000000
73 #define MV_PCI_MEM_SIZE (512 * 1024 * 1024) /* 512 MB */
74 #define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE
75 #define MV_PCI_MEM_SLICE_SIZE (MV_PCI_MEM_SIZE / MV_PCI_PORTS)
76 /* PCI/PCIE I/O */
77 #define MV_PCI_IO_PHYS_BASE 0xBF000000
78 #define MV_PCI_IO_SIZE (16 * 1024 * 1024) /* 16 MB */
79 #define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE
80 #define MV_PCI_IO_SLICE_SIZE (MV_PCI_IO_SIZE / MV_PCI_PORTS)
81 #define MV_PCI_VA_MEM_BASE 0
82 #define MV_PCI_VA_IO_BASE 0
83
84 /*
85 * Device Bus (VA == PA)
86 */
87 #define MV_DEV_BOOT_BASE 0xF9300000
88 #define MV_DEV_BOOT_SIZE (1024 * 1024) /* 1 MB */
89
90 #define MV_DEV_CS0_BASE 0xF9400000
91 #define MV_DEV_CS0_SIZE (1024 * 1024) /* 1 MB */
92
93 #define MV_DEV_CS1_BASE 0xF9500000
94 #define MV_DEV_CS1_SIZE (32 * 1024 * 1024) /* 32 MB */
95
96 #define MV_DEV_CS2_BASE 0xFB500000
97 #define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */
98
99 /*
100 * Integrated SoC peripherals addresses
101 */
102 #define MV_BASE MV_PHYS_BASE /* VA == PA mapping */
103 #define MV_DDR_CADR_BASE_ARMV7 (MV_BASE + 0x20180)
104 #define MV_DDR_CADR_BASE (MV_BASE + 0x1500)
105 #define MV_MPP_BASE (MV_BASE + 0x10000)
106
107 #define MV_MISC_BASE (MV_BASE + 0x18200)
108 #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000)
109 #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80)
110 #define MV_MP_CLOCKS_BASE (MV_MBUS_BRIDGE_BASE + 0x700)
111
112 #define MV_CPU_CONTROL_BASE_ARMV7 (MV_MBUS_BRIDGE_BASE + 0x1800)
113 #define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100)
114
115 #define MV_PCI_BASE (MV_BASE + 0x30000)
116 #define MV_PCI_SIZE 0x2000
117
118 #define MV_PCIE_BASE_ARMADA38X (MV_BASE + 0x80000)
119 #define MV_PCIE_BASE (MV_BASE + 0x40000)
120 #define MV_PCIE_SIZE 0x2000
121 #define MV_SDIO_BASE (MV_BASE + 0x90000)
122 #define MV_SDIO_SIZE 0x10000
123
124 /*
125 * Decode windows definitions and macros
126 */
127 #define MV_WIN_CPU_CTRL_ARMV7(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8)))
128 #define MV_WIN_CPU_BASE_ARMV7(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4)
129 #define MV_WIN_CPU_REMAP_LO_ARMV7(n) (0x10 * (n) + 0x008)
130 #define MV_WIN_CPU_REMAP_HI_ARMV7(n) (0x10 * (n) + 0x00C)
131
132 #define MV_WIN_CPU_CTRL_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880))
133 #define MV_WIN_CPU_BASE_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884))
134 #define MV_WIN_CPU_REMAP_LO_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888))
135 #define MV_WIN_CPU_REMAP_HI_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C))
136
137 #if defined(SOC_MV_DISCOVERY)
138 #define MV_WIN_CPU_MAX 14
139 #else
140 #define MV_WIN_CPU_MAX 8
141 #endif
142 #define MV_WIN_CPU_MAX_ARMV7 20
143
144 #define MV_WIN_CPU_ATTR_SHIFT 8
145 #define MV_WIN_CPU_TARGET_SHIFT 4
146 #define MV_WIN_CPU_ENABLE_BIT 1
147
148 #define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0)
149 #define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4)
150 #define MV_WIN_DDR_MAX 4
151
152 /*
153 * These values are valid only for peripherals decoding windows
154 * Bit in ATTR is zeroed according to CS bank number
155 */
156 #define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs)))
157 #define MV_WIN_DDR_TARGET 0x0
158
159 #if defined(SOC_MV_DISCOVERY)
160 #define MV_WIN_CESA_TARGET 9
161 #define MV_WIN_CESA_ATTR(eng_sel) 1
162 #else
163 #define MV_WIN_CESA_TARGET 3
164 #define MV_WIN_CESA_ATTR(eng_sel) 0
165 #endif
166
167 #define MV_WIN_CESA_TARGET_ARMADAXP 9
168 /*
169 * Bits [2:3] of cesa attribute select engine:
170 * eng_sel:
171 * 1: engine1
172 * 2: engine0
173 */
174 #define MV_WIN_CESA_ATTR_ARMADAXP(eng_sel) (1 | ((eng_sel) << 2))
175 #define MV_WIN_CESA_TARGET_ARMADA38X 9
176 /*
177 * Bits [1:0] = Data swapping
178 * 0x0 = Byte swap
179 * 0x1 = No swap
180 * 0x2 = Byte and word swap
181 * 0x3 = Word swap
182 * Bits [4:2] = CESA select:
183 * 0x6 = CESA0
184 * 0x5 = CESA1
185 */
186 #define MV_WIN_CESA_ATTR_ARMADA38X(eng_sel) (0x11 | (1 << (3 - (eng_sel))))
187 /* CESA TDMA address decoding registers */
188 #define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xA04)
189 #define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xA00)
190 #define MV_WIN_CESA_MAX 4
191
192 #define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320)
193 #define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324)
194 #define MV_WIN_USB_MAX 4
195
196 #define MV_WIN_USB3_CTRL(n) (0x8 * (n) + 0x4000)
197 #define MV_WIN_USB3_BASE(n) (0x8 * (n) + 0x4004)
198 #define MV_WIN_USB3_MAX 8
199
200 #define MV_WIN_NETA_OFFSET 0x2000
201 #define MV_WIN_NETA_BASE(n) MV_WIN_ETH_BASE(n) + MV_WIN_NETA_OFFSET
202
203 #define MV_WIN_CESA_OFFSET 0x2000
204
205 #define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200)
206 #define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204)
207 #define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280)
208 #define MV_WIN_ETH_MAX 6
209
210 #define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00)
211 #define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04)
212 #define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60)
213 #define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70)
214 #define MV_WIN_IDMA_MAX 8
215 #define MV_IDMA_CHAN_MAX 4
216
217 #define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100)
218 #define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100)
219 #define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100)
220 #define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100)
221 #define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100)
222 #define MV_WIN_XOR_MAX 8
223 #define MV_XOR_CHAN_MAX 2
224 #define MV_XOR_NON_REMAP 4
225
226 #define MV_WIN_PCIE_TARGET_ARMADAXP(n) (4 + (4 * ((n) % 2)))
227 #define MV_WIN_PCIE_MEM_ATTR_ARMADAXP(n) (0xE8 + (0x10 * ((n) / 2)))
228 #define MV_WIN_PCIE_IO_ATTR_ARMADAXP(n) (0xE0 + (0x10 * ((n) / 2)))
229 #define MV_WIN_PCIE_TARGET_ARMADA38X(n) ((n) == 0 ? 8 : 4)
230 #define MV_WIN_PCIE_MEM_ATTR_ARMADA38X(n) ((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20)))
231 #define MV_WIN_PCIE_IO_ATTR_ARMADA38X(n) ((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20)))
232 #if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD)
233 #define MV_WIN_PCIE_TARGET(n) 4
234 #define MV_WIN_PCIE_MEM_ATTR(n) 0xE8
235 #define MV_WIN_PCIE_IO_ATTR(n) 0xE0
236 #elif defined(SOC_MV_ORION)
237 #define MV_WIN_PCIE_TARGET(n) 4
238 #define MV_WIN_PCIE_MEM_ATTR(n) 0x59
239 #define MV_WIN_PCIE_IO_ATTR(n) 0x51
240 #else
241 #define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2)))
242 #define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2)))
243 #define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2)))
244 #endif
245
246 #define MV_WIN_PCI_TARGET 3
247 #define MV_WIN_PCI_MEM_ATTR 0x59
248 #define MV_WIN_PCI_IO_ATTR 0x51
249
250 #define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \
251 (n) + 1) + 0x1820)
252 #define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \
253 (n) + 1) + 0x1824)
254 #define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \
255 (n) + 1) + 0x182C)
256 #define MV_WIN_PCIE_MAX 6
257
258 #define MV_PCIE_BAR_CTRL(n) (0x04 * (n) + 0x1800)
259 #define MV_PCIE_BAR_BASE(n) (0x08 * ((n) < 3 ? (n) : 4) + 0x0010)
260 #define MV_PCIE_BAR_BASE_H(n) (0x08 * (n) + 0x0014)
261 #define MV_PCIE_BAR_MAX 4
262 #define MV_PCIE_BAR_64BIT (0x4)
263 #define MV_PCIE_BAR_PREFETCH_EN (0x8)
264
265 #define MV_PCIE_CONTROL (0x1a00)
266 #define MV_PCIE_ROOT_CMPLX (1 << 1)
267
268 #define MV_WIN_SATA_CTRL_ARMADA38X(n) (0x10 * (n) + 0x60)
269 #define MV_WIN_SATA_BASE_ARMADA38X(n) (0x10 * (n) + 0x64)
270 #define MV_WIN_SATA_SIZE_ARMADA38X(n) (0x10 * (n) + 0x68)
271 #define MV_WIN_SATA_MAX_ARMADA38X 4
272 #define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30)
273 #define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34)
274 #define MV_WIN_SATA_MAX 4
275
276 #define MV_WIN_SDHCI_CTRL(n) (0x8 * (n) + 0x4080)
277 #define MV_WIN_SDHCI_BASE(n) (0x8 * (n) + 0x4084)
278 #define MV_WIN_SDHCI_MAX 8
279
280 #define MV_BOOTROM_MEM_ADDR 0xFFF00000
281 #define MV_BOOTROM_WIN_SIZE 0xF
282 #define MV_CPU_SUBSYS_REGS_LEN 0x100
283
284 #define IO_WIN_9_CTRL_OFFSET 0x98
285 #define IO_WIN_9_BASE_OFFSET 0x9C
286
287 /* Mbus decoding unit IDs and attributes */
288 #define MBUS_BOOTROM_TGT_ID 0x1
289 #define MBUS_BOOTROM_ATTR 0x1D
290
291 /* Internal Units Sync Barrier Control Register */
292 #define MV_SYNC_BARRIER_CTRL 0x84
293 #define MV_SYNC_BARRIER_CTRL_ALL 0xFFFF
294
295 /* IO Window Control Register fields */
296 #define IO_WIN_SIZE_SHIFT 16
297 #define IO_WIN_SIZE_MASK 0xFFFF
298 #define IO_WIN_COH_ATTR_MASK (0xF << 12)
299 #define IO_WIN_ATTR_SHIFT 8
300 #define IO_WIN_ATTR_MASK 0xFF
301 #define IO_WIN_TGT_SHIFT 4
302 #define IO_WIN_TGT_MASK 0xF
303 #define IO_WIN_SYNC_SHIFT 1
304 #define IO_WIN_SYNC_MASK 0x1
305 #define IO_WIN_ENA_SHIFT 0
306 #define IO_WIN_ENA_MASK 0x1
307
308 #define WIN_REG_IDX_RD(pre,reg,off,base) \
309 static __inline uint32_t \
310 pre ## _ ## reg ## _read(int i) \
311 { \
312 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \
313 }
314
315 #define WIN_REG_IDX_RD2(pre,reg,off,base) \
316 static __inline uint32_t \
317 pre ## _ ## reg ## _read(int i, int j) \
318 { \
319 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \
320 } \
321
322 #define WIN_REG_BASE_IDX_RD(pre,reg,off) \
323 static __inline uint32_t \
324 pre ## _ ## reg ## _read(uint32_t base, int i) \
325 { \
326 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \
327 }
328
329 #define WIN_REG_BASE_IDX_RD2(pre,reg,off) \
330 static __inline uint32_t \
331 pre ## _ ## reg ## _read(uint32_t base, int i, int j) \
332 { \
333 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \
334 }
335
336 #define WIN_REG_IDX_WR(pre,reg,off,base) \
337 static __inline void \
338 pre ## _ ## reg ## _write(int i, uint32_t val) \
339 { \
340 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \
341 }
342
343 #define WIN_REG_IDX_WR2(pre,reg,off,base) \
344 static __inline void \
345 pre ## _ ## reg ## _write(int i, int j, uint32_t val) \
346 { \
347 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \
348 }
349
350 #define WIN_REG_BASE_IDX_WR(pre,reg,off) \
351 static __inline void \
352 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \
353 { \
354 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \
355 }
356
357 #define WIN_REG_BASE_IDX_WR2(pre,reg,off) \
358 static __inline void \
359 pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val) \
360 { \
361 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \
362 }
363
364 #define WIN_REG_RD(pre,reg,off,base) \
365 static __inline uint32_t \
366 pre ## _ ## reg ## _read(void) \
367 { \
368 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \
369 }
370
371 #define WIN_REG_BASE_RD(pre,reg,off) \
372 static __inline uint32_t \
373 pre ## _ ## reg ## _read(uint32_t base) \
374 { \
375 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \
376 }
377
378 #define WIN_REG_WR(pre,reg,off,base) \
379 static __inline void \
380 pre ## _ ## reg ## _write(uint32_t val) \
381 { \
382 bus_space_write_4(fdtbus_bs_tag, base, off, val); \
383 }
384
385 #define WIN_REG_BASE_WR(pre,reg,off) \
386 static __inline void \
387 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \
388 { \
389 bus_space_write_4(fdtbus_bs_tag, base, off, val); \
390 }
391
392 #endif /* _MVWIN_H_ */
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