The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/mvwin.h

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * SPDX-License-Identifier: BSD-3-Clause
    3  *
    4  * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
    5  * All rights reserved.
    6  *
    7  * Developed by Semihalf.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. Neither the name of MARVELL nor the names of contributors
   18  *    may be used to endorse or promote products derived from this software
   19  *    without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   24  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   31  * SUCH DAMAGE.
   32  *
   33  * $FreeBSD: releng/12.0/sys/arm/mv/mvwin.h 332344 2018-04-09 23:36:52Z mw $
   34  */
   35 
   36 #ifndef _MVWIN_H_
   37 #define _MVWIN_H_
   38 
   39 /*
   40  * Decode windows addresses.
   41  *
   42  * All decoding windows must be aligned to their size, which has to be
   43  * a power of 2.
   44  */
   45 
   46 /*
   47  * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA)
   48  */
   49 
   50 /* SoC Regs */
   51 #define MV_PHYS_BASE            0xF1000000
   52 #define MV_SIZE                 (1024 * 1024)   /* 1 MB */
   53 
   54 /* SRAM */
   55 #define MV_CESA_SRAM_BASE       0xF1100000
   56 
   57 /*
   58  * External devices: 0x80000000, 1 GB (VA == PA)
   59  * Includes Device Bus, PCI and PCIE.
   60  */
   61 #if defined(SOC_MV_ORION)
   62 #define MV_PCI_PORTS    2       /* 1x PCI + 1x PCIE */
   63 #elif defined(SOC_MV_KIRKWOOD)
   64 #define MV_PCI_PORTS    1       /* 1x PCIE */
   65 #elif defined(SOC_MV_DISCOVERY)
   66 #define MV_PCI_PORTS    8       /* 8x PCIE */
   67 #else
   68 #define MV_PCI_PORTS    1       /* 1x PCIE -> worst case */
   69 #endif
   70 
   71 /* PCI/PCIE Memory */
   72 #define MV_PCI_MEM_PHYS_BASE    0x80000000
   73 #define MV_PCI_MEM_SIZE         (512 * 1024 * 1024)     /* 512 MB */
   74 #define MV_PCI_MEM_BASE         MV_PCI_MEM_PHYS_BASE
   75 #define MV_PCI_MEM_SLICE_SIZE   (MV_PCI_MEM_SIZE / MV_PCI_PORTS)
   76 /* PCI/PCIE I/O */
   77 #define MV_PCI_IO_PHYS_BASE     0xBF000000
   78 #define MV_PCI_IO_SIZE          (16 * 1024 * 1024)      /* 16 MB */
   79 #define MV_PCI_IO_BASE          MV_PCI_IO_PHYS_BASE
   80 #define MV_PCI_IO_SLICE_SIZE    (MV_PCI_IO_SIZE / MV_PCI_PORTS)
   81 #define MV_PCI_VA_MEM_BASE      0
   82 #define MV_PCI_VA_IO_BASE       0
   83 
   84 /*
   85  * Device Bus (VA == PA)
   86  */
   87 #define MV_DEV_BOOT_BASE    0xF9300000
   88 #define MV_DEV_BOOT_SIZE    (1024 * 1024)   /* 1 MB */
   89 
   90 #define MV_DEV_CS0_BASE     0xF9400000
   91 #define MV_DEV_CS0_SIZE     (1024 * 1024)   /* 1 MB */
   92 
   93 #define MV_DEV_CS1_BASE     0xF9500000
   94 #define MV_DEV_CS1_SIZE     (32 * 1024 * 1024)  /* 32 MB */
   95 
   96 #define MV_DEV_CS2_BASE     0xFB500000
   97 #define MV_DEV_CS2_SIZE     (1024 * 1024)   /* 1 MB */
   98 
   99 
  100 /*
  101  * Integrated SoC peripherals addresses
  102  */
  103 #define MV_BASE                 MV_PHYS_BASE    /* VA == PA mapping */
  104 #define MV_DDR_CADR_BASE_ARMV7  (MV_BASE + 0x20180)
  105 #define MV_DDR_CADR_BASE        (MV_BASE + 0x1500)
  106 #define MV_MPP_BASE             (MV_BASE + 0x10000)
  107 
  108 
  109 #define MV_MISC_BASE            (MV_BASE + 0x18200)
  110 #define MV_MBUS_BRIDGE_BASE     (MV_BASE + 0x20000)
  111 #define MV_INTREGS_BASE         (MV_MBUS_BRIDGE_BASE + 0x80)
  112 #define MV_MP_CLOCKS_BASE       (MV_MBUS_BRIDGE_BASE + 0x700)
  113 
  114 #define MV_CPU_CONTROL_BASE_ARMV7       (MV_MBUS_BRIDGE_BASE + 0x1800)
  115 #define MV_CPU_CONTROL_BASE     (MV_MBUS_BRIDGE_BASE + 0x100)
  116 
  117 #define MV_PCI_BASE             (MV_BASE + 0x30000)
  118 #define MV_PCI_SIZE             0x2000
  119 
  120 #define MV_PCIE_BASE_ARMADA38X  (MV_BASE + 0x80000)
  121 #define MV_PCIE_BASE            (MV_BASE + 0x40000)
  122 #define MV_PCIE_SIZE            0x2000
  123 #define MV_SDIO_BASE            (MV_BASE + 0x90000)
  124 #define MV_SDIO_SIZE            0x10000
  125 
  126 /*
  127  * Decode windows definitions and macros
  128  */
  129 #define MV_WIN_CPU_CTRL_ARMV7(n)                (((n) < 8) ? 0x10 * (n) :  0x90 + (0x8 * ((n) - 8)))
  130 #define MV_WIN_CPU_BASE_ARMV7(n)                ((((n) < 8) ? 0x10 * (n) :  0x90 + (0x8 * ((n) - 8))) + 0x4)
  131 #define MV_WIN_CPU_REMAP_LO_ARMV7(n)    (0x10 * (n) +  0x008)
  132 #define MV_WIN_CPU_REMAP_HI_ARMV7(n)    (0x10 * (n) +  0x00C)
  133 
  134 #define MV_WIN_CPU_CTRL_ARMV5(n)                (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880))
  135 #define MV_WIN_CPU_BASE_ARMV5(n)                (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884))
  136 #define MV_WIN_CPU_REMAP_LO_ARMV5(n)            (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888))
  137 #define MV_WIN_CPU_REMAP_HI_ARMV5(n)            (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C))
  138 
  139 #if defined(SOC_MV_DISCOVERY)
  140 #define MV_WIN_CPU_MAX                  14
  141 #else
  142 #define MV_WIN_CPU_MAX                  8
  143 #endif
  144 #define MV_WIN_CPU_MAX_ARMV7            20
  145 
  146 #define MV_WIN_CPU_ATTR_SHIFT           8
  147 #define MV_WIN_CPU_TARGET_SHIFT         4
  148 #define MV_WIN_CPU_ENABLE_BIT           1
  149 
  150 #define MV_WIN_DDR_BASE(n)              (0x8 * (n) + 0x0)
  151 #define MV_WIN_DDR_SIZE(n)              (0x8 * (n) + 0x4)
  152 #define MV_WIN_DDR_MAX                  4
  153 
  154 /*
  155  * These values are valid only for peripherals decoding windows
  156  * Bit in ATTR is zeroed according to CS bank number
  157  */
  158 #define MV_WIN_DDR_ATTR(cs)             (0x0F & ~(0x01 << (cs)))
  159 #define MV_WIN_DDR_TARGET               0x0
  160 
  161 #if defined(SOC_MV_DISCOVERY)
  162 #define MV_WIN_CESA_TARGET              9
  163 #define MV_WIN_CESA_ATTR(eng_sel)       1
  164 #else
  165 #define MV_WIN_CESA_TARGET              3
  166 #define MV_WIN_CESA_ATTR(eng_sel)       0
  167 #endif
  168 
  169 #define MV_WIN_CESA_TARGET_ARMADAXP     9
  170 /*
  171  * Bits [2:3] of cesa attribute select engine:
  172  * eng_sel:
  173  *  1: engine1
  174  *  2: engine0
  175  */
  176 #define MV_WIN_CESA_ATTR_ARMADAXP(eng_sel)      (1 | ((eng_sel) << 2))
  177 #define MV_WIN_CESA_TARGET_ARMADA38X            9
  178 /*
  179  * Bits [1:0] = Data swapping
  180  *  0x0 = Byte swap
  181  *  0x1 = No swap
  182  *  0x2 = Byte and word swap
  183  *  0x3 = Word swap
  184  * Bits [4:2] = CESA select:
  185  *  0x6 = CESA0
  186  *  0x5 = CESA1
  187  */
  188 #define MV_WIN_CESA_ATTR_ARMADA38X(eng_sel)     (0x11 | (1 << (3 - (eng_sel))))
  189 /* CESA TDMA address decoding registers */
  190 #define MV_WIN_CESA_CTRL(n)             (0x8 * (n) + 0xA04)
  191 #define MV_WIN_CESA_BASE(n)             (0x8 * (n) + 0xA00)
  192 #define MV_WIN_CESA_MAX                 4
  193 
  194 #define MV_WIN_USB_CTRL(n)              (0x10 * (n) + 0x320)
  195 #define MV_WIN_USB_BASE(n)              (0x10 * (n) + 0x324)
  196 #define MV_WIN_USB_MAX                  4
  197 
  198 #define MV_WIN_USB3_CTRL(n)             (0x8 * (n) + 0x4000)
  199 #define MV_WIN_USB3_BASE(n)             (0x8 * (n) + 0x4004)
  200 #define MV_WIN_USB3_MAX                 8
  201 
  202 #define MV_WIN_NETA_OFFSET              0x2000
  203 #define MV_WIN_NETA_BASE(n)             MV_WIN_ETH_BASE(n) + MV_WIN_NETA_OFFSET
  204 
  205 #define MV_WIN_CESA_OFFSET              0x2000
  206 
  207 #define MV_WIN_ETH_BASE(n)              (0x8 * (n) + 0x200)
  208 #define MV_WIN_ETH_SIZE(n)              (0x8 * (n) + 0x204)
  209 #define MV_WIN_ETH_REMAP(n)             (0x4 * (n) + 0x280)
  210 #define MV_WIN_ETH_MAX                  6
  211 
  212 #define MV_WIN_IDMA_BASE(n)             (0x8 * (n) + 0xa00)
  213 #define MV_WIN_IDMA_SIZE(n)             (0x8 * (n) + 0xa04)
  214 #define MV_WIN_IDMA_REMAP(n)            (0x4 * (n) + 0xa60)
  215 #define MV_WIN_IDMA_CAP(n)              (0x4 * (n) + 0xa70)
  216 #define MV_WIN_IDMA_MAX                 8
  217 #define MV_IDMA_CHAN_MAX                4
  218 
  219 #define MV_WIN_XOR_BASE(n, m)           (0x4 * (n) + 0xa50 + (m) * 0x100)
  220 #define MV_WIN_XOR_SIZE(n, m)           (0x4 * (n) + 0xa70 + (m) * 0x100)
  221 #define MV_WIN_XOR_REMAP(n, m)          (0x4 * (n) + 0xa90 + (m) * 0x100)
  222 #define MV_WIN_XOR_CTRL(n, m)           (0x4 * (n) + 0xa40 + (m) * 0x100)
  223 #define MV_WIN_XOR_OVERR(n, m)          (0x4 * (n) + 0xaa0 + (m) * 0x100)
  224 #define MV_WIN_XOR_MAX                  8
  225 #define MV_XOR_CHAN_MAX                 2
  226 #define MV_XOR_NON_REMAP                4
  227 
  228 #define MV_WIN_PCIE_TARGET_ARMADAXP(n)          (4 + (4 * ((n) % 2)))
  229 #define MV_WIN_PCIE_MEM_ATTR_ARMADAXP(n)        (0xE8 + (0x10 * ((n) / 2)))
  230 #define MV_WIN_PCIE_IO_ATTR_ARMADAXP(n)         (0xE0 + (0x10 * ((n) / 2)))
  231 #define MV_WIN_PCIE_TARGET_ARMADA38X(n)         ((n) == 0 ? 8 : 4)
  232 #define MV_WIN_PCIE_MEM_ATTR_ARMADA38X(n)       ((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20)))
  233 #define MV_WIN_PCIE_IO_ATTR_ARMADA38X(n)        ((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20)))
  234 #if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD)
  235 #define MV_WIN_PCIE_TARGET(n)           4
  236 #define MV_WIN_PCIE_MEM_ATTR(n)         0xE8
  237 #define MV_WIN_PCIE_IO_ATTR(n)          0xE0
  238 #elif defined(SOC_MV_ORION)
  239 #define MV_WIN_PCIE_TARGET(n)           4
  240 #define MV_WIN_PCIE_MEM_ATTR(n)         0x59
  241 #define MV_WIN_PCIE_IO_ATTR(n)          0x51
  242 #else
  243 #define MV_WIN_PCIE_TARGET(n)           (4 + (4 * ((n) % 2)))
  244 #define MV_WIN_PCIE_MEM_ATTR(n)         (0xE8 + (0x10 * ((n) / 2)))
  245 #define MV_WIN_PCIE_IO_ATTR(n)          (0xE0 + (0x10 * ((n) / 2)))
  246 #endif
  247 
  248 #define MV_WIN_PCI_TARGET               3
  249 #define MV_WIN_PCI_MEM_ATTR             0x59
  250 #define MV_WIN_PCI_IO_ATTR              0x51
  251 
  252 #define MV_WIN_PCIE_CTRL(n)             (0x10 * (((n) < 5) ? (n) : \
  253                                             (n) + 1) + 0x1820)
  254 #define MV_WIN_PCIE_BASE(n)             (0x10 * (((n) < 5) ? (n) : \
  255                                             (n) + 1) + 0x1824)
  256 #define MV_WIN_PCIE_REMAP(n)            (0x10 * (((n) < 5) ? (n) : \
  257                                             (n) + 1) + 0x182C)
  258 #define MV_WIN_PCIE_MAX                 6
  259 
  260 #define MV_PCIE_BAR_CTRL(n)             (0x04 * (n) + 0x1800)
  261 #define MV_PCIE_BAR_BASE(n)             (0x08 * ((n) < 3 ? (n) : 4) + 0x0010)
  262 #define MV_PCIE_BAR_BASE_H(n)           (0x08 * (n) + 0x0014)
  263 #define MV_PCIE_BAR_MAX                 4
  264 #define MV_PCIE_BAR_64BIT               (0x4)
  265 #define MV_PCIE_BAR_PREFETCH_EN         (0x8)
  266 
  267 #define MV_PCIE_CONTROL                 (0x1a00)
  268 #define MV_PCIE_ROOT_CMPLX              (1 << 1)
  269 
  270 #define MV_WIN_SATA_CTRL_ARMADA38X(n)   (0x10 * (n) + 0x60)
  271 #define MV_WIN_SATA_BASE_ARMADA38X(n)   (0x10 * (n) + 0x64)
  272 #define MV_WIN_SATA_SIZE_ARMADA38X(n)   (0x10 * (n) + 0x68)
  273 #define MV_WIN_SATA_MAX_ARMADA38X       4
  274 #define MV_WIN_SATA_CTRL(n)             (0x10 * (n) + 0x30)
  275 #define MV_WIN_SATA_BASE(n)             (0x10 * (n) + 0x34)
  276 #define MV_WIN_SATA_MAX                 4
  277 
  278 #define MV_WIN_SDHCI_CTRL(n)            (0x8 * (n) + 0x4080)
  279 #define MV_WIN_SDHCI_BASE(n)            (0x8 * (n) + 0x4084)
  280 #define MV_WIN_SDHCI_MAX                8
  281 
  282 #define MV_BOOTROM_MEM_ADDR     0xFFF00000
  283 #define MV_BOOTROM_WIN_SIZE     0xF
  284 #define MV_CPU_SUBSYS_REGS_LEN  0x100
  285 
  286 #define IO_WIN_9_CTRL_OFFSET    0x98
  287 #define IO_WIN_9_BASE_OFFSET    0x9C
  288 
  289 /* Mbus decoding unit IDs and attributes */
  290 #define MBUS_BOOTROM_TGT_ID     0x1
  291 #define MBUS_BOOTROM_ATTR       0x1D
  292 
  293 /* Internal Units Sync Barrier Control Register */
  294 #define MV_SYNC_BARRIER_CTRL            0x84
  295 #define MV_SYNC_BARRIER_CTRL_ALL        0xFFFF
  296 
  297 /* IO Window Control Register fields */
  298 #define IO_WIN_SIZE_SHIFT       16
  299 #define IO_WIN_SIZE_MASK        0xFFFF
  300 #define IO_WIN_COH_ATTR_MASK    (0xF << 12)
  301 #define IO_WIN_ATTR_SHIFT       8
  302 #define IO_WIN_ATTR_MASK        0xFF
  303 #define IO_WIN_TGT_SHIFT        4
  304 #define IO_WIN_TGT_MASK         0xF
  305 #define IO_WIN_SYNC_SHIFT       1
  306 #define IO_WIN_SYNC_MASK        0x1
  307 #define IO_WIN_ENA_SHIFT        0
  308 #define IO_WIN_ENA_MASK         0x1
  309 
  310 #define WIN_REG_IDX_RD(pre,reg,off,base)                                        \
  311         static __inline uint32_t                                                \
  312         pre ## _ ## reg ## _read(int i)                                         \
  313         {                                                                       \
  314                 return (bus_space_read_4(fdtbus_bs_tag, base, off(i)));         \
  315         }
  316 
  317 #define WIN_REG_IDX_RD2(pre,reg,off,base)                                       \
  318         static  __inline uint32_t                                               \
  319         pre ## _ ## reg ## _read(int i, int j)                                  \
  320         {                                                                       \
  321                 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j)));              \
  322         }                                                                       \
  323 
  324 #define WIN_REG_BASE_IDX_RD(pre,reg,off)                                        \
  325         static __inline uint32_t                                                \
  326         pre ## _ ## reg ## _read(uint32_t base, int i)                          \
  327         {                                                                       \
  328                 return (bus_space_read_4(fdtbus_bs_tag, base, off(i)));         \
  329         }
  330 
  331 #define WIN_REG_BASE_IDX_RD2(pre,reg,off)                                       \
  332         static __inline uint32_t                                                \
  333         pre ## _ ## reg ## _read(uint32_t base, int i, int j)                           \
  334         {                                                                       \
  335                 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j)));              \
  336         }
  337 
  338 #define WIN_REG_IDX_WR(pre,reg,off,base)                                        \
  339         static __inline void                                                    \
  340         pre ## _ ## reg ## _write(int i, uint32_t val)                          \
  341         {                                                                       \
  342                 bus_space_write_4(fdtbus_bs_tag, base, off(i), val);                    \
  343         }
  344 
  345 #define WIN_REG_IDX_WR2(pre,reg,off,base)                                       \
  346         static __inline void                                                    \
  347         pre ## _ ## reg ## _write(int i, int j, uint32_t val)                   \
  348         {                                                                       \
  349                 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val);         \
  350         }
  351 
  352 #define WIN_REG_BASE_IDX_WR(pre,reg,off)                                        \
  353         static __inline void                                                    \
  354         pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val)           \
  355         {                                                                       \
  356                 bus_space_write_4(fdtbus_bs_tag, base, off(i), val);                    \
  357         }
  358 
  359 #define WIN_REG_BASE_IDX_WR2(pre,reg,off)                                       \
  360         static __inline void                                                    \
  361         pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val)            \
  362         {                                                                       \
  363                 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val);                 \
  364         }
  365 
  366 #define WIN_REG_RD(pre,reg,off,base)                                            \
  367         static __inline uint32_t                                                \
  368         pre ## _ ## reg ## _read(void)                                          \
  369         {                                                                       \
  370                 return (bus_space_read_4(fdtbus_bs_tag, base, off));                    \
  371         }
  372 
  373 #define WIN_REG_BASE_RD(pre,reg,off)                                            \
  374         static __inline uint32_t                                                \
  375         pre ## _ ## reg ## _read(uint32_t base)                                 \
  376         {                                                                       \
  377                 return (bus_space_read_4(fdtbus_bs_tag, base, off));                    \
  378         }
  379 
  380 #define WIN_REG_WR(pre,reg,off,base)                                            \
  381         static __inline void                                                    \
  382         pre ## _ ## reg ## _write(uint32_t val)                                 \
  383         {                                                                       \
  384                 bus_space_write_4(fdtbus_bs_tag, base, off, val);                       \
  385         }
  386 
  387 #define WIN_REG_BASE_WR(pre,reg,off)                                            \
  388         static __inline void                                                    \
  389         pre ## _ ## reg ## _write(uint32_t base, uint32_t val)                  \
  390         {                                                                       \
  391                 bus_space_write_4(fdtbus_bs_tag, base, off, val);                       \
  392         }
  393 
  394 #endif /* _MVWIN_H_ */

Cache object: 4e6d45c946cb0ef6e97587e6875474b8


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.