Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/mvwin.h
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1 /*- 2 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: releng/9.0/sys/arm/mv/mvwin.h 209131 2010-06-13 13:28:53Z raj $ 32 */ 33 34 #ifndef _MVWIN_H_ 35 #define _MVWIN_H_ 36 37 /* 38 * Physical addresses of integrated SoC peripherals 39 */ 40 #define MV_PHYS_BASE 0xF1000000 41 #define MV_SIZE 0x100000 42 43 /* 44 * Decode windows addresses (physical) 45 */ 46 #define MV_PCIE_IO_PHYS_BASE (MV_PHYS_BASE + MV_SIZE) 47 #define MV_PCIE_IO_BASE MV_PCIE_IO_PHYS_BASE 48 #define MV_PCIE_IO_SIZE (1024 * 1024) 49 #define MV_PCI_IO_PHYS_BASE (MV_PCIE_IO_PHYS_BASE + MV_PCIE_IO_SIZE) 50 #define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE 51 #define MV_PCI_IO_SIZE (1024 * 1024) 52 53 #define MV_PCIE_MEM_PHYS_BASE (MV_PCI_IO_PHYS_BASE + MV_PCI_IO_SIZE) 54 #define MV_PCIE_MEM_BASE MV_PCIE_MEM_PHYS_BASE 55 #define MV_PCIE_MEM_SIZE (64 * 1024 * 1024) 56 #define MV_PCI_MEM_PHYS_BASE (MV_PCIE_MEM_PHYS_BASE + MV_PCIE_MEM_SIZE) 57 #define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 58 #define MV_PCI_MEM_SIZE (64 * 1024 * 1024) 59 60 /* XXX DEV_BOOT, CSx are board specific, should be defined per platform */ 61 62 /* 512KB NOR FLASH */ 63 #define MV_DEV_BOOT_PHYS_BASE (MV_PCI_MEM_PHYS_BASE + MV_PCI_MEM_SIZE) 64 #define MV_DEV_BOOT_SIZE (512 * 1024) 65 /* CS0: 7-seg LED */ 66 #define MV_DEV_CS0_PHYS_BASE 0xFA000000 67 #define MV_DEV_CS0_SIZE (1024 * 1024) /* XXX u-boot has 2MB */ 68 /* CS1: 32MB NOR FLASH */ 69 #define MV_DEV_CS1_PHYS_BASE (MV_DEV_CS0_PHYS_BASE + MV_DEV_CS0_SIZE) 70 #define MV_DEV_CS1_SIZE (32 * 1024 * 1024) 71 /* CS2: 32MB NAND FLASH */ 72 #define MV_DEV_CS2_PHYS_BASE (MV_DEV_CS1_PHYS_BASE + MV_DEV_CS1_SIZE) 73 #define MV_DEV_CS2_SIZE 1024 /* XXX u-boot has 1MB */ 74 75 #define MV_CESA_SRAM_PHYS_BASE 0xFD000000 76 #define MV_CESA_SRAM_BASE MV_CESA_SRAM_PHYS_BASE /* VA == PA mapping */ 77 #define MV_CESA_SRAM_SIZE (1024 * 1024) 78 79 /* XXX this is probably not robust against wraparounds... */ 80 #if ((MV_CESA_SRAM_PHYS_BASE + MV_CESA_SRAM_SIZE) > 0xFFFEFFFF) 81 #error Devices memory layout overlaps reset vectors range! 82 #endif 83 84 /* 85 * Integrated SoC peripherals addresses 86 */ 87 #define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ 88 #define MV_DDR_CADR_BASE (MV_BASE + 0x1500) 89 #define MV_MPP_BASE (MV_BASE + 0x10000) 90 91 #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 92 #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 93 #define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) 94 95 #define MV_PCI_BASE (MV_BASE + 0x30000) 96 #define MV_PCI_SIZE 0x2000 97 98 #define MV_PCIE_BASE (MV_BASE + 0x40000) 99 #define MV_PCIE_SIZE 0x2000 100 101 #define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000) 102 #define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) 103 #define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) 104 #define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) 105 #define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) 106 #define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) 107 #define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) 108 #define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) 109 110 #define MV_DEV_CS0_BASE MV_DEV_CS0_PHYS_BASE 111 112 /* 113 * Decode windows definitions and macros 114 */ 115 #define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 116 #define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 117 #define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 118 #define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 119 #if defined(SOC_MV_DISCOVERY) 120 #define MV_WIN_CPU_MAX 14 121 #else 122 #define MV_WIN_CPU_MAX 8 123 #endif 124 125 #define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) 126 #define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) 127 #define MV_WIN_DDR_MAX 4 128 129 #define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xa04) 130 #define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xa00) 131 #define MV_WIN_CESA_MAX 4 132 133 #if defined(SOC_MV_DISCOVERY) 134 #define MV_WIN_CESA_TARGET 9 135 #define MV_WIN_CESA_ATTR 1 136 #else 137 #define MV_WIN_CESA_TARGET 3 138 #define MV_WIN_CESA_ATTR 0 139 #endif 140 141 #define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x0) 142 #define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x4) 143 #define MV_WIN_USB_MAX 4 144 145 #define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) 146 #define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) 147 #define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) 148 #define MV_WIN_ETH_MAX 6 149 150 #define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) 151 #define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) 152 #define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) 153 #define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) 154 #define MV_WIN_IDMA_MAX 8 155 #define MV_IDMA_CHAN_MAX 4 156 157 #define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100) 158 #define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100) 159 #define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100) 160 #define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100) 161 #define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100) 162 #define MV_WIN_XOR_MAX 8 163 #define MV_XOR_CHAN_MAX 2 164 #define MV_XOR_NON_REMAP 4 165 166 #if defined(SOC_MV_DISCOVERY) 167 #define MV_WIN_PCIE_MEM_TARGET 4 168 #define MV_WIN_PCIE_MEM_ATTR 0xE8 169 #define MV_WIN_PCIE_IO_TARGET 4 170 #define MV_WIN_PCIE_IO_ATTR 0xE0 171 #elif defined(SOC_MV_KIRKWOOD) 172 #define MV_WIN_PCIE_MEM_TARGET 4 173 #define MV_WIN_PCIE_MEM_ATTR 0xE8 174 #define MV_WIN_PCIE_IO_TARGET 4 175 #define MV_WIN_PCIE_IO_ATTR 0xE0 176 #elif defined(SOC_MV_ORION) 177 #define MV_WIN_PCIE_MEM_TARGET 4 178 #define MV_WIN_PCIE_MEM_ATTR 0x59 179 #define MV_WIN_PCIE_IO_TARGET 4 180 #define MV_WIN_PCIE_IO_ATTR 0x51 181 #define MV_WIN_PCI_MEM_TARGET 3 182 #define MV_WIN_PCI_MEM_ATTR 0x59 183 #define MV_WIN_PCI_IO_TARGET 3 184 #define MV_WIN_PCI_IO_ATTR 0x51 185 #endif 186 187 #define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ 188 (n) + 1) + 0x1820) 189 #define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ 190 (n) + 1) + 0x1824) 191 #define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ 192 (n) + 1) + 0x182C) 193 #define MV_WIN_PCIE_MAX 6 194 195 #define MV_PCIE_BAR(n) (0x04 * (n) + 0x1804) 196 #define MV_PCIE_BAR_MAX 3 197 198 #define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) 199 #define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) 200 #define MV_WIN_SATA_MAX 4 201 202 #define WIN_REG_IDX_RD(pre,reg,off,base) \ 203 static __inline uint32_t \ 204 pre ## _ ## reg ## _read(int i) \ 205 { \ 206 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 207 } 208 209 #define WIN_REG_IDX_RD2(pre,reg,off,base) \ 210 static __inline uint32_t \ 211 pre ## _ ## reg ## _read(int i, int j) \ 212 { \ 213 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 214 } \ 215 216 #define WIN_REG_BASE_IDX_RD(pre,reg,off) \ 217 static __inline uint32_t \ 218 pre ## _ ## reg ## _read(uint32_t base, int i) \ 219 { \ 220 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 221 } 222 223 #define WIN_REG_BASE_IDX_RD2(pre,reg,off) \ 224 static __inline uint32_t \ 225 pre ## _ ## reg ## _read(uint32_t base, int i, int j) \ 226 { \ 227 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 228 } 229 230 #define WIN_REG_IDX_WR(pre,reg,off,base) \ 231 static __inline void \ 232 pre ## _ ## reg ## _write(int i, uint32_t val) \ 233 { \ 234 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 235 } 236 237 #define WIN_REG_IDX_WR2(pre,reg,off,base) \ 238 static __inline void \ 239 pre ## _ ## reg ## _write(int i, int j, uint32_t val) \ 240 { \ 241 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 242 } 243 244 #define WIN_REG_BASE_IDX_WR(pre,reg,off) \ 245 static __inline void \ 246 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ 247 { \ 248 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 249 } 250 251 #define WIN_REG_BASE_IDX_WR2(pre,reg,off) \ 252 static __inline void \ 253 pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val) \ 254 { \ 255 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 256 } 257 258 #define WIN_REG_RD(pre,reg,off,base) \ 259 static __inline uint32_t \ 260 pre ## _ ## reg ## _read(void) \ 261 { \ 262 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 263 } 264 265 #define WIN_REG_BASE_RD(pre,reg,off) \ 266 static __inline uint32_t \ 267 pre ## _ ## reg ## _read(uint32_t base) \ 268 { \ 269 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 270 } 271 272 #define WIN_REG_WR(pre,reg,off,base) \ 273 static __inline void \ 274 pre ## _ ## reg ## _write(uint32_t val) \ 275 { \ 276 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 277 } 278 279 #define WIN_REG_BASE_WR(pre,reg,off) \ 280 static __inline void \ 281 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ 282 { \ 283 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 284 } 285 286 #endif /* _MVWIN_H_ */
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