1 /*-
2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD: releng/11.0/sys/arm/mv/orion/db88f5xxx.c 298627 2016-04-26 11:53:37Z br $");
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/bus.h>
38 #include <sys/kernel.h>
39
40 #include <vm/vm.h>
41 #include <vm/pmap.h>
42
43 #include <machine/bus.h>
44 #include <machine/intr.h>
45 #include <machine/vmparam.h>
46
47 #include <arm/mv/mvreg.h>
48 #include <arm/mv/mvvar.h>
49 #include <arm/mv/mvwin.h>
50
51 /*
52 * Virtual address space layout:
53 * -----------------------------
54 * 0x0000_0000 - 0xbfff_ffff : user process
55 *
56 * 0xc040_0000 - virtual_avail : kernel reserved (text, data, page tables
57 * : structures, ARM stacks etc.)
58 * virtual_avail - 0xefff_ffff : KVA (virtual_avail is typically < 0xc0a0_0000)
59 * 0xf000_0000 - 0xf0ff_ffff : no-cache allocation area (16MB)
60 * 0xf100_0000 - 0xf10f_ffff : SoC integrated devices registers range (1MB)
61 * 0xf110_0000 - 0xf11f_ffff : PCI-Express I/O space (1MB)
62 * 0xf120_0000 - 0xf12f_ffff : PCI I/O space (1MB)
63 * 0xf130_0000 - 0xf52f_ffff : PCI-Express memory space (64MB)
64 * 0xf530_0000 - 0xf92f_ffff : PCI memory space (64MB)
65 * 0xf930_0000 - 0xfffe_ffff : unused (~108MB)
66 * 0xffff_0000 - 0xffff_0fff : 'high' vectors page (4KB)
67 * 0xffff_1000 - 0xffff_1fff : ARM_TP_ADDRESS/RAS page (4KB)
68 * 0xffff_2000 - 0xffff_ffff : unused (~55KB)
69 */
70
71
72 #if 0
73 int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin);
74
75 /* Static device mappings. */
76 const struct devmap_entry db88f5xxx_devmap[] = {
77 /*
78 * Map the on-board devices VA == PA so that we can access them
79 * with the MMU on or off.
80 */
81 { /* SoC integrated peripherals registers range */
82 MV_BASE,
83 MV_PHYS_BASE,
84 MV_SIZE,
85 },
86 { /* PCIE I/O */
87 MV_PCIE_IO_BASE,
88 MV_PCIE_IO_PHYS_BASE,
89 MV_PCIE_IO_SIZE,
90 },
91 { /* PCIE Memory */
92 MV_PCIE_MEM_BASE,
93 MV_PCIE_MEM_PHYS_BASE,
94 MV_PCIE_MEM_SIZE,
95 },
96 { /* PCI I/O */
97 MV_PCI_IO_BASE,
98 MV_PCI_IO_PHYS_BASE,
99 MV_PCI_IO_SIZE,
100 },
101 { /* PCI Memory */
102 MV_PCI_MEM_BASE,
103 MV_PCI_MEM_PHYS_BASE,
104 MV_PCI_MEM_SIZE,
105 },
106 { /* 7-seg LED */
107 MV_DEV_CS0_BASE,
108 MV_DEV_CS0_PHYS_BASE,
109 MV_DEV_CS0_SIZE,
110 },
111 { 0, 0, 0, }
112 };
113
114 /*
115 * The pci_irq_map table consists of 3 columns:
116 * - PCI slot number (less than zero means ANY).
117 * - PCI IRQ pin (less than zero means ANY).
118 * - PCI IRQ (less than zero marks end of table).
119 *
120 * IRQ number from the first matching entry is used to configure PCI device
121 */
122
123 /* PCI IRQ Map for DB-88F5281 */
124 const struct obio_pci_irq_map pci_irq_map[] = {
125 { 7, -1, GPIO2IRQ(12) },
126 { 8, -1, GPIO2IRQ(13) },
127 { 9, -1, GPIO2IRQ(13) },
128 { -1, -1, -1 }
129 };
130
131 /* PCI IRQ Map for DB-88F5182 */
132 const struct obio_pci_irq_map pci_irq_map[] = {
133 { 7, -1, GPIO2IRQ(0) },
134 { 8, -1, GPIO2IRQ(1) },
135 { 9, -1, GPIO2IRQ(1) },
136 { -1, -1, -1 }
137 };
138 #endif
139
140 #if 0
141 /*
142 * mv_gpio_config row structure:
143 * <GPIO number>, <GPIO flags>, <GPIO mode>
144 *
145 * - GPIO pin number (less than zero marks end of table)
146 * - GPIO flags:
147 * MV_GPIO_BLINK
148 * MV_GPIO_POLAR_LOW
149 * MV_GPIO_EDGE
150 * MV_GPIO_LEVEL
151 * - GPIO mode:
152 * 1 - Output, set to HIGH.
153 * 0 - Output, set to LOW.
154 * -1 - Input.
155 */
156
157 /* GPIO Configuration for DB-88F5281 */
158 const struct gpio_config mv_gpio_config[] = {
159 { 12, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
160 { 13, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
161 { -1, -1, -1 }
162 };
163
164 #if 0
165 /* GPIO Configuration for DB-88F5182 */
166 const struct gpio_config mv_gpio_config[] = {
167 { 0, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
168 { 1, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
169 { -1, -1, -1 }
170 };
171 #endif
172
173 #endif
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