The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/orion/db88f5xxx.c

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
    3  * All rights reserved.
    4  *
    5  * Developed by Semihalf.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. Neither the name of MARVELL nor the names of contributors
   16  *    may be used to endorse or promote products derived from this software
   17  *    without specific prior written permission.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  */
   31 
   32 #include <sys/cdefs.h>
   33 __FBSDID("$FreeBSD: releng/8.2/sys/arm/mv/orion/db88f5xxx.c 197251 2009-09-16 12:07:58Z raj $");
   34 
   35 #include <sys/param.h>
   36 #include <sys/systm.h>
   37 #include <sys/bus.h>
   38 #include <sys/kernel.h>
   39 
   40 #include <vm/vm.h>
   41 #include <vm/pmap.h>
   42 
   43 #include <machine/bus.h>
   44 #include <machine/intr.h>
   45 #include <machine/pte.h>
   46 #include <machine/pmap.h>
   47 #include <machine/vmparam.h>
   48 
   49 #include <arm/mv/mvreg.h>
   50 #include <arm/mv/mvvar.h>
   51 #include <arm/mv/mvwin.h>
   52 
   53 /*
   54  * Virtual address space layout:
   55  * -----------------------------
   56  * 0x0000_0000 - 0xbfff_ffff    : user process
   57  *
   58  * 0xc040_0000 - virtual_avail  : kernel reserved (text, data, page tables
   59  *                              : structures, ARM stacks etc.)
   60  * virtual_avail - 0xefff_ffff  : KVA (virtual_avail is typically < 0xc0a0_0000)
   61  * 0xf000_0000 - 0xf0ff_ffff    : no-cache allocation area (16MB)
   62  * 0xf100_0000 - 0xf10f_ffff    : SoC integrated devices registers range (1MB)
   63  * 0xf110_0000 - 0xf11f_ffff    : PCI-Express I/O space (1MB)
   64  * 0xf120_0000 - 0xf12f_ffff    : PCI I/O space (1MB)
   65  * 0xf130_0000 - 0xf52f_ffff    : PCI-Express memory space (64MB)
   66  * 0xf530_0000 - 0xf92f_ffff    : PCI memory space (64MB)
   67  * 0xf930_0000 - 0xfffe_ffff    : unused (~108MB)
   68  * 0xffff_0000 - 0xffff_0fff    : 'high' vectors page (4KB)
   69  * 0xffff_1000 - 0xffff_1fff    : ARM_TP_ADDRESS/RAS page (4KB)
   70  * 0xffff_2000 - 0xffff_ffff    : unused (~55KB)
   71  */
   72 
   73 int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin);
   74 
   75 /* Static device mappings. */
   76 const struct pmap_devmap pmap_devmap[] = {
   77         /*
   78          * Map the on-board devices VA == PA so that we can access them
   79          * with the MMU on or off.
   80          */
   81         { /* SoC integrated peripherals registers range */
   82                 MV_BASE,
   83                 MV_PHYS_BASE,
   84                 MV_SIZE,
   85                 VM_PROT_READ | VM_PROT_WRITE,
   86                 PTE_NOCACHE,
   87         },
   88         { /* PCIE I/O */
   89                 MV_PCIE_IO_BASE,
   90                 MV_PCIE_IO_PHYS_BASE,
   91                 MV_PCIE_IO_SIZE,
   92                 VM_PROT_READ | VM_PROT_WRITE,
   93                 PTE_NOCACHE,
   94         },
   95         { /* PCIE Memory */
   96                 MV_PCIE_MEM_BASE,
   97                 MV_PCIE_MEM_PHYS_BASE,
   98                 MV_PCIE_MEM_SIZE,
   99                 VM_PROT_READ | VM_PROT_WRITE,
  100                 PTE_NOCACHE,
  101         },
  102         { /* PCI I/O */
  103                 MV_PCI_IO_BASE,
  104                 MV_PCI_IO_PHYS_BASE,
  105                 MV_PCI_IO_SIZE,
  106                 VM_PROT_READ | VM_PROT_WRITE,
  107                 PTE_NOCACHE,
  108         },
  109         { /* PCI Memory */
  110                 MV_PCI_MEM_BASE,
  111                 MV_PCI_MEM_PHYS_BASE,
  112                 MV_PCI_MEM_SIZE,
  113                 VM_PROT_READ | VM_PROT_WRITE,
  114                 PTE_NOCACHE,
  115         },
  116         { /* 7-seg LED */
  117                 MV_DEV_CS0_BASE,
  118                 MV_DEV_CS0_PHYS_BASE,
  119                 MV_DEV_CS0_SIZE,
  120                 VM_PROT_READ | VM_PROT_WRITE,
  121                 PTE_NOCACHE,
  122         },
  123         { 0, 0, 0, 0, 0, }
  124 };
  125 
  126 /*
  127  * The pci_irq_map table consists of 3 columns:
  128  * - PCI slot number (less than zero means ANY).
  129  * - PCI IRQ pin (less than zero means ANY).
  130  * - PCI IRQ (less than zero marks end of table).
  131  *
  132  * IRQ number from the first matching entry is used to configure PCI device
  133  */
  134 
  135 /* PCI IRQ Map for DB-88F5281 */
  136 const struct obio_pci_irq_map pci_irq_map[] = {
  137         { 7, -1, GPIO2IRQ(12) },
  138         { 8, -1, GPIO2IRQ(13) },
  139         { 9, -1, GPIO2IRQ(13) },
  140         { -1, -1, -1 }
  141 };
  142 
  143 #if 0
  144 /* PCI IRQ Map for DB-88F5182 */
  145 const struct obio_pci_irq_map pci_irq_map[] = {
  146         { 7, -1, GPIO2IRQ(0) },
  147         { 8, -1, GPIO2IRQ(1) },
  148         { 9, -1, GPIO2IRQ(1) },
  149         { -1, -1, -1 }
  150 };
  151 #endif
  152 
  153 /*
  154  * mv_gpio_config row structure:
  155  *      <GPIO number>, <GPIO flags>, <GPIO mode>
  156  *
  157  * - GPIO pin number (less than zero marks end of table)
  158  * - GPIO flags:
  159  *      MV_GPIO_BLINK
  160  *      MV_GPIO_POLAR_LOW
  161  *      MV_GPIO_EDGE
  162  *      MV_GPIO_LEVEL
  163  * - GPIO mode:
  164  *      1       - Output, set to HIGH.
  165  *      0       - Output, set to LOW.
  166  *      -1      - Input.
  167  */
  168 
  169 /* GPIO Configuration for DB-88F5281 */
  170 const struct gpio_config mv_gpio_config[] = {
  171         { 12, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
  172         { 13, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
  173         { -1, -1, -1 }
  174 };
  175 
  176 #if 0
  177 /* GPIO Configuration for DB-88F5182 */
  178 const struct gpio_config mv_gpio_config[] = {
  179         { 0, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
  180         { 1, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
  181         { -1, -1, -1 }
  182 };
  183 #endif
  184 
  185 void
  186 platform_mpp_init(void)
  187 {
  188 
  189         /*
  190          * MPP configuration for DB-88F5281
  191          *
  192          * MPP[2]:  PCI_REQn[3]
  193          * MPP[3]:  PCI_GNTn[3]
  194          * MPP[4]:  PCI_REQn[4]
  195          * MPP[5]:  PCI_GNTn[4]
  196          * MPP[6]:  <UNKNOWN>
  197          * MPP[7]:  <UNKNOWN>
  198          * MPP[8]:  <UNKNOWN>
  199          * MPP[9]:  <UNKNOWN>
  200          * MPP[14]: NAND Flash REn[2]
  201          * MPP[15]: NAND Flash WEn[2]
  202          * MPP[16]: UA1_RXD
  203          * MPP[17]: UA1_TXD
  204          * MPP[18]: UA1_CTS
  205          * MPP[19]: UA1_RTS
  206          *
  207          * Others:  GPIO
  208          *
  209          * <UNKNOWN> entries are not documented, not on the schematics etc.
  210          */
  211         bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL0, 0x33222203);
  212         bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL1, 0x44000033);
  213         bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL2, 0x00000000);
  214 
  215 #if 0
  216         /*
  217          * MPP configuration for DB-88F5182
  218          *
  219          * MPP[2]:  PCI_REQn[3]
  220          * MPP[3]:  PCI_GNTn[3]
  221          * MPP[4]:  PCI_REQn[4]
  222          * MPP[5]:  PCI_GNTn[4]
  223          * MPP[6]:  SATA0_ACT
  224          * MPP[7]:  SATA1_ACT
  225          * MPP[12]: SATA0_PRESENT
  226          * MPP[13]: SATA1_PRESENT
  227          * MPP[14]: NAND_FLASH_REn[2]
  228          * MPP[15]: NAND_FLASH_WEn[2]
  229          * MPP[16]: UA1_RXD
  230          * MPP[17]: UA1_TXD
  231          * MPP[18]: UA1_CTS
  232          * MPP[19]: UA1_RTS
  233          *
  234          * Others:  GPIO
  235          */
  236         bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL0, 0x55222203);
  237         bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL1, 0x44550000);
  238         bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL2, 0x00000000);
  239 #endif
  240 }
  241 
  242 static void
  243 platform_identify(void *dummy)
  244 {
  245 
  246         soc_identify();
  247 
  248         /*
  249          * XXX Board identification e.g. read out from FPGA or similar should
  250          * go here
  251          */
  252 }
  253 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, NULL);

Cache object: 7b62f7ceb50dc8aeb99654226bba7af1


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.