The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/orion/orion.c

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    1 /*-
    2  * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
    3  * All rights reserved.
    4  *
    5  * Developed by Semihalf.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. Neither the name of MARVELL nor the names of contributors
   16  *    may be used to endorse or promote products derived from this software
   17  *    without specific prior written permission.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  */
   31 
   32 #include <sys/cdefs.h>
   33 __FBSDID("$FreeBSD: releng/8.4/sys/arm/mv/orion/orion.c 194949 2009-06-25 10:03:51Z raj $");
   34 
   35 #include <sys/param.h>
   36 #include <sys/systm.h>
   37 #include <sys/bus.h>
   38 
   39 #include <machine/bus.h>
   40 
   41 #include <arm/mv/mvreg.h>
   42 #include <arm/mv/mvvar.h>
   43 #include <arm/mv/mvwin.h>
   44 
   45 extern const struct obio_pci_irq_map pci_irq_map[];
   46 
   47 struct obio_device obio_devices[] = {
   48         { "ic", MV_IC_BASE, MV_IC_SIZE,
   49                 { -1 },
   50                 { -1 },
   51                 CPU_PM_CTRL_NONE
   52         },
   53         { "timer", MV_TIMERS_BASE, MV_TIMERS_SIZE,
   54                 { MV_INT_BRIDGE, -1 },
   55                 { -1 },
   56                 CPU_PM_CTRL_NONE
   57         },
   58         { "gpio", MV_GPIO_BASE, MV_GPIO_SIZE,
   59                 { MV_INT_GPIO7_0, MV_INT_GPIO15_8,
   60                   MV_INT_GPIO23_16, MV_INT_GPIO31_24, -1 },
   61                 { -1 },
   62                 CPU_PM_CTRL_NONE
   63         },
   64         { "uart", MV_UART0_BASE, MV_UART_SIZE,
   65                 { MV_INT_UART0, -1 },
   66                 { -1 },
   67                 CPU_PM_CTRL_NONE
   68         },
   69         { "uart", MV_UART1_BASE, MV_UART_SIZE,
   70                 { MV_INT_UART1, -1 },
   71                 { -1 },
   72                 CPU_PM_CTRL_NONE
   73         },
   74         { "idma", MV_IDMA_BASE, MV_IDMA_SIZE,
   75                 { MV_INT_IDMA_ERR, MV_INT_IDMA0, MV_INT_IDMA1,
   76                   MV_INT_IDMA2, MV_INT_IDMA3, -1 },
   77                 { -1 },
   78                 CPU_PM_CTRL_NONE
   79         },
   80         { "ehci", MV_USB0_BASE, MV_USB_SIZE,
   81                 { MV_INT_USB_BERR, MV_INT_USB_CI, -1 },
   82                 { -1 },
   83                 CPU_PM_CTRL_NONE
   84         },
   85         { "mge", MV_ETH0_BASE, MV_ETH_SIZE,
   86                 { MV_INT_GBERX, MV_INT_GBETX, MV_INT_GBEMISC,
   87                   MV_INT_GBESUM, MV_INT_GBEERR, -1 },
   88                 { -1 },
   89                 CPU_PM_CTRL_NONE
   90         },
   91         { "twsi", MV_TWSI0_BASE, MV_TWSI_SIZE,
   92                 { -1 }, { -1 },
   93                 CPU_PM_CTRL_NONE
   94         },
   95         { "sata", MV_SATAHC_BASE, MV_SATAHC_SIZE,
   96                 { MV_INT_SATA, -1 }, { -1 },
   97                 CPU_PM_CTRL_NONE
   98         },
   99         { NULL, 0, 0, { 0 } }
  100 };
  101 
  102 const struct obio_pci mv_pci_info[] = {
  103         { MV_TYPE_PCIE,
  104                 MV_PCIE_BASE,   MV_PCIE_SIZE,
  105                 MV_PCIE_IO_BASE, MV_PCIE_IO_SIZE,       4, 0x51,
  106                 MV_PCIE_MEM_BASE, MV_PCIE_MEM_SIZE,     4, 0x59,
  107                 NULL, MV_INT_PEX0
  108         },
  109 
  110         { MV_TYPE_PCI,
  111                 MV_PCI_BASE, MV_PCI_SIZE,
  112                 MV_PCI_IO_BASE, MV_PCI_IO_SIZE,         3, 0x51,
  113                 MV_PCI_MEM_BASE, MV_PCI_MEM_SIZE,       3, 0x59,
  114                 pci_irq_map, -1
  115         },
  116 
  117         { 0, 0, 0 }
  118 };
  119 
  120 struct resource_spec mv_gpio_res[] = {
  121         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  122         { SYS_RES_IRQ,          0,      RF_ACTIVE },
  123         { SYS_RES_IRQ,          1,      RF_ACTIVE },
  124         { SYS_RES_IRQ,          2,      RF_ACTIVE },
  125         { SYS_RES_IRQ,          3,      RF_ACTIVE },
  126         { -1, 0 }
  127 };
  128 
  129 const struct decode_win cpu_win_tbl[] = {
  130         /* Device bus BOOT */
  131         { 1, 0x0f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 },
  132 
  133         /* Device bus CS0 */
  134         { 1, 0x1e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 },
  135 
  136         /* Device bus CS1 */
  137         { 1, 0x1d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 },
  138 
  139         /* Device bus CS2 */
  140         { 1, 0x1b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 },
  141 };
  142 const struct decode_win *cpu_wins = cpu_win_tbl;
  143 int cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win);
  144 
  145 /*
  146  * Note: the decode windows table for IDMA does not explicitly have DRAM
  147  * entries, which are not statically defined: active DDR banks (== windows)
  148  * are established in run time from actual DDR windows settings. All active
  149  * DDR banks are mapped into IDMA decode windows, so at least one IDMA decode
  150  * window is occupied by the DDR bank; in case when all (MV_WIN_DDR_MAX)
  151  * DDR banks are active, the remaining available IDMA decode windows for other
  152  * targets is only MV_WIN_IDMA_MAX - MV_WIN_DDR_MAX.
  153  */
  154 const struct decode_win idma_win_tbl[] = {
  155         /* PCIE MEM */
  156         { 4, 0x59, MV_PCIE_MEM_PHYS_BASE, MV_PCIE_MEM_SIZE, -1 },
  157 
  158         /* PCI MEM */
  159         { 3, 0x59, MV_PCI_MEM_PHYS_BASE, MV_PCI_MEM_SIZE, -1 },
  160 
  161         /* Device bus BOOT */
  162         { 1, 0x0f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 },
  163 
  164         /* Device bus CS0 */
  165         { 1, 0x1e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 },
  166 
  167         /* Device bus CS1 */
  168         { 1, 0x1d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 },
  169 
  170         /* Device bus CS2 */
  171         { 1, 0x1b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 },
  172 };
  173 const struct decode_win *idma_wins = idma_win_tbl;
  174 int idma_wins_no = sizeof(idma_win_tbl) / sizeof(struct decode_win);
  175 
  176 uint32_t
  177 get_tclk(void)
  178 {
  179         uint32_t sar;
  180 
  181         /*
  182          * On Orion TCLK is can be configured to 150 MHz or 166 MHz.
  183          * Current setting is read from Sample At Reset register.
  184          */
  185         sar = bus_space_read_4(obio_tag, MV_MPP_BASE, SAMPLE_AT_RESET);
  186         sar = (sar & TCLK_MASK) >> TCLK_SHIFT;
  187         switch (sar) {
  188         case 1:
  189                 return (TCLK_150MHZ);
  190         case 2:
  191                 return (TCLK_166MHZ);
  192         default:
  193                 panic("Unknown TCLK settings!");
  194         }
  195 }

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