The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/timer.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2006 Benno Rice.
    5  * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
    6  * All rights reserved.
    7  *
    8  * Adapted to Marvell SoC by Semihalf.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   24  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   29  *
   30  * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
   31  */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD: head/sys/arm/mv/timer.c 332011 2018-04-04 12:30:52Z mw $");
   35 
   36 #include <sys/param.h>
   37 #include <sys/systm.h>
   38 #include <sys/bus.h>
   39 #include <sys/kernel.h>
   40 #include <sys/module.h>
   41 #include <sys/malloc.h>
   42 #include <sys/rman.h>
   43 #include <sys/timeet.h>
   44 #include <sys/timetc.h>
   45 #include <sys/watchdog.h>
   46 #include <machine/bus.h>
   47 #include <machine/cpu.h>
   48 #include <machine/intr.h>
   49 #include <machine/machdep.h>
   50 
   51 #include <arm/mv/mvreg.h>
   52 #include <arm/mv/mvvar.h>
   53 
   54 #include <dev/ofw/ofw_bus.h>
   55 #include <dev/ofw/ofw_bus_subr.h>
   56 
   57 #define INITIAL_TIMECOUNTER     (0xffffffff)
   58 #define MAX_WATCHDOG_TICKS      (0xffffffff)
   59 
   60 #define MV_TMR  0x1
   61 #define MV_WDT  0x2
   62 #define MV_NONE 0x0
   63 
   64 #define MV_CLOCK_SRC_ARMV7      25000000        /* Timers' 25MHz mode */
   65 
   66 #define WATCHDOG_TIMER_ARMV5            2
   67 
   68 typedef void (*mv_watchdog_enable_t)(void);
   69 typedef void (*mv_watchdog_disable_t)(void);
   70 
   71 struct mv_timer_config {
   72         enum soc_family         soc_family;
   73         mv_watchdog_enable_t    watchdog_enable;
   74         mv_watchdog_disable_t   watchdog_disable;
   75         unsigned int            clock_src;
   76         uint32_t                bridge_irq_cause;
   77         uint32_t                irq_timer0_clr;
   78         uint32_t                irq_timer_wd_clr;
   79 };
   80 
   81 struct mv_timer_softc {
   82         struct resource *       timer_res[2];
   83         bus_space_tag_t         timer_bst;
   84         bus_space_handle_t      timer_bsh;
   85         struct mtx              timer_mtx;
   86         struct eventtimer       et;
   87         boolean_t               has_wdt;
   88         struct mv_timer_config* config;
   89 };
   90 
   91 static struct resource_spec mv_timer_spec[] = {
   92         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
   93         { SYS_RES_IRQ,          0,      RF_ACTIVE | RF_OPTIONAL },
   94         { -1, 0 }
   95 };
   96 
   97 /* Interrupt is not required by MV_WDT devices */
   98 static struct ofw_compat_data mv_timer_compat[] = {
   99         {"marvell,armada-380-timer",    MV_NONE },
  100         {"marvell,armada-xp-timer",     MV_TMR | MV_WDT },
  101         {"mrvl,timer",                  MV_TMR | MV_WDT },
  102         {NULL,                          MV_NONE }
  103 };
  104 
  105 static struct mv_timer_softc *timer_softc = NULL;
  106 static int timers_initialized = 0;
  107 
  108 static int      mv_timer_probe(device_t);
  109 static int      mv_timer_attach(device_t);
  110 
  111 static int      mv_hardclock(void *);
  112 static unsigned mv_timer_get_timecount(struct timecounter *);
  113 
  114 static uint32_t mv_get_timer_control(void);
  115 static void     mv_set_timer_control(uint32_t);
  116 static uint32_t mv_get_timer(uint32_t);
  117 static void     mv_set_timer(uint32_t, uint32_t);
  118 static void     mv_set_timer_rel(uint32_t, uint32_t);
  119 static void     mv_watchdog_event(void *, unsigned int, int *);
  120 static int      mv_timer_start(struct eventtimer *et,
  121     sbintime_t first, sbintime_t period);
  122 static int      mv_timer_stop(struct eventtimer *et);
  123 static void     mv_setup_timers(void);
  124 
  125 static void mv_watchdog_enable_armv5(void);
  126 static void mv_watchdog_enable_armadaxp(void);
  127 static void mv_watchdog_disable_armv5(void);
  128 static void mv_watchdog_disable_armadaxp(void);
  129 
  130 static void mv_delay(int usec, void* arg);
  131 
  132 static struct mv_timer_config timer_armadaxp_config =
  133 {
  134         MV_SOC_ARMADA_XP,
  135         &mv_watchdog_enable_armadaxp,
  136         &mv_watchdog_disable_armadaxp,
  137         MV_CLOCK_SRC_ARMV7,
  138         BRIDGE_IRQ_CAUSE_ARMADAXP,
  139         IRQ_TIMER0_CLR_ARMADAXP,
  140         IRQ_TIMER_WD_CLR_ARMADAXP,
  141 };
  142 static struct mv_timer_config timer_armv5_config =
  143 {
  144         MV_SOC_ARMV5,
  145         &mv_watchdog_enable_armv5,
  146         &mv_watchdog_disable_armv5,
  147         0,
  148         BRIDGE_IRQ_CAUSE,
  149         IRQ_TIMER0_CLR,
  150         IRQ_TIMER_WD_CLR,
  151 };
  152 
  153 static struct ofw_compat_data mv_timer_soc_config[] = {
  154         {"marvell,armada-xp-timer",     (uintptr_t)&timer_armadaxp_config },
  155         {"mrvl,timer",                  (uintptr_t)&timer_armv5_config },
  156         {NULL,                          (uintptr_t)NULL },
  157 };
  158 
  159 static struct timecounter mv_timer_timecounter = {
  160         .tc_get_timecount = mv_timer_get_timecount,
  161         .tc_name = "CPUTimer1",
  162         .tc_frequency = 0,      /* This is assigned on the fly in the init sequence */
  163         .tc_counter_mask = ~0u,
  164         .tc_quality = 1000,
  165 };
  166 
  167 static int
  168 mv_timer_probe(device_t dev)
  169 {
  170 
  171         if (!ofw_bus_status_okay(dev))
  172                 return (ENXIO);
  173 
  174         if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data == MV_NONE)
  175                 return (ENXIO);
  176 
  177         device_set_desc(dev, "Marvell CPU Timer");
  178         return (0);
  179 }
  180 
  181 static int
  182 mv_timer_attach(device_t dev)
  183 {
  184         int     error;
  185         void    *ihl;
  186         struct  mv_timer_softc *sc;
  187         uint32_t irq_cause, irq_mask;
  188 
  189         if (timer_softc != NULL)
  190                 return (ENXIO);
  191 
  192         sc = (struct mv_timer_softc *)device_get_softc(dev);
  193         timer_softc = sc;
  194 
  195         sc->config = (struct mv_timer_config*)
  196             ofw_bus_search_compatible(dev, mv_timer_soc_config)->ocd_data;
  197 
  198         if (sc->config->clock_src == 0)
  199                 sc->config->clock_src = get_tclk();
  200 
  201         error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res);
  202         if (error) {
  203                 device_printf(dev, "could not allocate resources\n");
  204                 return (ENXIO);
  205         }
  206 
  207         sc->timer_bst = rman_get_bustag(sc->timer_res[0]);
  208         sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]);
  209 
  210         sc->has_wdt = ofw_bus_has_prop(dev, "mrvl,has-wdt");
  211 
  212         mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF);
  213 
  214         if (sc->has_wdt) {
  215                 if (sc->config->watchdog_disable)
  216                         sc->config->watchdog_disable();
  217                 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
  218         }
  219 
  220         if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data
  221             == MV_WDT) {
  222                 /* Don't set timers for wdt-only entry. */
  223                 device_printf(dev, "only watchdog attached\n");
  224                 return (0);
  225         } else if (sc->timer_res[1] == NULL) {
  226                 device_printf(dev, "no interrupt resource\n");
  227                 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
  228                 return (ENXIO);
  229         }
  230 
  231         if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
  232             mv_hardclock, NULL, sc, &ihl) != 0) {
  233                 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
  234                 device_printf(dev, "Could not setup interrupt.\n");
  235                 return (ENXIO);
  236         }
  237 
  238         mv_setup_timers();
  239         if (sc->config->soc_family != MV_SOC_ARMADA_XP ) {
  240                 irq_cause = read_cpu_ctrl(sc->config->bridge_irq_cause);
  241                 irq_cause &= sc->config->irq_timer0_clr;
  242 
  243                 write_cpu_ctrl(sc->config->bridge_irq_cause, irq_cause);
  244                 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
  245                 irq_mask |= IRQ_TIMER0_MASK;
  246                 irq_mask &= ~IRQ_TIMER1_MASK;
  247                 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
  248         }
  249         sc->et.et_name = "CPUTimer0";
  250         sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
  251         sc->et.et_quality = 1000;
  252 
  253         sc->et.et_frequency = sc->config->clock_src;
  254         sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
  255         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
  256         sc->et.et_start = mv_timer_start;
  257         sc->et.et_stop = mv_timer_stop;
  258         sc->et.et_priv = sc;
  259         et_register(&sc->et);
  260         mv_timer_timecounter.tc_frequency = sc->config->clock_src;
  261         tc_init(&mv_timer_timecounter);
  262 
  263 #ifdef PLATFORM
  264         arm_set_delay(mv_delay, NULL);
  265 #endif
  266         return (0);
  267 }
  268 
  269 static int
  270 mv_hardclock(void *arg)
  271 {
  272         struct  mv_timer_softc *sc;
  273         uint32_t irq_cause;
  274 
  275         irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
  276         irq_cause &= timer_softc->config->irq_timer0_clr;
  277         write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
  278 
  279         sc = (struct mv_timer_softc *)arg;
  280         if (sc->et.et_active)
  281                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
  282 
  283         return (FILTER_HANDLED);
  284 }
  285 
  286 static device_method_t mv_timer_methods[] = {
  287         DEVMETHOD(device_probe, mv_timer_probe),
  288         DEVMETHOD(device_attach, mv_timer_attach),
  289 
  290         { 0, 0 }
  291 };
  292 
  293 static driver_t mv_timer_driver = {
  294         "timer",
  295         mv_timer_methods,
  296         sizeof(struct mv_timer_softc),
  297 };
  298 
  299 static devclass_t mv_timer_devclass;
  300 
  301 DRIVER_MODULE(timer_mv, simplebus, mv_timer_driver, mv_timer_devclass, 0, 0);
  302 
  303 static unsigned
  304 mv_timer_get_timecount(struct timecounter *tc)
  305 {
  306 
  307         return (INITIAL_TIMECOUNTER - mv_get_timer(1));
  308 }
  309 
  310 static void
  311 mv_delay(int usec, void* arg)
  312 {
  313         uint32_t        val, val_temp;
  314         int32_t         nticks;
  315 
  316         val = mv_get_timer(1);
  317         nticks = ((timer_softc->config->clock_src / 1000000 + 1) * usec);
  318 
  319         while (nticks > 0) {
  320                 val_temp = mv_get_timer(1);
  321                 if (val > val_temp)
  322                         nticks -= (val - val_temp);
  323                 else
  324                         nticks -= (val + (INITIAL_TIMECOUNTER - val_temp));
  325 
  326                 val = val_temp;
  327         }
  328 }
  329 
  330 #ifndef PLATFORM
  331 void
  332 DELAY(int usec)
  333 {
  334         uint32_t        val;
  335 
  336         if (!timers_initialized) {
  337                 for (; usec > 0; usec--)
  338                         for (val = 100; val > 0; val--)
  339                                 __asm __volatile("nop" ::: "memory");
  340         } else {
  341                 TSENTER();
  342                 mv_delay(usec, NULL);
  343                 TSEXIT();
  344         }
  345 }
  346 #endif
  347 
  348 static uint32_t
  349 mv_get_timer_control(void)
  350 {
  351 
  352         return (bus_space_read_4(timer_softc->timer_bst,
  353             timer_softc->timer_bsh, CPU_TIMER_CONTROL));
  354 }
  355 
  356 static void
  357 mv_set_timer_control(uint32_t val)
  358 {
  359 
  360         bus_space_write_4(timer_softc->timer_bst,
  361             timer_softc->timer_bsh, CPU_TIMER_CONTROL, val);
  362 }
  363 
  364 static uint32_t
  365 mv_get_timer(uint32_t timer)
  366 {
  367 
  368         return (bus_space_read_4(timer_softc->timer_bst,
  369             timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8));
  370 }
  371 
  372 static void
  373 mv_set_timer(uint32_t timer, uint32_t val)
  374 {
  375 
  376         bus_space_write_4(timer_softc->timer_bst,
  377             timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val);
  378 }
  379 
  380 static void
  381 mv_set_timer_rel(uint32_t timer, uint32_t val)
  382 {
  383 
  384         bus_space_write_4(timer_softc->timer_bst,
  385             timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
  386 }
  387 
  388 static void
  389 mv_watchdog_enable_armv5(void)
  390 {
  391         uint32_t val, irq_cause, irq_mask;
  392 
  393         irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
  394         irq_cause &= timer_softc->config->irq_timer_wd_clr;
  395         write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
  396 
  397         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
  398         irq_mask |= IRQ_TIMER_WD_MASK;
  399         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
  400 
  401         val = read_cpu_ctrl(RSTOUTn_MASK);
  402         val |= WD_RST_OUT_EN;
  403         write_cpu_ctrl(RSTOUTn_MASK, val);
  404 
  405         val = mv_get_timer_control();
  406         val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
  407         mv_set_timer_control(val);
  408 }
  409 
  410 static void
  411 mv_watchdog_enable_armadaxp(void)
  412 {
  413         uint32_t irq_cause, val;
  414 
  415         irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
  416         irq_cause &= timer_softc->config->irq_timer_wd_clr;
  417         write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
  418 
  419         val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
  420         val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
  421         write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
  422 
  423         val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
  424         val &= ~RSTOUTn_MASK_WD;
  425         write_cpu_misc(RSTOUTn_MASK_ARMV7, val);
  426 
  427         val = mv_get_timer_control();
  428         val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
  429         mv_set_timer_control(val);
  430 }
  431 
  432 static void
  433 mv_watchdog_disable_armv5(void)
  434 {
  435         uint32_t val, irq_cause,irq_mask;
  436 
  437         val = mv_get_timer_control();
  438         val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
  439         mv_set_timer_control(val);
  440 
  441         val = read_cpu_ctrl(RSTOUTn_MASK);
  442         val &= ~WD_RST_OUT_EN;
  443         write_cpu_ctrl(RSTOUTn_MASK, val);
  444 
  445         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
  446         irq_mask &= ~(IRQ_TIMER_WD_MASK);
  447         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
  448 
  449         irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
  450         irq_cause &= timer_softc->config->irq_timer_wd_clr;
  451         write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
  452 }
  453 
  454 static void
  455 mv_watchdog_disable_armadaxp(void)
  456 {
  457         uint32_t val, irq_cause;
  458 
  459         val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
  460         val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
  461         write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
  462 
  463         val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
  464         val |= RSTOUTn_MASK_WD;
  465         write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD);
  466 
  467         irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);
  468         irq_cause &= timer_softc->config->irq_timer_wd_clr;
  469         write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);
  470 
  471         val = mv_get_timer_control();
  472         val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
  473         mv_set_timer_control(val);
  474 }
  475 
  476 /*
  477  * Watchdog event handler.
  478  */
  479 static void
  480 mv_watchdog_event(void *arg, unsigned int cmd, int *error)
  481 {
  482         uint64_t ns;
  483         uint64_t ticks;
  484 
  485         mtx_lock(&timer_softc->timer_mtx);
  486         if (cmd == 0) {
  487                 if (timer_softc->config->watchdog_disable != NULL)
  488                         timer_softc->config->watchdog_disable();
  489         } else {
  490                 /*
  491                  * Watchdog timeout is in nanosecs, calculation according to
  492                  * watchdog(9)
  493                  */
  494                 ns = (uint64_t)1 << (cmd & WD_INTERVAL);
  495                 ticks = (uint64_t)(ns * timer_softc->config->clock_src) / 1000000000;
  496                 if (ticks > MAX_WATCHDOG_TICKS) {
  497                         if (timer_softc->config->watchdog_disable != NULL)
  498                                 timer_softc->config->watchdog_disable();
  499                 } else {
  500                         mv_set_timer(WATCHDOG_TIMER_ARMV5, ticks);
  501                         if (timer_softc->config->watchdog_enable != NULL)
  502                                 timer_softc->config->watchdog_enable();
  503                         *error = 0;
  504                 }
  505         }
  506         mtx_unlock(&timer_softc->timer_mtx);
  507 }
  508 
  509 static int
  510 mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
  511 {
  512         struct  mv_timer_softc *sc;
  513         uint32_t val, val1;
  514 
  515         /* Calculate dividers. */
  516         sc = (struct mv_timer_softc *)et->et_priv;
  517         if (period != 0)
  518                 val = ((uint32_t)sc->et.et_frequency * period) >> 32;
  519         else
  520                 val = 0;
  521         if (first != 0)
  522                 val1 = ((uint32_t)sc->et.et_frequency * first) >> 32;
  523         else
  524                 val1 = val;
  525 
  526         /* Apply configuration. */
  527         mv_set_timer_rel(0, val);
  528         mv_set_timer(0, val1);
  529         val = mv_get_timer_control();
  530         val |= CPU_TIMER0_EN;
  531         if (period != 0)
  532                 val |= CPU_TIMER0_AUTO;
  533         else
  534                 val &= ~CPU_TIMER0_AUTO;
  535         mv_set_timer_control(val);
  536         return (0);
  537 }
  538 
  539 static int
  540 mv_timer_stop(struct eventtimer *et)
  541 {
  542         uint32_t val;
  543 
  544         val = mv_get_timer_control();
  545         val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
  546         mv_set_timer_control(val);
  547         return (0);
  548 }
  549 
  550 static void
  551 mv_setup_timers(void)
  552 {
  553         uint32_t val;
  554 
  555         mv_set_timer_rel(1, INITIAL_TIMECOUNTER);
  556         mv_set_timer(1, INITIAL_TIMECOUNTER);
  557         val = mv_get_timer_control();
  558         val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
  559         val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
  560 
  561         if (timer_softc->config->soc_family == MV_SOC_ARMADA_XP) {
  562                 /* Enable 25MHz mode */
  563                 val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
  564         }
  565 
  566         mv_set_timer_control(val);
  567         timers_initialized = 1;
  568 }

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