The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/timer.c

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    1 /*-
    2  * Copyright (c) 2006 Benno Rice.
    3  * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
    4  * All rights reserved.
    5  *
    6  * Adapted to Marvell SoC by Semihalf.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   27  *
   28  * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
   29  */
   30 
   31 #include <sys/cdefs.h>
   32 __FBSDID("$FreeBSD: releng/10.0/sys/arm/mv/timer.c 251371 2013-06-04 09:33:03Z gber $");
   33 
   34 #include <sys/param.h>
   35 #include <sys/systm.h>
   36 #include <sys/bus.h>
   37 #include <sys/kernel.h>
   38 #include <sys/module.h>
   39 #include <sys/malloc.h>
   40 #include <sys/rman.h>
   41 #include <sys/timeet.h>
   42 #include <sys/timetc.h>
   43 #include <sys/watchdog.h>
   44 #include <machine/bus.h>
   45 #include <machine/cpu.h>
   46 #include <machine/frame.h>
   47 #include <machine/intr.h>
   48 
   49 #include <arm/mv/mvreg.h>
   50 #include <arm/mv/mvvar.h>
   51 
   52 #include <dev/ofw/ofw_bus.h>
   53 #include <dev/ofw/ofw_bus_subr.h>
   54 
   55 #define INITIAL_TIMECOUNTER     (0xffffffff)
   56 #define MAX_WATCHDOG_TICKS      (0xffffffff)
   57 
   58 #if defined(SOC_MV_ARMADAXP)
   59 #define MV_CLOCK_SRC            25000000        /* Timers' 25MHz mode */
   60 #else
   61 #define MV_CLOCK_SRC            get_tclk()
   62 #endif
   63 
   64 struct mv_timer_softc {
   65         struct resource *       timer_res[2];
   66         bus_space_tag_t         timer_bst;
   67         bus_space_handle_t      timer_bsh;
   68         struct mtx              timer_mtx;
   69         struct eventtimer       et;
   70 };
   71 
   72 static struct resource_spec mv_timer_spec[] = {
   73         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
   74         { SYS_RES_IRQ,          0,      RF_ACTIVE },
   75         { -1, 0 }
   76 };
   77 
   78 static struct mv_timer_softc *timer_softc = NULL;
   79 static int timers_initialized = 0;
   80 
   81 static int      mv_timer_probe(device_t);
   82 static int      mv_timer_attach(device_t);
   83 
   84 static int      mv_hardclock(void *);
   85 static unsigned mv_timer_get_timecount(struct timecounter *);
   86 
   87 static uint32_t mv_get_timer_control(void);
   88 static void     mv_set_timer_control(uint32_t);
   89 static uint32_t mv_get_timer(uint32_t);
   90 static void     mv_set_timer(uint32_t, uint32_t);
   91 static void     mv_set_timer_rel(uint32_t, uint32_t);
   92 static void     mv_watchdog_enable(void);
   93 static void     mv_watchdog_disable(void);
   94 static void     mv_watchdog_event(void *, unsigned int, int *);
   95 static int      mv_timer_start(struct eventtimer *et,
   96     sbintime_t first, sbintime_t period);
   97 static int      mv_timer_stop(struct eventtimer *et);
   98 static void     mv_setup_timers(void);
   99 
  100 static struct timecounter mv_timer_timecounter = {
  101         .tc_get_timecount = mv_timer_get_timecount,
  102         .tc_name = "CPUTimer1",
  103         .tc_frequency = 0,      /* This is assigned on the fly in the init sequence */
  104         .tc_counter_mask = ~0u,
  105         .tc_quality = 1000,
  106 };
  107 
  108 static int
  109 mv_timer_probe(device_t dev)
  110 {
  111 
  112         if (!ofw_bus_is_compatible(dev, "mrvl,timer"))
  113                 return (ENXIO);
  114 
  115         device_set_desc(dev, "Marvell CPU Timer");
  116         return (0);
  117 }
  118 
  119 static int
  120 mv_timer_attach(device_t dev)
  121 {
  122         int     error;
  123         void    *ihl;
  124         struct  mv_timer_softc *sc;
  125 #if !defined(SOC_MV_ARMADAXP)
  126         uint32_t irq_cause, irq_mask;
  127 #endif
  128 
  129         if (timer_softc != NULL)
  130                 return (ENXIO);
  131 
  132         sc = (struct mv_timer_softc *)device_get_softc(dev);
  133         timer_softc = sc;
  134 
  135         error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res);
  136         if (error) {
  137                 device_printf(dev, "could not allocate resources\n");
  138                 return (ENXIO);
  139         }
  140 
  141         sc->timer_bst = rman_get_bustag(sc->timer_res[0]);
  142         sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]);
  143 
  144         mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF);
  145         mv_watchdog_disable();
  146         EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
  147 
  148         if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
  149             mv_hardclock, NULL, sc, &ihl) != 0) {
  150                 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
  151                 device_printf(dev, "Could not setup interrupt.\n");
  152                 return (ENXIO);
  153         }
  154 
  155         mv_setup_timers();
  156 #if !defined(SOC_MV_ARMADAXP)
  157         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
  158         irq_cause &= IRQ_TIMER0_CLR;
  159 
  160         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
  161         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
  162         irq_mask |= IRQ_TIMER0_MASK;
  163         irq_mask &= ~IRQ_TIMER1_MASK;
  164         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
  165 #endif
  166         sc->et.et_name = "CPUTimer0";
  167         sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
  168         sc->et.et_quality = 1000;
  169 
  170         sc->et.et_frequency = MV_CLOCK_SRC;
  171         sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
  172         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
  173         sc->et.et_start = mv_timer_start;
  174         sc->et.et_stop = mv_timer_stop;
  175         sc->et.et_priv = sc;
  176         et_register(&sc->et);
  177         mv_timer_timecounter.tc_frequency = MV_CLOCK_SRC;
  178         tc_init(&mv_timer_timecounter);
  179 
  180         return (0);
  181 }
  182 
  183 static int
  184 mv_hardclock(void *arg)
  185 {
  186         struct  mv_timer_softc *sc;
  187         uint32_t irq_cause;
  188 
  189         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
  190         irq_cause &= IRQ_TIMER0_CLR;
  191         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
  192 
  193         sc = (struct mv_timer_softc *)arg;
  194         if (sc->et.et_active)
  195                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
  196 
  197         return (FILTER_HANDLED);
  198 }
  199 
  200 static device_method_t mv_timer_methods[] = {
  201         DEVMETHOD(device_probe, mv_timer_probe),
  202         DEVMETHOD(device_attach, mv_timer_attach),
  203 
  204         { 0, 0 }
  205 };
  206 
  207 static driver_t mv_timer_driver = {
  208         "timer",
  209         mv_timer_methods,
  210         sizeof(struct mv_timer_softc),
  211 };
  212 
  213 static devclass_t mv_timer_devclass;
  214 
  215 DRIVER_MODULE(timer, simplebus, mv_timer_driver, mv_timer_devclass, 0, 0);
  216 
  217 static unsigned
  218 mv_timer_get_timecount(struct timecounter *tc)
  219 {
  220 
  221         return (INITIAL_TIMECOUNTER - mv_get_timer(1));
  222 }
  223 
  224 void
  225 cpu_initclocks(void)
  226 {
  227 
  228         cpu_initclocks_bsp();
  229 }
  230 
  231 void
  232 DELAY(int usec)
  233 {
  234         uint32_t        val, val_temp;
  235         int32_t         nticks;
  236 
  237         if (!timers_initialized) {
  238                 for (; usec > 0; usec--)
  239                         for (val = 100; val > 0; val--)
  240                                 __asm __volatile("nop" ::: "memory");
  241                 return;
  242         }
  243 
  244         val = mv_get_timer(1);
  245         nticks = ((MV_CLOCK_SRC / 1000000 + 1) * usec);
  246 
  247         while (nticks > 0) {
  248                 val_temp = mv_get_timer(1);
  249                 if (val > val_temp)
  250                         nticks -= (val - val_temp);
  251                 else
  252                         nticks -= (val + (INITIAL_TIMECOUNTER - val_temp));
  253 
  254                 val = val_temp;
  255         }
  256 }
  257 
  258 static uint32_t
  259 mv_get_timer_control(void)
  260 {
  261 
  262         return (bus_space_read_4(timer_softc->timer_bst,
  263             timer_softc->timer_bsh, CPU_TIMER_CONTROL));
  264 }
  265 
  266 static void
  267 mv_set_timer_control(uint32_t val)
  268 {
  269 
  270         bus_space_write_4(timer_softc->timer_bst,
  271             timer_softc->timer_bsh, CPU_TIMER_CONTROL, val);
  272 }
  273 
  274 static uint32_t
  275 mv_get_timer(uint32_t timer)
  276 {
  277 
  278         return (bus_space_read_4(timer_softc->timer_bst,
  279             timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8));
  280 }
  281 
  282 static void
  283 mv_set_timer(uint32_t timer, uint32_t val)
  284 {
  285 
  286         bus_space_write_4(timer_softc->timer_bst,
  287             timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val);
  288 }
  289 
  290 static void
  291 mv_set_timer_rel(uint32_t timer, uint32_t val)
  292 {
  293 
  294         bus_space_write_4(timer_softc->timer_bst,
  295             timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
  296 }
  297 
  298 static void
  299 mv_watchdog_enable(void)
  300 {
  301         uint32_t val, irq_cause;
  302 #if !defined(SOC_MV_ARMADAXP)
  303         uint32_t irq_mask;
  304 #endif
  305 
  306         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
  307         irq_cause &= IRQ_TIMER_WD_CLR;
  308         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
  309 
  310 #if defined(SOC_MV_ARMADAXP)
  311         val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
  312         val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
  313         write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
  314 #else
  315         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
  316         irq_mask |= IRQ_TIMER_WD_MASK;
  317         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
  318 
  319         val = read_cpu_ctrl(RSTOUTn_MASK);
  320         val |= WD_RST_OUT_EN;
  321         write_cpu_ctrl(RSTOUTn_MASK, val);
  322 #endif
  323 
  324         val = mv_get_timer_control();
  325         val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO;
  326 #if defined(SOC_MV_ARMADAXP)
  327         val |= CPU_TIMER_WD_25MHZ_EN;
  328 #endif
  329         mv_set_timer_control(val);
  330 }
  331 
  332 static void
  333 mv_watchdog_disable(void)
  334 {
  335         uint32_t val, irq_cause;
  336 #if !defined(SOC_MV_ARMADAXP)
  337         uint32_t irq_mask;
  338 #endif
  339 
  340         val = mv_get_timer_control();
  341         val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
  342         mv_set_timer_control(val);
  343 
  344 #if defined(SOC_MV_ARMADAXP)
  345         val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
  346         val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
  347         write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
  348 #else
  349         val = read_cpu_ctrl(RSTOUTn_MASK);
  350         val &= ~WD_RST_OUT_EN;
  351         write_cpu_ctrl(RSTOUTn_MASK, val);
  352 
  353         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
  354         irq_mask &= ~(IRQ_TIMER_WD_MASK);
  355         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
  356 #endif
  357 
  358         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
  359         irq_cause &= IRQ_TIMER_WD_CLR;
  360         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
  361 }
  362 
  363 
  364 /*
  365  * Watchdog event handler.
  366  */
  367 static void
  368 mv_watchdog_event(void *arg, unsigned int cmd, int *error)
  369 {
  370         uint64_t ns;
  371         uint64_t ticks;
  372 
  373         mtx_lock(&timer_softc->timer_mtx);
  374         if (cmd == 0)
  375                 mv_watchdog_disable();
  376         else {
  377                 /*
  378                  * Watchdog timeout is in nanosecs, calculation according to
  379                  * watchdog(9)
  380                  */
  381                 ns = (uint64_t)1 << (cmd & WD_INTERVAL);
  382                 ticks = (uint64_t)(ns * MV_CLOCK_SRC) / 1000000000;
  383                 if (ticks > MAX_WATCHDOG_TICKS)
  384                         mv_watchdog_disable();
  385                 else {
  386                         /* Timer 2 is the watchdog */
  387                         mv_set_timer(2, ticks);
  388                         mv_watchdog_enable();
  389                         *error = 0;
  390                 }
  391         }
  392         mtx_unlock(&timer_softc->timer_mtx);
  393 }
  394 
  395 static int
  396 mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
  397 {
  398         struct  mv_timer_softc *sc;
  399         uint32_t val, val1;
  400 
  401         /* Calculate dividers. */
  402         sc = (struct mv_timer_softc *)et->et_priv;
  403         if (period != 0)
  404                 val = ((uint32_t)sc->et.et_frequency * period) >> 32;
  405         else
  406                 val = 0;
  407         if (first != 0)
  408                 val1 = ((uint32_t)sc->et.et_frequency * first) >> 32;
  409         else
  410                 val1 = val;
  411 
  412         /* Apply configuration. */
  413         mv_set_timer_rel(0, val);
  414         mv_set_timer(0, val1);
  415         val = mv_get_timer_control();
  416         val |= CPU_TIMER0_EN;
  417         if (period != 0)
  418                 val |= CPU_TIMER0_AUTO;
  419         else
  420                 val &= ~CPU_TIMER0_AUTO;
  421         mv_set_timer_control(val);
  422         return (0);
  423 }
  424 
  425 static int
  426 mv_timer_stop(struct eventtimer *et)
  427 {
  428         uint32_t val;
  429 
  430         val = mv_get_timer_control();
  431         val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
  432         mv_set_timer_control(val);
  433         return (0);
  434 }
  435 
  436 static void
  437 mv_setup_timers(void)
  438 {
  439         uint32_t val;
  440 
  441         mv_set_timer_rel(1, INITIAL_TIMECOUNTER);
  442         mv_set_timer(1, INITIAL_TIMECOUNTER);
  443         val = mv_get_timer_control();
  444         val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
  445         val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
  446 #if defined(SOC_MV_ARMADAXP)
  447         /* Enable 25MHz mode */
  448         val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
  449 #endif
  450         mv_set_timer_control(val);
  451         timers_initialized = 1;
  452 }

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