The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/timer.c

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    1 /*-
    2  * Copyright (c) 2006 Benno Rice.
    3  * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
    4  * All rights reserved.
    5  *
    6  * Adapted to Marvell SoC by Semihalf.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   27  *
   28  * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
   29  */
   30 
   31 #include <sys/cdefs.h>
   32 __FBSDID("$FreeBSD: stable/9/sys/arm/mv/timer.c 218426 2011-02-08 01:43:45Z marcel $");
   33 
   34 #include <sys/param.h>
   35 #include <sys/systm.h>
   36 #include <sys/bus.h>
   37 #include <sys/kernel.h>
   38 #include <sys/module.h>
   39 #include <sys/malloc.h>
   40 #include <sys/rman.h>
   41 #include <sys/timeet.h>
   42 #include <sys/timetc.h>
   43 #include <sys/watchdog.h>
   44 #include <machine/bus.h>
   45 #include <machine/cpu.h>
   46 #include <machine/frame.h>
   47 #include <machine/intr.h>
   48 
   49 #include <arm/mv/mvreg.h>
   50 #include <arm/mv/mvvar.h>
   51 
   52 #include <dev/ofw/ofw_bus.h>
   53 #include <dev/ofw/ofw_bus_subr.h>
   54 
   55 #define INITIAL_TIMECOUNTER     (0xffffffff)
   56 #define MAX_WATCHDOG_TICKS      (0xffffffff)
   57 
   58 struct mv_timer_softc {
   59         struct resource *       timer_res[2];
   60         bus_space_tag_t         timer_bst;
   61         bus_space_handle_t      timer_bsh;
   62         struct mtx              timer_mtx;
   63         struct eventtimer       et;
   64 };
   65 
   66 static struct resource_spec mv_timer_spec[] = {
   67         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
   68         { SYS_RES_IRQ,          0,      RF_ACTIVE },
   69         { -1, 0 }
   70 };
   71 
   72 static struct mv_timer_softc *timer_softc = NULL;
   73 static int timers_initialized = 0;
   74 
   75 static int      mv_timer_probe(device_t);
   76 static int      mv_timer_attach(device_t);
   77 
   78 static int      mv_hardclock(void *);
   79 static unsigned mv_timer_get_timecount(struct timecounter *);
   80 
   81 static uint32_t mv_get_timer_control(void);
   82 static void     mv_set_timer_control(uint32_t);
   83 static uint32_t mv_get_timer(uint32_t);
   84 static void     mv_set_timer(uint32_t, uint32_t);
   85 static void     mv_set_timer_rel(uint32_t, uint32_t);
   86 static void     mv_watchdog_enable(void);
   87 static void     mv_watchdog_disable(void);
   88 static void     mv_watchdog_event(void *, unsigned int, int *);
   89 static int      mv_timer_start(struct eventtimer *et,
   90     struct bintime *first, struct bintime *period);
   91 static int      mv_timer_stop(struct eventtimer *et);
   92 static void     mv_setup_timers(void);
   93 
   94 static struct timecounter mv_timer_timecounter = {
   95         .tc_get_timecount = mv_timer_get_timecount,
   96         .tc_name = "CPUTimer1",
   97         .tc_frequency = 0,      /* This is assigned on the fly in the init sequence */
   98         .tc_counter_mask = ~0u,
   99         .tc_quality = 1000,
  100 };
  101 
  102 static int
  103 mv_timer_probe(device_t dev)
  104 {
  105 
  106         if (!ofw_bus_is_compatible(dev, "mrvl,timer"))
  107                 return (ENXIO);
  108 
  109         device_set_desc(dev, "Marvell CPU Timer");
  110         return (0);
  111 }
  112 
  113 static int
  114 mv_timer_attach(device_t dev)
  115 {
  116         int     error;
  117         void    *ihl;
  118         struct  mv_timer_softc *sc;
  119         uint32_t irq_cause, irq_mask;
  120 
  121         if (timer_softc != NULL)
  122                 return (ENXIO);
  123 
  124         sc = (struct mv_timer_softc *)device_get_softc(dev);
  125         timer_softc = sc;
  126 
  127         error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res);
  128         if (error) {
  129                 device_printf(dev, "could not allocate resources\n");
  130                 return (ENXIO);
  131         }
  132 
  133         sc->timer_bst = rman_get_bustag(sc->timer_res[0]);
  134         sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]);
  135 
  136         mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF);
  137         mv_watchdog_disable();
  138         EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
  139 
  140         if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
  141             mv_hardclock, NULL, sc, &ihl) != 0) {
  142                 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
  143                 device_printf(dev, "Could not setup interrupt.\n");
  144                 return (ENXIO);
  145         }
  146 
  147         mv_setup_timers();
  148         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
  149         irq_cause &= ~(IRQ_TIMER0);
  150         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
  151         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
  152         irq_mask |= IRQ_TIMER0_MASK;
  153         irq_mask &= ~IRQ_TIMER1_MASK;
  154         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
  155 
  156         sc->et.et_name = "CPUTimer0";
  157         sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
  158         sc->et.et_quality = 1000;
  159         sc->et.et_frequency = get_tclk();
  160         sc->et.et_min_period.sec = 0;
  161         sc->et.et_min_period.frac =
  162             ((0x00000002LLU << 32) / sc->et.et_frequency) << 32;
  163         sc->et.et_max_period.sec = 0xfffffff0U / sc->et.et_frequency;
  164         sc->et.et_max_period.frac =
  165             ((0xfffffffeLLU << 32) / sc->et.et_frequency) << 32;
  166         sc->et.et_start = mv_timer_start;
  167         sc->et.et_stop = mv_timer_stop;
  168         sc->et.et_priv = sc;
  169         et_register(&sc->et);
  170         mv_timer_timecounter.tc_frequency = get_tclk();
  171         tc_init(&mv_timer_timecounter);
  172 
  173         return (0);
  174 }
  175 
  176 static int
  177 mv_hardclock(void *arg)
  178 {
  179         struct  mv_timer_softc *sc;
  180         uint32_t irq_cause;
  181 
  182         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
  183         irq_cause &= ~(IRQ_TIMER0);
  184         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
  185 
  186         sc = (struct mv_timer_softc *)arg;
  187         if (sc->et.et_active)
  188                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
  189 
  190         return (FILTER_HANDLED);
  191 }
  192 
  193 static device_method_t mv_timer_methods[] = {
  194         DEVMETHOD(device_probe, mv_timer_probe),
  195         DEVMETHOD(device_attach, mv_timer_attach),
  196 
  197         { 0, 0 }
  198 };
  199 
  200 static driver_t mv_timer_driver = {
  201         "timer",
  202         mv_timer_methods,
  203         sizeof(struct mv_timer_softc),
  204 };
  205 
  206 static devclass_t mv_timer_devclass;
  207 
  208 DRIVER_MODULE(timer, simplebus, mv_timer_driver, mv_timer_devclass, 0, 0);
  209 
  210 static unsigned
  211 mv_timer_get_timecount(struct timecounter *tc)
  212 {
  213 
  214         return (INITIAL_TIMECOUNTER - mv_get_timer(1));
  215 }
  216 
  217 void
  218 cpu_initclocks(void)
  219 {
  220 
  221         cpu_initclocks_bsp();
  222 }
  223 
  224 void
  225 DELAY(int usec)
  226 {
  227         uint32_t        val, val_temp;
  228         int32_t         nticks;
  229 
  230         if (!timers_initialized) {
  231                 for (; usec > 0; usec--)
  232                         for (val = 100; val > 0; val--)
  233                                 __asm __volatile("nop" ::: "memory");
  234                 return;
  235         }
  236 
  237         val = mv_get_timer(1);
  238         nticks = ((get_tclk() / 1000000 + 1) * usec);
  239 
  240         while (nticks > 0) {
  241                 val_temp = mv_get_timer(1);
  242                 if (val > val_temp)
  243                         nticks -= (val - val_temp);
  244                 else
  245                         nticks -= (val + (INITIAL_TIMECOUNTER - val_temp));
  246 
  247                 val = val_temp;
  248         }
  249 }
  250 
  251 static uint32_t
  252 mv_get_timer_control(void)
  253 {
  254 
  255         return (bus_space_read_4(timer_softc->timer_bst,
  256             timer_softc->timer_bsh, CPU_TIMER_CONTROL));
  257 }
  258 
  259 static void
  260 mv_set_timer_control(uint32_t val)
  261 {
  262 
  263         bus_space_write_4(timer_softc->timer_bst,
  264             timer_softc->timer_bsh, CPU_TIMER_CONTROL, val);
  265 }
  266 
  267 static uint32_t
  268 mv_get_timer(uint32_t timer)
  269 {
  270 
  271         return (bus_space_read_4(timer_softc->timer_bst,
  272             timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8));
  273 }
  274 
  275 static void
  276 mv_set_timer(uint32_t timer, uint32_t val)
  277 {
  278 
  279         bus_space_write_4(timer_softc->timer_bst,
  280             timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val);
  281 }
  282 
  283 static void
  284 mv_set_timer_rel(uint32_t timer, uint32_t val)
  285 {
  286 
  287         bus_space_write_4(timer_softc->timer_bst,
  288             timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
  289 }
  290 
  291 static void
  292 mv_watchdog_enable(void)
  293 {
  294         uint32_t val;
  295         uint32_t irq_cause, irq_mask;
  296 
  297         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
  298         irq_cause &= ~(IRQ_TIMER_WD);
  299         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
  300 
  301         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
  302         irq_mask |= IRQ_TIMER_WD_MASK;
  303         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
  304 
  305         val = read_cpu_ctrl(RSTOUTn_MASK);
  306         val |= WD_RST_OUT_EN;
  307         write_cpu_ctrl(RSTOUTn_MASK, val);
  308 
  309         val = mv_get_timer_control();
  310         val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO;
  311         mv_set_timer_control(val);
  312 }
  313 
  314 static void
  315 mv_watchdog_disable(void)
  316 {
  317         uint32_t val;
  318         uint32_t irq_cause, irq_mask;
  319 
  320         val = mv_get_timer_control();
  321         val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
  322         mv_set_timer_control(val);
  323 
  324         val = read_cpu_ctrl(RSTOUTn_MASK);
  325         val &= ~WD_RST_OUT_EN;
  326         write_cpu_ctrl(RSTOUTn_MASK, val);
  327 
  328         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
  329         irq_mask &= ~(IRQ_TIMER_WD_MASK);
  330         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
  331 
  332         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
  333         irq_cause &= ~(IRQ_TIMER_WD);
  334         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
  335 }
  336 
  337 
  338 /*
  339  * Watchdog event handler.
  340  */
  341 static void
  342 mv_watchdog_event(void *arg, unsigned int cmd, int *error)
  343 {
  344         uint64_t ns;
  345         uint64_t ticks;
  346 
  347         mtx_lock(&timer_softc->timer_mtx);
  348         if (cmd == 0)
  349                 mv_watchdog_disable();
  350         else {
  351                 /*
  352                  * Watchdog timeout is in nanosecs, calculation according to
  353                  * watchdog(9)
  354                  */
  355                 ns = (uint64_t)1 << (cmd & WD_INTERVAL);
  356                 ticks = (uint64_t)(ns * get_tclk()) / 1000000000;
  357                 if (ticks > MAX_WATCHDOG_TICKS)
  358                         mv_watchdog_disable();
  359                 else {
  360                         /* Timer 2 is the watchdog */
  361                         mv_set_timer(2, ticks);
  362                         mv_watchdog_enable();
  363                         *error = 0;
  364                 }
  365         }
  366         mtx_unlock(&timer_softc->timer_mtx);
  367 }
  368 
  369 static int
  370 mv_timer_start(struct eventtimer *et,
  371     struct bintime *first, struct bintime *period)
  372 {
  373         struct  mv_timer_softc *sc;
  374         uint32_t val, val1;
  375 
  376         /* Calculate dividers. */
  377         sc = (struct mv_timer_softc *)et->et_priv;
  378         if (period != NULL) {
  379                 val = (sc->et.et_frequency * (period->frac >> 32)) >> 32;
  380                 if (period->sec != 0)
  381                         val += sc->et.et_frequency * period->sec;
  382         } else
  383                 val = 0;
  384         if (first != NULL) {
  385                 val1 = (sc->et.et_frequency * (first->frac >> 32)) >> 32;
  386                 if (first->sec != 0)
  387                         val1 += sc->et.et_frequency * first->sec;
  388         } else
  389                 val1 = val;
  390 
  391         /* Apply configuration. */
  392         mv_set_timer_rel(0, val);
  393         mv_set_timer(0, val1);
  394         val = mv_get_timer_control();
  395         val |= CPU_TIMER0_EN;
  396         if (period != NULL)
  397                 val |= CPU_TIMER0_AUTO;
  398         else
  399                 val &= ~CPU_TIMER0_AUTO;
  400         mv_set_timer_control(val);
  401         return (0);
  402 }
  403 
  404 static int
  405 mv_timer_stop(struct eventtimer *et)
  406 {
  407         uint32_t val;
  408 
  409         val = mv_get_timer_control();
  410         val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
  411         mv_set_timer_control(val);
  412         return (0);
  413 }
  414 
  415 static void
  416 mv_setup_timers(void)
  417 {
  418         uint32_t val;
  419 
  420         mv_set_timer_rel(1, INITIAL_TIMECOUNTER);
  421         mv_set_timer(1, INITIAL_TIMECOUNTER);
  422         val = mv_get_timer_control();
  423         val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
  424         val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
  425         mv_set_timer_control(val);
  426         timers_initialized = 1;
  427 }

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