Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/nvidia/drm2/tegra_dc_reg.h
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1 /*- 2 * Copyright 1992-2015 Michal Meloun 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 #ifndef _TEGRA_DC_REG_H_ 29 #define _TEGRA_DC_REG_H_ 30 31 /* 32 * !!! WARNING !!! 33 * Tegra manual uses registers index (and not register addreses). 34 * We follow the TRM notation and index is converted to offset in 35 * WR4 / RD4 macros 36 */ 37 38 /* --------------------------- DC CMD -------------------------------------- */ 39 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000 40 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001 41 #define SYNCPT_CNTRL_NO_STALL (1 << 8) 42 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0) 43 44 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002 45 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008 46 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009 47 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a 48 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010 49 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011 50 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012 51 #define DC_CMD_WIN_C_INCR_SYNCPT 0x018 52 #define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019 53 #define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a 54 #define DC_CMD_CONT_SYNCPT_VSYNC 0x028 55 #define SYNCPT_VSYNC_ENABLE (1 << 8) 56 57 #define DC_CMD_CTXSW 0x030 58 #define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031 59 #define DC_CMD_DISPLAY_COMMAND 0x032 60 #define DISPLAY_CTRL_MODE(x) ((x) << 5) 61 #define CTRL_MODE_STOP 0 62 #define CTRL_MODE_C_DISPLAY 1 63 #define CTRL_MODE_NC_DISPLAY 2 64 65 #define DC_CMD_SIGNAL_RAISE 0x033 66 #define DC_CMD_DISPLAY_POWER_CONTROL 0x036 67 #define PM1_ENABLE (1 << 18) 68 #define PM0_ENABLE (1 << 16) 69 #define PW4_ENABLE (1 << 8) 70 #define PW3_ENABLE (1 << 6) 71 #define PW2_ENABLE (1 << 4) 72 #define PW1_ENABLE (1 << 2) 73 #define PW0_ENABLE (1 << 0) 74 75 #define DC_CMD_INT_STATUS 0x037 76 #define DC_CMD_INT_MASK 0x038 77 #define DC_CMD_INT_ENABLE 0x039 78 #define DC_CMD_INT_TYPE 0x03a 79 #define DC_CMD_INT_POLARITY 0x03b 80 #define WIN_T_UF_INT (1 << 25) 81 #define WIN_D_UF_INT (1 << 24) 82 #define HC_UF_INT (1 << 23) 83 #define CMU_LUT_CONFLICT_INT (1 << 22) 84 #define WIN_C_OF_INT (1 << 16) 85 #define WIN_B_OF_INT (1 << 15) 86 #define WIN_A_OF_INT (1 << 14) 87 #define SSF_INT (1 << 13) 88 #define MSF_INT (1 << 12) 89 #define WIN_C_UF_INT (1 << 10) 90 #define WIN_B_UF_INT (1 << 9) 91 #define WIN_A_UF_INT (1 << 8) 92 #define SPI_BUSY_INT (1 << 6) 93 #define V_PULSE2_INT (1 << 5) 94 #define V_PULSE3_INT (1 << 4) 95 #define HBLANK_INT (1 << 3) 96 #define VBLANK_INT (1 << 2) 97 #define FRAME_END_INT (1 << 1) 98 99 #define DC_CMD_STATE_ACCESS 0x040 100 #define WRITE_MUX (1 << 2) 101 #define READ_MUX (1 << 0) 102 103 #define DC_CMD_STATE_CONTROL 0x041 104 #define NC_HOST_TRIG (1 << 24) 105 #define CURSOR_UPDATE (1 << 15) 106 #define WIN_C_UPDATE (1 << 11) 107 #define WIN_B_UPDATE (1 << 10) 108 #define WIN_A_UPDATE (1 << 9) 109 #define WIN_UPDATE(x) (1 << (9 + (x))) 110 #define GENERAL_UPDATE (1 << 8) 111 #define CURSOR_ACT_REQ (1 << 7) 112 #define WIN_D_ACT_REQ (1 << 4) 113 #define WIN_C_ACT_REQ (1 << 3) 114 #define WIN_B_ACT_REQ (1 << 2) 115 #define WIN_A_ACT_REQ (1 << 1) 116 #define WIN_ACT_REQ(x) (1 << (1 + (x))) 117 #define GENERAL_ACT_REQ (1 << 0) 118 119 #define DC_CMD_DISPLAY_WINDOW_HEADER 0x042 120 #define WINDOW_D_SELECT (1 << 7) 121 #define WINDOW_C_SELECT (1 << 6) 122 #define WINDOW_B_SELECT (1 << 5) 123 #define WINDOW_A_SELECT (1 << 4) 124 #define WINDOW_SELECT(x) (1 << (4 + (x))) 125 126 #define DC_CMD_REG_ACT_CONTROL 0x043 127 #define DC_CMD_WIN_D_INCR_SYNCPT 0x04c 128 #define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL 0x04d 129 #define DC_CMD_WIN_D_INCR_SYNCPT_ERROR 0x04e 130 131 /* ---------------------------- DC COM ------------------------------------- */ 132 133 /* --------------------------- DC DISP ------------------------------------- */ 134 135 #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 136 #define M1_ENABLE (1 << 26) 137 #define M0_ENABLE (1 << 24) 138 #define V_PULSE2_ENABLE (1 << 18) 139 #define V_PULSE1_ENABLE (1 << 16) 140 #define V_PULSE0_ENABLE (1 << 14) 141 #define H_PULSE2_ENABLE (1 << 12) 142 #define H_PULSE1_ENABLE (1 << 10) 143 #define H_PULSE0_ENABLE (1 << 8) 144 145 #define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401 146 147 #define DC_DISP_DISP_WIN_OPTIONS 0x402 148 #define HDMI_ENABLE (1 << 30) 149 #define DSI_ENABLE (1 << 29) 150 #define SOR1_TIMING_CYA (1 << 27) 151 #define SOR1_ENABLE (1 << 26) 152 #define SOR_ENABLE (1 << 25) 153 #define CURSOR_ENABLE (1 << 16) 154 155 #define DC_DISP_DISP_TIMING_OPTIONS 0x405 156 #define VSYNC_H_POSITION(x) (((x) & 0xfff) << 0) 157 158 #define DC_DISP_REF_TO_SYNC 0x406 159 #define DC_DISP_SYNC_WIDTH 0x407 160 #define DC_DISP_BACK_PORCH 0x408 161 #define DC_DISP_DISP_ACTIVE 0x409 162 #define DC_DISP_FRONT_PORCH 0x40a 163 #define DC_DISP_H_PULSE0_CONTROL 0x40b 164 #define DC_DISP_H_PULSE0_POSITION_A 0x40c 165 #define DC_DISP_H_PULSE0_POSITION_B 0x40d 166 #define DC_DISP_H_PULSE0_POSITION_C 0x40e 167 #define DC_DISP_H_PULSE0_POSITION_D 0x40f 168 #define DC_DISP_H_PULSE1_CONTROL 0x410 169 #define DC_DISP_H_PULSE1_POSITION_A 0x411 170 #define DC_DISP_H_PULSE1_POSITION_B 0x412 171 #define DC_DISP_H_PULSE1_POSITION_C 0x413 172 #define DC_DISP_H_PULSE1_POSITION_D 0x414 173 #define DC_DISP_H_PULSE2_CONTROL 0x415 174 #define DC_DISP_H_PULSE2_POSITION_A 0x416 175 #define DC_DISP_H_PULSE2_POSITION_B 0x417 176 #define DC_DISP_H_PULSE2_POSITION_C 0x418 177 #define DC_DISP_H_PULSE2_POSITION_D 0x419 178 #define DC_DISP_V_PULSE0_CONTROL 0x41a 179 #define DC_DISP_V_PULSE0_POSITION_A 0x41b 180 #define DC_DISP_V_PULSE0_POSITION_B 0x41c 181 #define DC_DISP_V_PULSE0_POSITION_C 0x41d 182 #define DC_DISP_V_PULSE1_CONTROL 0x41e 183 #define DC_DISP_V_PULSE1_POSITION_A 0x41f 184 #define DC_DISP_V_PULSE1_POSITION_B 0x420 185 #define DC_DISP_V_PULSE1_POSITION_C 0x421 186 #define DC_DISP_V_PULSE2_CONTROL 0x422 187 #define DC_DISP_V_PULSE2_POSITION_A 0x423 188 #define DC_DISP_V_PULSE3_CONTROL 0x424 189 #define PULSE_CONTROL_LAST(x) (((x) & 0x7f) << 8) 190 #define LAST_START_A 0 191 #define LAST_END_A 1 192 #define LAST_START_B 2 193 #define LAST_END_B 3 194 #define LAST_START_C 4 195 #define LAST_END_C 5 196 #define LAST_START_D 6 197 #define LAST_END_D 7 198 #define PULSE_CONTROL_QUAL(x) (((x) & 0x3) << 8) 199 #define QUAL_ALWAYS 0 200 #define QUAL_VACTIVE 2 201 #define QUAL_VACTIVE1 3 202 #define PULSE_POLARITY (1 << 4) 203 #define PULSE_MODE (1 << 3) 204 205 #define DC_DISP_V_PULSE3_POSITION_A 0x425 206 #define PULSE_END(x) (((x) & 0xfff) << 16) 207 #define PULSE_START(x) (((x) & 0xfff) << 0) 208 209 #define DC_DISP_DISP_CLOCK_CONTROL 0x42e 210 #define PIXEL_CLK_DIVIDER(x) (((x) & 0xf) << 8) 211 #define PCD1 0 212 #define PCD1H 1 213 #define PCD2 2 214 #define PCD3 3 215 #define PCD4 4 216 #define PCD6 5 217 #define PCD8 6 218 #define PCD9 7 219 #define PCD12 8 220 #define PCD16 9 221 #define PCD18 10 222 #define PCD24 11 223 #define PCD13 12 224 #define SHIFT_CLK_DIVIDER(x) ((x) & 0xff) 225 226 #define DC_DISP_DISP_INTERFACE_CONTROL 0x42f 227 #define DISP_ORDER_BLUE_RED ( 1 << 9) 228 #define DISP_ALIGNMENT_LSB ( 1 << 8) 229 #define DISP_DATA_FORMAT(x) (((x) & 0xf) << 8) 230 #define DF1P1C 0 231 #define DF1P2C24B 1 232 #define DF1P2C18B 2 233 #define DF1P2C16B 3 234 #define DF1S 4 235 #define DF2S 5 236 #define DF3S 6 237 #define DFSPI 7 238 #define DF1P3C24B 8 239 #define DF2P1C18B 9 240 #define DFDUAL1P1C18B 10 241 242 #define DC_DISP_DISP_COLOR_CONTROL 0x430 243 #define NON_BASE_COLOR (1 << 18) 244 #define BLANK_COLOR (1 << 17) 245 #define DISP_COLOR_SWAP (1 << 16) 246 #define ORD_DITHER_ROTATION(x) (((x) & 0x3) << 12) 247 #define DITHER_CONTROL(x) (((x) & 0x3) << 8) 248 #define DITHER_DISABLE 0 249 #define DITHER_ORDERED 2 250 #define DITHER_TEMPORAL 3 251 #define BASE_COLOR_SIZE(x) (((x) & 0xF) << 0) 252 #define SIZE_BASE666 0 253 #define SIZE_BASE111 1 254 #define SIZE_BASE222 2 255 #define SIZE_BASE333 3 256 #define SIZE_BASE444 4 257 #define SIZE_BASE555 5 258 #define SIZE_BASE565 6 259 #define SIZE_BASE332 7 260 #define SIZE_BASE888 8 261 262 #define DC_DISP_CURSOR_START_ADDR 0x43e 263 #define CURSOR_CLIP(x) (((x) & 0x3) << 28) 264 #define CC_DISPLAY 0 265 #define CC_WA 1 266 #define CC_WB 2 267 #define CC_WC 3 268 #define CURSOR_SIZE(x) (((x) & 0x3) << 24) 269 #define C32x32 0 270 #define C64x64 1 271 #define C128x128 2 272 #define C256x256 3 273 #define CURSOR_START_ADDR(x) (((x) >> 10) & 0x3FFFFF) 274 275 #define DC_DISP_CURSOR_POSITION 0x440 276 #define CURSOR_POSITION(h, v) ((((h) & 0x3fff) << 0) | \ 277 (((v) & 0x3fff) << 16)) 278 #define DC_DISP_CURSOR_UNDERFLOW_CTRL 0x4eb 279 #define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1 280 #define CURSOR_MODE_SELECT (1 << 24) 281 #define CURSOR_DST_BLEND_FACTOR_SELECT(x) (((x) & 0x3) << 16) 282 #define DST_BLEND_ZERO 0 283 #define DST_BLEND_K1 1 284 #define DST_NEG_K1_TIMES_SRC 2 285 #define CURSOR_SRC_BLEND_FACTOR_SELECT(x) (((x) & 0x3) << 8) 286 #define SRC_BLEND_K1 0 287 #define SRC_BLEND_K1_TIMES_SRC 1 288 #define CURSOR_ALPHA(x) (((x) & 0xFF) << 0) 289 290 #define DC_DISP_CURSOR_UFLOW_DBG_PIXEL 0x4f3 291 #define CURSOR_UFLOW_CYA (1 << 7) 292 #define CURSOR_UFLOW_CTRL_DBG_MODE (1 << 0) 293 /* --------------------------- DC WIN ------------------------------------- */ 294 295 #define DC_WINC_COLOR_PALETTE 0x500 296 #define DC_WINC_CSC_YOF 0x611 297 #define DC_WINC_CSC_KYRGB 0x612 298 #define DC_WINC_CSC_KUR 0x613 299 #define DC_WINC_CSC_KVR 0x614 300 #define DC_WINC_CSC_KUG 0x615 301 #define DC_WINC_CSC_KVG 0x616 302 #define DC_WINC_CSC_KUB 0x617 303 #define DC_WINC_CSC_KVB 0x618 304 305 #define DC_WINC_WIN_OPTIONS 0x700 306 #define H_FILTER_MODE (1U << 31) 307 #define WIN_ENABLE (1 << 30) 308 #define INTERLACE_ENABLE (1 << 23) 309 #define YUV_RANGE_EXPAND (1 << 22) 310 #define DV_ENABLE (1 << 20) 311 #define CSC_ENABLE (1 << 18) 312 #define CP_ENABLE (1 << 16) 313 #define V_FILTER_UV_ALIGN (1 << 14) 314 #define V_FILTER_OPTIMIZE (1 << 12) 315 #define V_FILTER_ENABLE (1 << 10) 316 #define H_FILTER_ENABLE (1 << 8) 317 #define COLOR_EXPAND (1 << 6) 318 #define SCAN_COLUMN (1 << 4) 319 #define V_DIRECTION (1 << 2) 320 #define H_DIRECTION (1 << 0) 321 322 #define DC_WIN_BYTE_SWAP 0x701 323 #define BYTE_SWAP(x) (((x) & 0x7) << 0) 324 #define NOSWAP 0 325 #define SWAP2 1 326 #define SWAP4 2 327 #define SWAP4HW 3 328 #define SWAP02 4 329 #define SWAPLEFT 5 330 331 #define DC_WIN_COLOR_DEPTH 0x703 332 #define WIN_COLOR_DEPTH_P8 3 333 #define WIN_COLOR_DEPTH_B4G4R4A4 4 334 #define WIN_COLOR_DEPTH_B5G5R5A 5 335 #define WIN_COLOR_DEPTH_B5G6R5 6 336 #define WIN_COLOR_DEPTH_AB5G5R5 7 337 #define WIN_COLOR_DEPTH_B8G8R8A8 12 338 #define WIN_COLOR_DEPTH_R8G8B8A8 13 339 #define WIN_COLOR_DEPTH_YCbCr422 16 340 #define WIN_COLOR_DEPTH_YUV422 17 341 #define WIN_COLOR_DEPTH_YCbCr420P 18 342 #define WIN_COLOR_DEPTH_YUV420P 19 343 #define WIN_COLOR_DEPTH_YCbCr422P 20 344 #define WIN_COLOR_DEPTH_YUV422P 21 345 #define WIN_COLOR_DEPTH_YCbCr422R 22 346 #define WIN_COLOR_DEPTH_YUV422R 23 347 #define WIN_COLOR_DEPTH_YCbCr422RA 24 348 #define WIN_COLOR_DEPTH_YUV422RA 25 349 350 #define DC_WIN_POSITION 0x704 351 #define WIN_POSITION(h, v) ((((h) & 0x1fff) << 0) | \ 352 (((v) & 0x1fff) << 16)) 353 354 #define DC_WIN_SIZE 0x705 355 #define WIN_SIZE(h, v) ((((h) & 0x1fff) << 0) | \ 356 (((v) & 0x1fff) << 16)) 357 358 #define DC_WIN_PRESCALED_SIZE 0x706 359 #define WIN_PRESCALED_SIZE(h, v) ((((h) & 0x7fff) << 0) | \ 360 (((v) & 0x1fff) << 16)) 361 362 #define DC_WIN_H_INITIAL_DDA 0x707 363 #define DC_WIN_V_INITIAL_DDA 0x708 364 #define DC_WIN_DDA_INCREMENT 0x709 365 #define WIN_DDA_INCREMENT(h, v) ((((h) & 0xffff) << 0) | \ 366 (((v) & 0xffff) << 16)) 367 #define DC_WIN_LINE_STRIDE 0x70a 368 369 /* -------------------------- DC WINBUF ------------------------------------ */ 370 371 #define DC_WINBUF_START_ADDR 0x800 372 #define DC_WINBUF_START_ADDR_NS 0x801 373 #define DC_WINBUF_START_ADDR_U 0x802 374 #define DC_WINBUF_START_ADDR_U_NS 0x803 375 #define DC_WINBUF_START_ADDR_V 0x804 376 #define DC_WINBUF_START_ADDR_V_NS 0x805 377 #define DC_WINBUF_ADDR_H_OFFSET 0x806 378 #define DC_WINBUF_ADDR_H_OFFSET_NS 0x807 379 #define DC_WINBUF_ADDR_V_OFFSET 0x808 380 #define DC_WINBUF_ADDR_V_OFFSET_NS 0x809 381 #define DC_WINBUF_UFLOW_STATUS 0x80a 382 #define DC_WINBUF_SURFACE_KIND 0x80b 383 #define SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4) 384 #define SURFACE_KIND_PITCH 0 385 #define SURFACE_KIND_TILED 1 386 #define SURFACE_KIND_BL_16B2 2 387 #define DC_WINBUF_SURFACE_WEIGHT 0x80c 388 #define DC_WINBUF_START_ADDR_HI 0x80d 389 #define DC_WINBUF_START_ADDR_HI_NS 0x80e 390 #define DC_WINBUF_START_ADDR_U_HI 0x80f 391 #define DC_WINBUF_START_ADDR_U_HI_NS 0x810 392 #define DC_WINBUF_START_ADDR_V_HI 0x811 393 #define DC_WINBUF_START_ADDR_V_HI_NS 0x812 394 #define DC_WINBUF_UFLOW_CTRL 0x824 395 #define UFLOW_CTR_ENABLE (1 << 0) 396 #define DC_WINBUF_UFLOW_DBG_PIXEL 0x825 397 398 #endif /* _TEGRA_DC_REG_H_ */
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