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sys/arm/nvidia/tegra124/tegra124_clk_per.c
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1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/lock.h> 34 #include <sys/mutex.h> 35 #include <sys/rman.h> 36 37 #include <machine/bus.h> 38 39 #include <dev/extres/clk/clk.h> 40 41 #include <dt-bindings/clock/tegra124-car.h> 42 #include "tegra124_car.h" 43 44 /* The TEGRA124_CLK_XUSB_GATE is missing in current 45 * DT bindings, define it localy 46 */ 47 #ifdef TEGRA124_CLK_XUSB_GATE 48 #error "TEGRA124_CLK_XUSB_GATE is now defined, revisit XUSB code!" 49 #else 50 #define TEGRA124_CLK_XUSB_GATE 143 51 #endif 52 53 /* Bits in base register. */ 54 #define PERLCK_AMUX_MASK 0x0F 55 #define PERLCK_AMUX_SHIFT 16 56 #define PERLCK_AMUX_DIS (1 << 20) 57 #define PERLCK_UDIV_DIS (1 << 24) 58 #define PERLCK_ENA_MASK (1 << 28) 59 #define PERLCK_MUX_SHIFT 29 60 #define PERLCK_MUX_MASK 0x07 61 62 struct periph_def { 63 struct clknode_init_def clkdef; 64 uint32_t base_reg; 65 uint32_t div_width; 66 uint32_t div_mask; 67 uint32_t div_f_width; 68 uint32_t div_f_mask; 69 uint32_t flags; 70 }; 71 72 struct pgate_def { 73 struct clknode_init_def clkdef; 74 uint32_t idx; 75 uint32_t flags; 76 }; 77 #define PLIST(x) static const char *x[] 78 79 #define GATE(_id, cname, plist, _idx) \ 80 { \ 81 .clkdef.id = TEGRA124_CLK_##_id, \ 82 .clkdef.name = cname, \ 83 .clkdef.parent_names = (const char *[]){plist}, \ 84 .clkdef.parent_cnt = 1, \ 85 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 86 .idx = _idx, \ 87 .flags = 0, \ 88 } 89 90 /* Sources for multiplexors. */ 91 PLIST(mux_a_N_audio_N_p_N_clkm) = 92 {"pllA_out0", NULL, "audio", NULL, 93 "pllP_out0", NULL, "clk_m"}; 94 PLIST(mux_a_N_audio0_N_p_N_clkm) = 95 {"pllA_out0", NULL, "audio0", NULL, 96 "pllP_out0", NULL, "clk_m"}; 97 PLIST(mux_a_N_audio1_N_p_N_clkm) = 98 {"pllA_out0", NULL, "audio1", NULL, 99 "pllP_out0", NULL, "clk_m"}; 100 PLIST(mux_a_N_audio2_N_p_N_clkm) = 101 {"pllA_out0", NULL, "audio2", NULL, 102 "pllP_out0", NULL, "clk_m"}; 103 PLIST(mux_a_N_audio3_N_p_N_clkm) = 104 {"pllA_out0", NULL, "audio3", NULL, 105 "pllP_out0", NULL, "clk_m"}; 106 PLIST(mux_a_N_audio4_N_p_N_clkm) = 107 {"pllA_out0", NULL, "audio4", NULL, 108 "pllP_out0", NULL, "clk_m"}; 109 PLIST(mux_a_clks_p_clkm_e) = 110 {"pllA_out0", "clk_s", "pllP_out0", 111 "clk_m", "pllE_out0"}; 112 PLIST(mux_a_c2_c_c3_p_N_clkm) = 113 {"pllA_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 114 "pllP_out0", NULL, "clk_m"}; 115 116 PLIST(mux_m_c_p_a_c2_c3) = 117 {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0", 118 "pllC2_out0", "pllC3_out0"}; 119 PLIST(mux_m_c_p_a_c2_c3_clkm) = 120 {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0", 121 "pllC2_out0", "pllC3_out0", "clk_m"}; 122 PLIST(mux_m_c_p_a_c2_c3_clkm_c4) = 123 {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0", 124 "pllC2_out0", "pllC3_out0", "clk_m", "pllC4_out0"}; 125 PLIST(mux_m_c_p_clkm_mud_c2_c3) = 126 {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m", 127 "pllM_UD", "pllC2_out0", "pllC3_out0"}; 128 PLIST(mux_m_c_p_clkm_mud_c2_c3_cud) = 129 {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m", 130 "pllM_UD", "pllC2_out0", "pllC3_out0", "pllC_UD"}; 131 132 PLIST(mux_m_c2_c_c3_p_N_a) = 133 {"pllM_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 134 "pllP_out0", NULL, "pllA_out0"}; 135 PLIST(mux_m_c2_c_c3_p_N_a_c4) = 136 {"pllM_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 137 NULL, "pllA_out0", "pllC4_out0"}; 138 139 PLIST(mux_p_N_c_N_N_N_clkm) = 140 {"pllP_out0", NULL, "pllC_out0", NULL, 141 NULL, NULL, "clk_m"}; 142 PLIST(mux_p_N_c_N_m_N_clkm) = 143 {"pllP_out0", NULL, "pllC_out0", NULL, 144 "pllM_out0", NULL, "clk_m"}; 145 PLIST(mux_p_c_c2_clkm) = 146 {"pllP_out0", "pllC_out0", "pllC2_out0", "clk_m"}; 147 PLIST(mux_p_c2_c_c3_m) = 148 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 149 "pllM_out0"}; 150 PLIST(mux_p_c2_c_c3_m_N_clkm) = 151 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 152 "pllM_out0", NULL, "clk_m"}; 153 PLIST(mux_p_c2_c_c3_m_e_clkm) = 154 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 155 "pllM_out0", "pllE_out0", "clk_m"}; 156 PLIST(mux_p_c2_c_c3_m_a_clkm) = 157 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 158 "pllM_out0", "pllA_out0", "clk_m"}; 159 PLIST(mux_p_c2_c_c3_m_clks_clkm) = 160 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 161 "pllM_out0", "clk_s", "clk_m"}; 162 PLIST(mux_p_c2_c_c3_clks_N_clkm) = 163 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 164 "clk_s", NULL, "clk_m"}; 165 PLIST(mux_p_c2_c_c3_clkm_N_clks) = 166 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 167 "clk_m", NULL, "clk_s"}; 168 PLIST(mux_p_clkm_clks_E) = 169 {"pllP_out0", "clk_m", "clk_s", "pllE_out0"}; 170 PLIST(mux_p_m_d_a_c_d2_clkm) = 171 {"pllP_out0", "pllM_out0", "pllD_out0", "pllA_out0", 172 "pllC_out0", "pllD2_out0", "clk_m"}; 173 174 PLIST(mux_clkm_N_u48_N_p_N_u480) = 175 {"clk_m", NULL, "pllU_48", NULL, 176 "pllP_out0", NULL, "pllU_480"}; 177 PLIST(mux_clkm_p_c2_c_c3_refre) = 178 {"clk_m", "pllP_out0", "pllC2_out0", "pllC_out0", 179 "pllC3_out0", "pllREFE_out"}; 180 PLIST(mux_clkm_refe_clks_u480_c_c2_c3_oscdiv) = 181 {"clk_m", "pllREFE_out", "clk_s", "pllU_480", 182 "pllC_out0", "pllC2_out0", "pllC3_out0", "osc_div_clk"}; 183 184 PLIST(mux_sep_audio) = 185 {"pllA_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 186 "pllP_out0", NULL, "clk_m", NULL, 187 "spdif_in", "i2s0", "i2s1", "i2s2", 188 "i2s4", "pllA_out0", "ext_vimclk"}; 189 190 static uint32_t clk_enable_reg[] = { 191 CLK_OUT_ENB_L, 192 CLK_OUT_ENB_H, 193 CLK_OUT_ENB_U, 194 CLK_OUT_ENB_V, 195 CLK_OUT_ENB_W, 196 CLK_OUT_ENB_X, 197 }; 198 199 static uint32_t clk_reset_reg[] = { 200 RST_DEVICES_L, 201 RST_DEVICES_H, 202 RST_DEVICES_U, 203 RST_DEVICES_V, 204 RST_DEVICES_W, 205 RST_DEVICES_X, 206 }; 207 208 #define L(n) ((0 * 32) + (n)) 209 #define H(n) ((1 * 32) + (n)) 210 #define U(n) ((2 * 32) + (n)) 211 #define V(n) ((3 * 32) + (n)) 212 #define W(n) ((4 * 32) + (n)) 213 #define X(n) ((5 * 32) + (n)) 214 215 static struct pgate_def pgate_def[] = { 216 /* bank L -> 0-31 */ 217 /* GATE(CPU, "cpu", "clk_m", L(0)), */ 218 GATE(ISPB, "ispb", "clk_m", L(3)), 219 GATE(RTC, "rtc", "clk_s", L(4)), 220 GATE(TIMER, "timer", "clk_m", L(5)), 221 GATE(UARTA, "uarta", "pc_uarta" , L(6)), 222 GATE(UARTB, "uartb", "pc_uartb", L(7)), 223 GATE(VFIR, "vfir", "pc_vfir", L(7)), 224 /* GATE(GPIO, "gpio", "clk_m", L(8)), */ 225 GATE(SDMMC2, "sdmmc2", "pc_sdmmc2", L(9)), 226 GATE(SPDIF_OUT, "spdif_out", "pc_spdif_out", L(10)), 227 GATE(SPDIF_IN, "spdif_in", "pc_spdif_in", L(10)), 228 GATE(I2S1, "i2s1", "pc_i2s1", L(11)), 229 GATE(I2C1, "i2c1", "pc_i2c1", L(12)), 230 GATE(SDMMC1, "sdmmc1", "pc_sdmmc1", L(14)), 231 GATE(SDMMC4, "sdmmc4", "pc_sdmmc4", L(15)), 232 GATE(PWM, "pwm", "pc_pwm", L(17)), 233 GATE(I2S2, "i2s2", "pc_i2s2", L(18)), 234 GATE(VI, "vi", "pc_vi", L(20)), 235 GATE(USBD, "usbd", "clk_m", L(22)), 236 GATE(ISP, "isp", "pc_isp", L(23)), 237 GATE(DISP2, "disp2", "pc_disp2", L(26)), 238 GATE(DISP1, "disp1", "pc_disp1", L(27)), 239 GATE(HOST1X, "host1x", "pc_host1x", L(28)), 240 GATE(VCP, "vcp", "clk_m", L(29)), 241 GATE(I2S0, "i2s0", "pc_i2s0", L(30)), 242 /* GATE(CACHE2, "ccache2", "clk_m", L(31)), */ 243 244 /* bank H -> 32-63 */ 245 GATE(MC, "mem", "clk_m", H(0)), 246 /* GATE(AHBDMA, "ahbdma", "clk_m", H(1)), */ 247 GATE(APBDMA, "apbdma", "clk_m", H(2)), 248 GATE(KBC, "kbc", "clk_s", H(4)), 249 /* GATE(STAT_MON, "stat_mon", "clk_s", H(5)), */ 250 /* GATE(PMC, "pmc", "clk_s", H(6)), */ 251 GATE(FUSE, "fuse", "clk_m", H(7)), 252 GATE(KFUSE, "kfuse", "clk_m", H(8)), 253 GATE(SBC1, "spi1", "pc_spi1", H(9)), 254 GATE(NOR, "snor", "pc_snor", H(10)), 255 /* GATE(JTAG2TBC, "jtag2tbc", "clk_m", H(11)), */ 256 GATE(SBC2, "spi2", "pc_spi2", H(12)), 257 GATE(SBC3, "spi3", "pc_spi3", H(14)), 258 GATE(I2C5, "i2c5", "pc_i2c5", H(15)), 259 GATE(DSIA, "dsia", "dsia_mux", H(16)), 260 GATE(MIPI, "hsi", "pc_hsi", H(18)), 261 GATE(HDMI, "hdmi", "pc_hdmi", H(19)), 262 GATE(CSI, "csi", "pllP_out3", H(20)), 263 GATE(I2C2, "i2c2", "pc_i2c2", H(22)), 264 GATE(UARTC, "uartc", "pc_uartc", H(23)), 265 GATE(MIPI_CAL, "mipi_cal", "clk_m", H(24)), 266 GATE(EMC, "emc", "pc_emc_2x", H(25)), 267 GATE(USB2, "usb2", "clk_m", H(26)), 268 GATE(USB3, "usb3", "clk_m", H(27)), 269 GATE(VDE, "vde", "pc_vde", H(29)), 270 GATE(BSEA, "bsea", "clk_m", H(30)), 271 GATE(BSEV, "bsev", "clk_m", H(31)), 272 273 /* bank U -> 64-95 */ 274 GATE(UARTD, "uartd", "pc_uartd", U(1)), 275 GATE(I2C3, "i2c3", "pc_i2c3", U(3)), 276 GATE(SBC4, "spi4", "pc_spi4", U(4)), 277 GATE(SDMMC3, "sdmmc3", "pc_sdmmc3", U(5)), 278 GATE(PCIE, "pcie", "clk_m", U(6)), 279 GATE(OWR, "owr", "pc_owr", U(7)), 280 GATE(AFI, "afi", "clk_m", U(8)), 281 GATE(CSITE, "csite", "pc_csite", U(9)), 282 /* GATE(AVPUCQ, "avpucq", clk_m, U(11)), */ 283 GATE(TRACE, "traceclkin", "pc_traceclkin", U(13)), 284 GATE(SOC_THERM, "soc_therm", "pc_soc_therm", U(14)), 285 GATE(DTV, "dtv", "clk_m", U(15)), 286 GATE(I2CSLOW, "i2c_slow", "pc_i2c_slow", U(17)), 287 GATE(DSIB, "dsib", "dsib_mux", U(18)), 288 GATE(TSEC, "tsec", "pc_tsec", U(19)), 289 /* GATE(IRAMA, "irama", "clk_m", U(20)), */ 290 /* GATE(IRAMB, "iramb", "clk_m", U(21)), */ 291 /* GATE(IRAMC, "iramc", "clk_m", U(22)), */ 292 /* GATE(IRAMD, "iramd", "clk_m", U(23)), */ 293 /* GATE(CRAM2, "cram2", "clk_m", U(24)), */ 294 GATE(XUSB_HOST, "xusb_core_host", "pc_xusb_core_host", U(25)), 295 /* GATE(M_DOUBLER, "m_doubler", "clk_m", U(26)), */ 296 GATE(MSENC, "msenc", "pc_msenc", U(27)), 297 GATE(CSUS, "sus_out", "clk_m", U(28)), 298 /* GATE(DEVD2_OUT, "devd2_out", "clk_m", U(29)), */ 299 /* GATE(DEVD1_OUT, "devd1_out", "clk_m", U(30)), */ 300 GATE(XUSB_DEV, "xusb_core_dev", "pc_xusb_core_dev", U(31)), 301 302 /* bank V -> 96-127 */ 303 /* GATE(CPUG, "cpug", "clk_m", V(0)), */ 304 /* GATE(CPULP, "cpuLP", "clk_m", V(1)), */ 305 GATE(MSELECT, "mselect", "pc_mselect", V(3)), 306 GATE(TSENSOR, "tsensor", "pc_tsensor", V(4)), 307 GATE(I2S3, "i2s3", "pc_i2s3", V(5)), 308 GATE(I2S4, "i2s4", "pc_i2s4", V(6)), 309 GATE(I2C4, "i2c4", "pc_i2c4", V(7)), 310 GATE(SBC5, "spi5", "pc_spi5", V(8)), 311 GATE(SBC6, "spi6", "pc_spi6", V(9)), 312 GATE(D_AUDIO, "audio", "pc_audio", V(10)), 313 GATE(APBIF, "apbif", "clk_m", V(11)), 314 GATE(DAM0, "dam0", "pc_dam0", V(12)), 315 GATE(DAM1, "dam1", "pc_dam1", V(13)), 316 GATE(DAM2, "dam2", "pc_dam2", V(14)), 317 GATE(HDA2CODEC_2X, "hda2codec_2x", "pc_hda2codec_2x", V(15)), 318 /* GATE(ATOMICS, "atomics", "clk_m", V(16)), */ 319 /* GATE(SPDIF_DOUBLER, "spdif_doubler", "clk_m", V(22)), */ 320 GATE(ACTMON, "actmon", "pc_actmon", V(23)), 321 GATE(EXTERN1, "extperiph1", "pc_extperiph1", V(24)), 322 GATE(EXTERN2, "extperiph2", "pc_extperiph2", V(25)), 323 GATE(EXTERN3, "extperiph3", "pc_extperiph3", V(26)), 324 GATE(SATA_OOB, "sata_oob", "pc_sata_oob", V(27)), 325 GATE(SATA, "sata", "pc_sata", V(28)), 326 GATE(HDA, "hda", "pc_hda", V(29)), 327 328 /* bank W -> 128-159*/ 329 GATE(HDA2HDMI, "hda2hdmi", "clk_m", W(0)), 330 GATE(SATA_COLD, "sata_cold", "clk_m", W(1)), /* Reset only */ 331 /* GATE(PCIERX0, "pcierx0", "clk_m", W(2)), */ 332 /* GATE(PCIERX1, "pcierx1", "clk_m", W(3)), */ 333 /* GATE(PCIERX2, "pcierx2", "clk_m", W(4)), */ 334 /* GATE(PCIERX3, "pcierx3", "clk_m", W(5)), */ 335 /* GATE(PCIERX4, "pcierx4", "clk_m", W(6)), */ 336 /* GATE(PCIERX5, "pcierx5", "clk_m", W(7)), */ 337 /* GATE(CEC, "cec", "clk_m", W(8)), */ 338 /* GATE(PCIE2_IOBIST, "pcie2_iobist", "clk_m", W(9)), */ 339 /* GATE(EMC_IOBIST, "emc_iobist", "clk_m", W(10)), */ 340 /* GATE(HDMI_IOBIST, "hdmi_iobist", "clk_m", W(11)), */ 341 /* GATE(SATA_IOBIST, "sata_iobist", "clk_m", W(12)), */ 342 /* GATE(MIPI_IOBIST, "mipi_iobist", "clk_m", W(13)), */ 343 GATE(XUSB_GATE, "xusb_gate", "clk_m", W(15)), 344 GATE(CILAB, "cilab", "pc_cilab", W(16)), 345 GATE(CILCD, "cilcd", "pc_cilcd", W(17)), 346 GATE(CILE, "cile", "pc_cile", W(18)), 347 GATE(DSIALP, "dsia_lp", "pc_dsia_lp", W(19)), 348 GATE(DSIBLP, "dsib_lp", "pc_dsib_lp", W(20)), 349 GATE(ENTROPY, "entropy", "pc_entropy", W(21)), 350 GATE(AMX, "amx", "pc_amx", W(25)), 351 GATE(ADX, "adx", "pc_adx", W(26)), 352 GATE(DFLL_REF, "dvfs_ref", "pc_dvfs_ref", W(27)), 353 GATE(DFLL_SOC, "dvfs_soc", "pc_dvfs_soc", W(27)), 354 GATE(XUSB_SS, "xusb_ss", "xusb_ss_mux", W(28)), 355 /* GATE(EMC_LATENCY, "emc_latency", "pc_emc_latency", W(29)), */ 356 357 /* bank X -> 160-191*/ 358 /* GATE(SPARE, "spare", "clk_m", X(0)), */ 359 /* GATE(CAM_MCLK, "CAM_MCLK", "clk_m", X(4)), */ 360 /* GATE(CAM_MCLK2, "CAM_MCLK2", "clk_m", X(5)), */ 361 GATE(I2C6, "i2c6", "pc_i2c6", X(6)), 362 GATE(VIM2_CLK, "vim2_clk", "clk_m", X(11)), 363 /* GATE(EMC_DLL, "emc_dll", "pc_emc_dll", X(14)), */ 364 GATE(HDMI_AUDIO, "hdmi_audio", "pc_hdmi_audio", X(16)), 365 GATE(CLK72MHZ, "clk72mhz", "pc_clk72mhz", X(17)), 366 GATE(VIC03, "vic", "pc_vic", X(18)), 367 GATE(ADX1, "adx1", "pc_adx1", X(20)), 368 GATE(DPAUX, "dpaux", "clk_m", X(21)), 369 GATE(SOR0_LVDS, "sor0", "pc_sor0", X(22)), 370 GATE(GPU, "gpu", "osc_div_clk", X(24)), 371 GATE(AMX1, "amx1", "pc_amx1", X(26)), 372 }; 373 374 /* Peripheral clock clock */ 375 #define DCF_HAVE_MUX 0x0100 /* Block with multipexor */ 376 #define DCF_HAVE_ENA 0x0200 /* Block with enable bit */ 377 #define DCF_HAVE_DIV 0x0400 /* Block with divider */ 378 379 /* Mark block with additional bits / functionality. */ 380 #define DCF_IS_MASK 0x00FF 381 #define DCF_IS_UART 0x0001 382 #define DCF_IS_VI 0x0002 383 #define DCF_IS_HOST1X 0x0003 384 #define DCF_IS_XUSB_SS 0x0004 385 #define DCF_IS_EMC_DLL 0x0005 386 #define DCF_IS_SATA 0x0006 387 #define DCF_IS_VIC 0x0007 388 #define DCF_IS_AUDIO 0x0008 389 #define DCF_IS_SOR0 0x0009 390 #define DCF_IS_EMC 0x000A 391 392 /* Basic pheripheral clock */ 393 #define PER_CLK(_id, cn, pl, r, diw, fiw, f) \ 394 { \ 395 .clkdef.id = _id, \ 396 .clkdef.name = cn, \ 397 .clkdef.parent_names = pl, \ 398 .clkdef.parent_cnt = nitems(pl), \ 399 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 400 .base_reg = r, \ 401 .div_width = diw, \ 402 .div_f_width = fiw, \ 403 .flags = f, \ 404 } 405 406 /* Mux with fractional 8.1 divider. */ 407 #define CLK_8_1(id, cn, pl, r, f) \ 408 PER_CLK(id, cn, pl, r, 8, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) 409 410 /* Mux with fractional 16.1 divider. */ 411 #define CLK16_1(id, cn, pl, r, f) \ 412 PER_CLK(id, cn, pl, r, 16, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) 413 /* Mux with integer 16bits divider. */ 414 #define CLK16_0(id, cn, pl, r, f) \ 415 PER_CLK(id, cn, pl, r, 16, 0, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) 416 /* Mux wihout divider. */ 417 #define CLK_0_0(id, cn, pl, r, f) \ 418 PER_CLK(id, cn, pl, r, 0, 0, (f) | DCF_HAVE_MUX) 419 420 static struct periph_def periph_def[] = { 421 CLK_8_1(0, "pc_i2s1", mux_a_N_audio1_N_p_N_clkm, CLK_SOURCE_I2S1, DCF_HAVE_ENA), 422 CLK_8_1(0, "pc_i2s2", mux_a_N_audio2_N_p_N_clkm, CLK_SOURCE_I2S2, DCF_HAVE_ENA), 423 CLK_8_1(0, "pc_spdif_out", mux_a_N_audio_N_p_N_clkm, CLK_SOURCE_SPDIF_OUT, 0), 424 CLK_8_1(0, "pc_spdif_in", mux_p_c2_c_c3_m, CLK_SOURCE_SPDIF_IN, 0), 425 CLK_8_1(0, "pc_pwm", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_PWM, 0), 426 CLK_8_1(0, "pc_spi2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI2, 0), 427 CLK_8_1(0, "pc_spi3", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI3, 0), 428 CLK16_0(0, "pc_i2c5", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C5, 0), 429 CLK16_0(0, "pc_i2c1", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C1, 0), 430 CLK_8_1(0, "pc_spi1", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI1, 0), 431 CLK_0_0(0, "pc_disp1", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_DISP1, 0), 432 CLK_0_0(0, "pc_disp2", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_DISP2, 0), 433 CLK_8_1(0, "pc_isp", mux_m_c_p_a_c2_c3_clkm_c4, CLK_SOURCE_ISP, 0), 434 CLK_8_1(0, "pc_vi", mux_m_c2_c_c3_p_N_a_c4, CLK_SOURCE_VI, DCF_IS_VI), 435 CLK_8_1(0, "pc_sdmmc1", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC1, 0), 436 CLK_8_1(0, "pc_sdmmc2", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC2, 0), 437 CLK_8_1(0, "pc_sdmmc4", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC4, 0), 438 CLK_8_1(0, "pc_vfir", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_VFIR, 0), 439 CLK_8_1(0, "pc_hsi", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HSI, 0), 440 CLK16_1(0, "pc_uarta", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTA, DCF_IS_UART), 441 CLK16_1(0, "pc_uartb", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTB, DCF_IS_UART), 442 CLK_8_1(0, "pc_host1x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HOST1X, DCF_IS_HOST1X), 443 CLK_8_1(0, "pc_hdmi", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_HDMI, 0), 444 CLK16_0(0, "pc_i2c2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C2, 0), 445 CLK_8_1(0, "pc_emc_2x", mux_m_c_p_clkm_mud_c2_c3_cud, CLK_SOURCE_EMC, DCF_IS_EMC), 446 CLK16_1(0, "pc_uartc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTC, DCF_IS_UART), 447 CLK_8_1(0, "pc_vi_sensor", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR, 0), 448 CLK_8_1(0, "pc_spi4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI4, 0), 449 CLK16_0(0, "pc_i2c3", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C3, 0), 450 CLK_8_1(0, "pc_sdmmc3", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC3, 0), 451 CLK16_1(0, "pc_uartd", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTD, DCF_IS_UART), 452 CLK_8_1(0, "pc_vde", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_VDE, 0), 453 CLK_8_1(0, "pc_owr", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_OWR, 0), 454 CLK_8_1(0, "pc_snor", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_NOR, 0), 455 CLK_8_1(0, "pc_csite", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_CSITE, 0), 456 CLK_8_1(0, "pc_i2s0", mux_a_N_audio0_N_p_N_clkm, CLK_SOURCE_I2S0, 0), 457 /* DTV xxx */ 458 CLK_8_1(0, "pc_msenc", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_MSENC, 0), 459 CLK_8_1(0, "pc_tsec", mux_p_c2_c_c3_m_a_clkm, CLK_SOURCE_TSEC, 0), 460 /* SPARE2 */ 461 462 CLK_8_1(0, "pc_mselect", mux_p_c2_c_c3_m_clks_clkm, CLK_SOURCE_MSELECT, 0), 463 CLK_8_1(0, "pc_tsensor", mux_p_c2_c_c3_clkm_N_clks, CLK_SOURCE_TSENSOR, 0), 464 CLK_8_1(0, "pc_i2s3", mux_a_N_audio3_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA), 465 CLK_8_1(0, "pc_i2s4", mux_a_N_audio4_N_p_N_clkm, CLK_SOURCE_I2S4, DCF_HAVE_ENA), 466 CLK16_0(0, "pc_i2c4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C4, 0), 467 CLK_8_1(0, "pc_spi5", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI5, 0), 468 CLK_8_1(0, "pc_spi6", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI6, 0), 469 CLK_8_1(0, "pc_audio", mux_sep_audio, CLK_SOURCE_AUDIO, DCF_IS_AUDIO), 470 CLK_8_1(0, "pc_dam0", mux_sep_audio, CLK_SOURCE_DAM0, DCF_IS_AUDIO), 471 CLK_8_1(0, "pc_dam1", mux_sep_audio, CLK_SOURCE_DAM1, DCF_IS_AUDIO), 472 CLK_8_1(0, "pc_dam2", mux_sep_audio, CLK_SOURCE_DAM2, DCF_IS_AUDIO), 473 CLK_8_1(0, "pc_hda2codec_2x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA2CODEC_2X, 0), 474 CLK_8_1(0, "pc_actmon", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_ACTMON, 0), 475 CLK_8_1(0, "pc_extperiph1", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH1, 0), 476 CLK_8_1(0, "pc_extperiph2", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH2, 0), 477 CLK_8_1(0, "pc_extperiph3", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH3, 0), 478 CLK_8_1(0, "pc_i2c_slow", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_I2C_SLOW, 0), 479 /* SYS */ 480 CLK_8_1(0, "pc_sor0", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_SOR0, DCF_IS_SOR0), 481 CLK_8_1(0, "pc_sata_oob", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA_OOB, 0), 482 CLK_8_1(0, "pc_sata", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA, DCF_IS_SATA), 483 CLK_8_1(0, "pc_hda", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA, 0), 484 CLK_8_1(TEGRA124_CLK_XUSB_HOST_SRC, 485 "pc_xusb_core_host", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_HOST, 0), 486 CLK_8_1(TEGRA124_CLK_XUSB_FALCON_SRC, 487 "pc_xusb_falcon", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_FALCON, 0), 488 CLK_8_1(TEGRA124_CLK_XUSB_FS_SRC, 489 "pc_xusb_fs", mux_clkm_N_u48_N_p_N_u480, CLK_SOURCE_XUSB_FS, 0), 490 CLK_8_1(TEGRA124_CLK_XUSB_DEV_SRC, 491 "pc_xusb_core_dev", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_DEV, 0), 492 CLK_8_1(TEGRA124_CLK_XUSB_SS_SRC, 493 "pc_xusb_ss", mux_clkm_refe_clks_u480_c_c2_c3_oscdiv, CLK_SOURCE_XUSB_SS, DCF_IS_XUSB_SS), 494 CLK_8_1(0, "pc_cilab", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILAB, 0), 495 CLK_8_1(0, "pc_cilcd", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILCD, 0), 496 CLK_8_1(0, "pc_cile", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILE, 0), 497 CLK_8_1(0, "pc_dsia_lp", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_DSIA_LP, 0), 498 CLK_8_1(0, "pc_dsib_lp", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_DSIB_LP, 0), 499 CLK_8_1(0, "pc_entropy", mux_p_clkm_clks_E, CLK_SOURCE_ENTROPY, 0), 500 CLK_8_1(0, "pc_dvfs_ref", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_REF, DCF_HAVE_ENA), 501 CLK_8_1(0, "pc_dvfs_soc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_SOC, DCF_HAVE_ENA), 502 CLK_8_1(0, "pc_traceclkin", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_TRACECLKIN, 0), 503 CLK_8_1(0, "pc_adx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX, DCF_HAVE_ENA), 504 CLK_8_1(0, "pc_amx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX, DCF_HAVE_ENA), 505 CLK_8_1(0, "pc_emc_latency", mux_m_c_p_clkm_mud_c2_c3, CLK_SOURCE_EMC_LATENCY, 0), 506 CLK_8_1(0, "pc_soc_therm", mux_m_c_p_a_c2_c3, CLK_SOURCE_SOC_THERM, 0), 507 CLK_8_1(0, "pc_vi_sensor2", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR2, 0), 508 CLK16_0(0, "pc_i2c6", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C6, 0), 509 CLK_8_1(0, "pc_emc_dll", mux_m_c_p_clkm_mud_c2_c3, CLK_SOURCE_EMC_DLL, DCF_IS_EMC_DLL), 510 CLK_8_1(0, "pc_hdmi_audio", mux_p_c_c2_clkm, CLK_SOURCE_HDMI_AUDIO, 0), 511 CLK_8_1(0, "pc_clk72mhz", mux_p_c_c2_clkm, CLK_SOURCE_CLK72MHZ, 0), 512 CLK_8_1(0, "pc_adx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX1, DCF_HAVE_ENA), 513 CLK_8_1(0, "pc_amx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX1, DCF_HAVE_ENA), 514 CLK_8_1(0, "pc_vic", mux_m_c_p_a_c2_c3_clkm, CLK_SOURCE_VIC, DCF_IS_VIC), 515 }; 516 517 static int periph_init(struct clknode *clk, device_t dev); 518 static int periph_recalc(struct clknode *clk, uint64_t *freq); 519 static int periph_set_freq(struct clknode *clk, uint64_t fin, 520 uint64_t *fout, int flags, int *stop); 521 static int periph_set_mux(struct clknode *clk, int idx); 522 523 struct periph_sc { 524 device_t clkdev; 525 uint32_t base_reg; 526 uint32_t div_shift; 527 uint32_t div_width; 528 uint32_t div_mask; 529 uint32_t div_f_width; 530 uint32_t div_f_mask; 531 uint32_t flags; 532 533 uint32_t divider; 534 int mux; 535 }; 536 537 static clknode_method_t periph_methods[] = { 538 /* Device interface */ 539 CLKNODEMETHOD(clknode_init, periph_init), 540 CLKNODEMETHOD(clknode_recalc_freq, periph_recalc), 541 CLKNODEMETHOD(clknode_set_freq, periph_set_freq), 542 CLKNODEMETHOD(clknode_set_mux, periph_set_mux), 543 CLKNODEMETHOD_END 544 }; 545 DEFINE_CLASS_1(tegra124_periph, tegra124_periph_class, periph_methods, 546 sizeof(struct periph_sc), clknode_class); 547 548 static int 549 periph_init(struct clknode *clk, device_t dev) 550 { 551 struct periph_sc *sc; 552 uint32_t reg; 553 sc = clknode_get_softc(clk); 554 555 DEVICE_LOCK(sc); 556 if (sc->flags & DCF_HAVE_ENA) 557 MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK); 558 559 RD4(sc, sc->base_reg, ®); 560 DEVICE_UNLOCK(sc); 561 562 /* Stnadard mux. */ 563 if (sc->flags & DCF_HAVE_MUX) 564 sc->mux = (reg >> PERLCK_MUX_SHIFT) & PERLCK_MUX_MASK; 565 else 566 sc->mux = 0; 567 if (sc->flags & DCF_HAVE_DIV) 568 sc->divider = (reg & sc->div_mask) + 2; 569 else 570 sc->divider = 1; 571 if ((sc->flags & DCF_IS_MASK) == DCF_IS_UART) { 572 if (!(reg & PERLCK_UDIV_DIS)) 573 sc->divider = 2; 574 } 575 576 /* AUDIO MUX */ 577 if ((sc->flags & DCF_IS_MASK) == DCF_IS_AUDIO) { 578 if (!(reg & PERLCK_AMUX_DIS) && (sc->mux == 7)) { 579 sc->mux = 8 + 580 ((reg >> PERLCK_AMUX_SHIFT) & PERLCK_MUX_MASK); 581 } 582 } 583 clknode_init_parent_idx(clk, sc->mux); 584 return(0); 585 } 586 587 static int 588 periph_set_mux(struct clknode *clk, int idx) 589 { 590 struct periph_sc *sc; 591 uint32_t reg; 592 593 sc = clknode_get_softc(clk); 594 if (!(sc->flags & DCF_HAVE_MUX)) 595 return (ENXIO); 596 597 sc->mux = idx; 598 DEVICE_LOCK(sc); 599 RD4(sc, sc->base_reg, ®); 600 reg &= ~(PERLCK_MUX_MASK << PERLCK_MUX_SHIFT); 601 if ((sc->flags & DCF_IS_MASK) == DCF_IS_AUDIO) { 602 reg &= ~PERLCK_AMUX_DIS; 603 reg &= ~(PERLCK_MUX_MASK << PERLCK_AMUX_SHIFT); 604 605 if (idx <= 7) { 606 reg |= idx << PERLCK_MUX_SHIFT; 607 } else { 608 reg |= 7 << PERLCK_MUX_SHIFT; 609 reg |= (idx - 8) << PERLCK_AMUX_SHIFT; 610 } 611 } else { 612 reg |= idx << PERLCK_MUX_SHIFT; 613 } 614 WR4(sc, sc->base_reg, reg); 615 DEVICE_UNLOCK(sc); 616 617 return(0); 618 } 619 620 static int 621 periph_recalc(struct clknode *clk, uint64_t *freq) 622 { 623 struct periph_sc *sc; 624 uint32_t reg; 625 626 sc = clknode_get_softc(clk); 627 628 if (sc->flags & DCF_HAVE_DIV) { 629 DEVICE_LOCK(sc); 630 RD4(sc, sc->base_reg, ®); 631 DEVICE_UNLOCK(sc); 632 *freq = (*freq << sc->div_f_width) / sc->divider; 633 } 634 return (0); 635 } 636 637 static int 638 periph_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, 639 int flags, int *stop) 640 { 641 struct periph_sc *sc; 642 uint64_t tmp, divider; 643 644 sc = clknode_get_softc(clk); 645 if (!(sc->flags & DCF_HAVE_DIV)) { 646 *stop = 0; 647 return (0); 648 } 649 650 tmp = fin << sc->div_f_width; 651 divider = tmp / *fout; 652 if ((tmp % *fout) != 0) 653 divider++; 654 655 if (divider < (1 << sc->div_f_width)) 656 divider = 1 << (sc->div_f_width - 1); 657 658 if (flags & CLK_SET_DRYRUN) { 659 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && 660 (*fout != (tmp / divider))) 661 return (ERANGE); 662 } else { 663 DEVICE_LOCK(sc); 664 MD4(sc, sc->base_reg, sc->div_mask, 665 (divider - (1 << sc->div_f_width))); 666 DEVICE_UNLOCK(sc); 667 sc->divider = divider; 668 } 669 *fout = tmp / divider; 670 *stop = 1; 671 return (0); 672 } 673 674 static int 675 periph_register(struct clkdom *clkdom, struct periph_def *clkdef) 676 { 677 struct clknode *clk; 678 struct periph_sc *sc; 679 680 clk = clknode_create(clkdom, &tegra124_periph_class, &clkdef->clkdef); 681 if (clk == NULL) 682 return (1); 683 684 sc = clknode_get_softc(clk); 685 sc->clkdev = clknode_get_device(clk); 686 sc->base_reg = clkdef->base_reg; 687 sc->div_width = clkdef->div_width; 688 sc->div_mask = (1 <<clkdef->div_width) - 1; 689 sc->div_f_width = clkdef->div_f_width; 690 sc->div_f_mask = (1 <<clkdef->div_f_width) - 1; 691 sc->flags = clkdef->flags; 692 693 clknode_register(clkdom, clk); 694 return (0); 695 } 696 697 /* -------------------------------------------------------------------------- */ 698 static int pgate_init(struct clknode *clk, device_t dev); 699 static int pgate_set_gate(struct clknode *clk, bool enable); 700 static int pgate_get_gate(struct clknode *clk, bool *enableD); 701 702 struct pgate_sc { 703 device_t clkdev; 704 uint32_t idx; 705 uint32_t flags; 706 uint32_t enabled; 707 708 }; 709 710 static clknode_method_t pgate_methods[] = { 711 /* Device interface */ 712 CLKNODEMETHOD(clknode_init, pgate_init), 713 CLKNODEMETHOD(clknode_set_gate, pgate_set_gate), 714 CLKNODEMETHOD(clknode_get_gate, pgate_get_gate), 715 CLKNODEMETHOD_END 716 }; 717 DEFINE_CLASS_1(tegra124_pgate, tegra124_pgate_class, pgate_methods, 718 sizeof(struct pgate_sc), clknode_class); 719 720 static uint32_t 721 get_enable_reg(int idx) 722 { 723 KASSERT(idx / 32 < nitems(clk_enable_reg), 724 ("Invalid clock index for enable: %d", idx)); 725 return (clk_enable_reg[idx / 32]); 726 } 727 728 static uint32_t 729 get_reset_reg(int idx) 730 { 731 KASSERT(idx / 32 < nitems(clk_reset_reg), 732 ("Invalid clock index for reset: %d", idx)); 733 return (clk_reset_reg[idx / 32]); 734 } 735 736 static int 737 pgate_init(struct clknode *clk, device_t dev) 738 { 739 struct pgate_sc *sc; 740 uint32_t ena_reg, rst_reg, mask; 741 742 sc = clknode_get_softc(clk); 743 mask = 1 << (sc->idx % 32); 744 745 DEVICE_LOCK(sc); 746 RD4(sc, get_enable_reg(sc->idx), &ena_reg); 747 RD4(sc, get_reset_reg(sc->idx), &rst_reg); 748 DEVICE_UNLOCK(sc); 749 750 sc->enabled = ena_reg & mask ? 1 : 0; 751 clknode_init_parent_idx(clk, 0); 752 753 return(0); 754 } 755 756 static int 757 pgate_set_gate(struct clknode *clk, bool enable) 758 { 759 struct pgate_sc *sc; 760 uint32_t reg, mask, base_reg; 761 762 sc = clknode_get_softc(clk); 763 mask = 1 << (sc->idx % 32); 764 sc->enabled = enable; 765 base_reg = get_enable_reg(sc->idx); 766 767 DEVICE_LOCK(sc); 768 MD4(sc, base_reg, mask, enable ? mask : 0); 769 RD4(sc, base_reg, ®); 770 DEVICE_UNLOCK(sc); 771 772 DELAY(2); 773 return(0); 774 } 775 776 static int 777 pgate_get_gate(struct clknode *clk, bool *enabled) 778 { 779 struct pgate_sc *sc; 780 uint32_t reg, mask, base_reg; 781 782 sc = clknode_get_softc(clk); 783 mask = 1 << (sc->idx % 32); 784 base_reg = get_enable_reg(sc->idx); 785 786 DEVICE_LOCK(sc); 787 RD4(sc, base_reg, ®); 788 DEVICE_UNLOCK(sc); 789 *enabled = reg & mask ? true: false; 790 791 return(0); 792 } 793 int 794 tegra124_hwreset_by_idx(struct tegra124_car_softc *sc, intptr_t idx, bool reset) 795 { 796 uint32_t reg, mask, reset_reg; 797 798 mask = 1 << (idx % 32); 799 reset_reg = get_reset_reg(idx); 800 801 CLKDEV_DEVICE_LOCK(sc->dev); 802 CLKDEV_MODIFY_4(sc->dev, reset_reg, mask, reset ? mask : 0); 803 CLKDEV_READ_4(sc->dev, reset_reg, ®); 804 CLKDEV_DEVICE_UNLOCK(sc->dev); 805 806 return(0); 807 } 808 809 static int 810 pgate_register(struct clkdom *clkdom, struct pgate_def *clkdef) 811 { 812 struct clknode *clk; 813 struct pgate_sc *sc; 814 815 clk = clknode_create(clkdom, &tegra124_pgate_class, &clkdef->clkdef); 816 if (clk == NULL) 817 return (1); 818 819 sc = clknode_get_softc(clk); 820 sc->clkdev = clknode_get_device(clk); 821 sc->idx = clkdef->idx; 822 sc->flags = clkdef->flags; 823 824 clknode_register(clkdom, clk); 825 return (0); 826 } 827 828 void 829 tegra124_periph_clock(struct tegra124_car_softc *sc) 830 { 831 int i, rv; 832 833 for (i = 0; i < nitems(periph_def); i++) { 834 rv = periph_register(sc->clkdom, &periph_def[i]); 835 if (rv != 0) 836 panic("tegra124_periph_register failed"); 837 } 838 for (i = 0; i < nitems(pgate_def); i++) { 839 rv = pgate_register(sc->clkdom, &pgate_def[i]); 840 if (rv != 0) 841 panic("tegra124_pgate_register failed"); 842 } 843 844 }
Cache object: 78f5003043d3385a3b2f58a70212bde6
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