Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c
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1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/malloc.h> 36 #include <sys/rman.h> 37 38 #include <machine/bus.h> 39 #include <machine/fdt.h> 40 41 #include <dev/extres/hwreset/hwreset.h> 42 #include <dev/extres/phy/phy.h> 43 #include <dev/extres/regulator/regulator.h> 44 #include <dev/fdt/fdt_common.h> 45 #include <dev/fdt/fdt_pinctrl.h> 46 #include <dev/ofw/openfirm.h> 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <arm/nvidia/tegra_efuse.h> 51 52 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 53 54 #include "phydev_if.h" 55 56 /* FUSE calibration data. */ 57 #define FUSE_XUSB_CALIB 0x0F0 58 #define FUSE_XUSB_CALIB_HS_CURR_LEVEL_123(x) (((x) >> 15) & 0x3F); 59 #define FUSE_XUSB_CALIB_HS_IREF_CAP(x) (((x) >> 13) & 0x03); 60 #define FUSE_XUSB_CALIB_HS_SQUELCH_LEVEL(x) (((x) >> 11) & 0x03); 61 #define FUSE_XUSB_CALIB_HS_TERM_RANGE_ADJ(x) (((x) >> 7) & 0x0F); 62 #define FUSE_XUSB_CALIB_HS_CURR_LEVEL_0(x) (((x) >> 0) & 0x3F); 63 64 /* Registers. */ 65 #define XUSB_PADCTL_USB2_PAD_MUX 0x004 66 67 #define XUSB_PADCTL_USB2_PORT_CAP 0x008 68 #define USB2_PORT_CAP_ULPI_PORT_INTERNAL (1 << 25) 69 #define USB2_PORT_CAP_ULPI_PORT_CAP (1 << 24) 70 #define USB2_PORT_CAP_PORT_REVERSE_ID(p) (1 << (3 + (p) * 4)) 71 #define USB2_PORT_CAP_PORT_INTERNAL(p) (1 << (2 + (p) * 4)) 72 #define USB2_PORT_CAP_PORT_CAP(p, x) (((x) & 3) << ((p) * 4)) 73 #define USB2_PORT_CAP_PORT_CAP_OTG 0x3 74 #define USB2_PORT_CAP_PORT_CAP_DEVICE 0x2 75 #define USB2_PORT_CAP_PORT_CAP_HOST 0x1 76 #define USB2_PORT_CAP_PORT_CAP_DISABLED 0x0 77 78 #define XUSB_PADCTL_SS_PORT_MAP 0x014 79 #define SS_PORT_MAP_PORT_INTERNAL(p) (1 << (3 + (p) * 4)) 80 #define SS_PORT_MAP_PORT_MAP(p, x) (((x) & 7) << ((p) * 4)) 81 82 #define XUSB_PADCTL_ELPG_PROGRAM 0x01C 83 #define ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26) 84 #define ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25) 85 #define ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24) 86 #define ELPG_PROGRAM_SSP_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4)) 87 #define ELPG_PROGRAM_SSP_ELPG_CLAMP_EN_EARLY(x) (1 << (17 + (x) * 4)) 88 #define ELPG_PROGRAM_SSP_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4)) 89 90 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040 91 #define IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19) 92 #define IOPHY_PLL_P0_CTL1_REFCLK_SEL(x) (((x) & 0xF) << 12) 93 #define IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1) 94 95 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044 96 #define IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6) 97 #define IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5) 98 #define IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4) 99 100 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(x) (0x058 + (x) * 4) 101 #define IOPHY_USB3_PAD_CTL2_CDR_CNTL(x) (((x) & 0x00FF) << 4) 102 #define IOPHY_USB3_PAD_CTL2_RX_EQ(x) (((x) & 0xFFFF) << 8) 103 #define IOPHY_USB3_PAD_CTL2_RX_WANDER(x) (((x) & 0x000F) << 4) 104 #define IOPHY_USB3_PAD_CTL2_RX_TERM_CNTL(x) (((x) & 0x0003) << 2) 105 #define IOPHY_USB3_PAD_CTL2_TX_TERM_CNTL(x) (((x) & 0x0003) << 0) 106 107 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(x) (0x068 + (x) * 4) 108 109 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0(x) (0x0A0 + (x) * 4) 110 #define USB2_OTG_PAD_CTL0_LSBIAS_SEL (1 << 23) 111 #define USB2_OTG_PAD_CTL0_DISCON_DETECT_METHOD (1 << 22) 112 #define USB2_OTG_PAD_CTL0_PD_ZI (1 << 21) 113 #define USB2_OTG_PAD_CTL0_PD2 (1 << 20) 114 #define USB2_OTG_PAD_CTL0_PD (1 << 19) 115 #define USB2_OTG_PAD_CTL0_TERM_EN (1 << 18) 116 #define USB2_OTG_PAD_CTL0_LS_LS_FSLEW(x) (((x) & 0x03) << 16) 117 #define USB2_OTG_PAD_CTL0_LS_RSLEW(x) (((x) & 0x03) << 14) 118 #define USB2_OTG_PAD_CTL0_FS_SLEW(x) (((x) & 0x03) << 12) 119 #define USB2_OTG_PAD_CTL0_HS_SLEW(x) (((x) & 0x3F) << 6) 120 #define USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(x) (((x) & 0x3F) << 0) 121 122 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1(x) (0x0AC + (x) * 4) 123 #define USB2_OTG_PAD_CTL1_RPU_RANGE_ADJ(x) (((x) & 0x3) << 11) 124 #define USB2_OTG_PAD_CTL1_HS_IREF_CAP(x) (((x) & 0x3) << 9) 125 #define USB2_OTG_PAD_CTL1_SPARE(x) (((x) & 0x3) << 7) 126 #define USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(x) (((x) & 0xF) << 3) 127 #define USB2_OTG_PAD_CTL1_PD_DR (1 << 2) 128 #define USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP (1 << 1) 129 #define USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP (1 << 0) 130 131 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x0B8 132 #define USB2_BIAS_PAD_CTL0_ADJRPU(x) (((x) & 0x7) << 14) 133 #define USB2_BIAS_PAD_CTL0_PD_TRK (1 << 13) 134 #define USB2_BIAS_PAD_CTL0_PD (1 << 12) 135 #define USB2_BIAS_PAD_CTL0_TERM_OFFSETL(x) (((x) & 0x3) << 9) 136 #define USB2_BIAS_PAD_CTL0_VBUS_LEVEL(x) (((x) & 0x3) << 7) 137 #define USB2_BIAS_PAD_CTL0_HS_CHIRP_LEVEL(x) (((x) & 0x3) << 5) 138 #define USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(x) (((x) & 0x7) << 2) 139 #define USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(x) (((x) & 0x3) << 0) 140 141 #define XUSB_PADCTL_HSIC_PAD0_CTL0 0x0C8 142 #define HSIC_PAD0_CTL0_HSIC_OPT(x) (((x) & 0xF) << 16) 143 #define HSIC_PAD0_CTL0_TX_SLEWN(x) (((x) & 0xF) << 12) 144 #define HSIC_PAD0_CTL0_TX_SLEWP(x) (((x) & 0xF) << 8) 145 #define HSIC_PAD0_CTL0_TX_RTUNEN(x) (((x) & 0xF) << 4) 146 #define HSIC_PAD0_CTL0_TX_RTUNEP(x) (((x) & 0xF) << 0) 147 148 #define XUSB_PADCTL_USB3_PAD_MUX 0x134 149 #define USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x))) 150 #define USB3_PAD_MUX_SATA_IDDQ_DISABLE (1 << 6) 151 152 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138 153 #define IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27) 154 #define IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24) 155 #define IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3) 156 #define IOPHY_PLL_S0_CTL1_PLL_RST_L (1 << 1) 157 #define IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0) 158 159 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2 0x13C 160 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL3 0x140 161 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL4 0x144 162 163 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148 164 #define IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1) 165 #define IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0) 166 167 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL2 0x14C 168 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL3 0x150 169 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL4 0x154 170 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL5 0x158 171 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL6 0x15C 172 173 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) 174 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) 175 176 struct padctl_softc { 177 device_t dev; 178 struct resource *mem_res; 179 hwreset_t rst; 180 int phy_ena_cnt; 181 182 /* Fuses calibration data */ 183 uint32_t hs_curr_level_0; 184 uint32_t hs_curr_level_123; 185 uint32_t hs_iref_cap; 186 uint32_t hs_term_range_adj; 187 uint32_t hs_squelch_level; 188 189 uint32_t hs_curr_level_offset; 190 }; 191 192 static struct ofw_compat_data compat_data[] = { 193 {"nvidia,tegra124-xusb-padctl", 1}, 194 {NULL, 0}, 195 }; 196 197 /* Ports. */ 198 enum padctl_port_type { 199 PADCTL_PORT_USB2, 200 PADCTL_PORT_ULPI, 201 PADCTL_PORT_HSIC, 202 PADCTL_PORT_USB3, 203 }; 204 205 struct padctl_lane; 206 struct padctl_port { 207 enum padctl_port_type type; 208 const char *name; 209 const char *base_name; 210 int idx; 211 int (*init)(struct padctl_softc *sc, 212 struct padctl_port *port); 213 214 /* Runtime data. */ 215 bool enabled; 216 regulator_t supply_vbus; /* USB2, USB3 */ 217 bool internal; /* ULPI, USB2, USB3 */ 218 uint32_t companion; /* USB3 */ 219 struct padctl_lane *lane; 220 }; 221 222 static int usb3_port_init(struct padctl_softc *sc, struct padctl_port *port); 223 224 #define PORT(t, n, p, i) { \ 225 .type = t, \ 226 .name = n "-" #p, \ 227 .base_name = n, \ 228 .idx = p, \ 229 .init = i, \ 230 } 231 static struct padctl_port ports_tbl[] = { 232 PORT(PADCTL_PORT_USB2, "usb2", 0, NULL), 233 PORT(PADCTL_PORT_USB2, "usb2", 1, NULL), 234 PORT(PADCTL_PORT_USB2, "usb2", 2, NULL), 235 PORT(PADCTL_PORT_ULPI, "ulpi", 0, NULL), 236 PORT(PADCTL_PORT_HSIC, "hsic", 0, NULL), 237 PORT(PADCTL_PORT_HSIC, "hsic", 1, NULL), 238 PORT(PADCTL_PORT_USB3, "usb3", 0, usb3_port_init), 239 PORT(PADCTL_PORT_USB3, "usb3", 1, usb3_port_init), 240 }; 241 242 /* Pads - a group of lannes. */ 243 enum padctl_pad_type { 244 PADCTL_PAD_USB2, 245 PADCTL_PAD_ULPI, 246 PADCTL_PAD_HSIC, 247 PADCTL_PAD_PCIE, 248 PADCTL_PAD_SATA, 249 }; 250 251 struct padctl_lane; 252 struct padctl_pad { 253 const char *name; 254 enum padctl_pad_type type; 255 int (*powerup)(struct padctl_softc *sc, 256 struct padctl_lane *lane); 257 int (*powerdown)(struct padctl_softc *sc, 258 struct padctl_lane *lane); 259 /* Runtime data. */ 260 bool enabled; 261 struct padctl_lane *lanes[8]; /* Safe maximum value. */ 262 int nlanes; 263 }; 264 265 static int usb2_powerup(struct padctl_softc *sc, struct padctl_lane *lane); 266 static int usb2_powerdown(struct padctl_softc *sc, struct padctl_lane *lane); 267 static int pcie_powerup(struct padctl_softc *sc, struct padctl_lane *lane); 268 static int pcie_powerdown(struct padctl_softc *sc, struct padctl_lane *lane); 269 static int sata_powerup(struct padctl_softc *sc, struct padctl_lane *lane); 270 static int sata_powerdown(struct padctl_softc *sc, struct padctl_lane *lane); 271 272 #define PAD(n, t, u, d) { \ 273 .name = n, \ 274 .type = t, \ 275 .powerup = u, \ 276 .powerdown = d, \ 277 } 278 static struct padctl_pad pads_tbl[] = { 279 PAD("usb2", PADCTL_PAD_USB2, usb2_powerup, usb2_powerdown), 280 PAD("ulpi", PADCTL_PAD_ULPI, NULL, NULL), 281 PAD("hsic", PADCTL_PAD_HSIC, NULL, NULL), 282 PAD("pcie", PADCTL_PAD_PCIE, pcie_powerup, pcie_powerdown), 283 PAD("sata", PADCTL_PAD_SATA, sata_powerup, sata_powerdown), 284 }; 285 286 /* Lanes. */ 287 static char *otg_mux[] = {"snps", "xusb", "uart", "rsvd"}; 288 static char *usb_mux[] = {"snps", "xusb"}; 289 static char *pci_mux[] = {"pcie", "usb3-ss", "sata", "rsvd"}; 290 291 struct padctl_lane { 292 const char *name; 293 int idx; 294 bus_size_t reg; 295 uint32_t shift; 296 uint32_t mask; 297 char **mux; 298 int nmux; 299 /* Runtime data. */ 300 bool enabled; 301 struct padctl_pad *pad; 302 struct padctl_port *port; 303 int mux_idx; 304 305 }; 306 307 #define LANE(n, p, r, s, m, mx) { \ 308 .name = n "-" #p, \ 309 .idx = p, \ 310 .reg = r, \ 311 .shift = s, \ 312 .mask = m, \ 313 .mux = mx, \ 314 .nmux = nitems(mx), \ 315 } 316 static struct padctl_lane lanes_tbl[] = { 317 LANE("usb2", 0, XUSB_PADCTL_USB2_PAD_MUX, 0, 0x3, otg_mux), 318 LANE("usb2", 1, XUSB_PADCTL_USB2_PAD_MUX, 2, 0x3, otg_mux), 319 LANE("usb2", 2, XUSB_PADCTL_USB2_PAD_MUX, 4, 0x3, otg_mux), 320 LANE("ulpi", 0, XUSB_PADCTL_USB2_PAD_MUX, 12, 0x1, usb_mux), 321 LANE("hsic", 0, XUSB_PADCTL_USB2_PAD_MUX, 14, 0x1, usb_mux), 322 LANE("hsic", 1, XUSB_PADCTL_USB2_PAD_MUX, 15, 0x1, usb_mux), 323 LANE("pcie", 0, XUSB_PADCTL_USB3_PAD_MUX, 16, 0x3, pci_mux), 324 LANE("pcie", 1, XUSB_PADCTL_USB3_PAD_MUX, 18, 0x3, pci_mux), 325 LANE("pcie", 2, XUSB_PADCTL_USB3_PAD_MUX, 20, 0x3, pci_mux), 326 LANE("pcie", 3, XUSB_PADCTL_USB3_PAD_MUX, 22, 0x3, pci_mux), 327 LANE("pcie", 4, XUSB_PADCTL_USB3_PAD_MUX, 24, 0x3, pci_mux), 328 LANE("sata", 0, XUSB_PADCTL_USB3_PAD_MUX, 26, 0x3, pci_mux), 329 }; 330 331 /* Define all possible mappings for USB3 port lanes */ 332 struct padctl_lane_map { 333 int port_idx; 334 enum padctl_pad_type pad_type; 335 int lane_idx; 336 }; 337 338 #define LANE_MAP(pi, pt, li) { \ 339 .port_idx = pi, \ 340 .pad_type = pt, \ 341 .lane_idx = li, \ 342 } 343 static struct padctl_lane_map lane_map_tbl[] = { 344 LANE_MAP(0, PADCTL_PAD_PCIE, 0), /* port USB3-0 -> lane PCIE-0 */ 345 LANE_MAP(1, PADCTL_PAD_PCIE, 1), /* port USB3-1 -> lane PCIE-1 */ 346 /* -- or -- */ 347 LANE_MAP(1, PADCTL_PAD_SATA, 0), /* port USB3-1 -> lane SATA-0 */ 348 }; 349 350 /* Phy class and methods. */ 351 static int xusbpadctl_phy_enable(struct phynode *phy, bool enable); 352 static phynode_method_t xusbpadctl_phynode_methods[] = { 353 PHYNODEMETHOD(phynode_enable, xusbpadctl_phy_enable), 354 PHYNODEMETHOD_END 355 356 }; 357 DEFINE_CLASS_1(xusbpadctl_phynode, xusbpadctl_phynode_class, 358 xusbpadctl_phynode_methods, 0, phynode_class); 359 360 static struct padctl_port *search_lane_port(struct padctl_softc *sc, 361 struct padctl_lane *lane); 362 /* ------------------------------------------------------------------------- 363 * 364 * PHY functions 365 */ 366 static int 367 usb3_port_init(struct padctl_softc *sc, struct padctl_port *port) 368 { 369 uint32_t reg; 370 371 reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP); 372 if (port->internal) 373 reg &= ~SS_PORT_MAP_PORT_INTERNAL(port->idx); 374 else 375 reg |= SS_PORT_MAP_PORT_INTERNAL(port->idx); 376 reg &= ~SS_PORT_MAP_PORT_MAP(port->idx, ~0); 377 reg |= SS_PORT_MAP_PORT_MAP(port->idx, port->companion); 378 WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg); 379 380 reg = RD4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx)); 381 reg &= ~IOPHY_USB3_PAD_CTL2_CDR_CNTL(~0); 382 reg &= ~IOPHY_USB3_PAD_CTL2_RX_EQ(~0); 383 reg &= ~IOPHY_USB3_PAD_CTL2_RX_WANDER(~0); 384 reg |= IOPHY_USB3_PAD_CTL2_CDR_CNTL(0x24); 385 reg |= IOPHY_USB3_PAD_CTL2_RX_EQ(0xF070); 386 reg |= IOPHY_USB3_PAD_CTL2_RX_WANDER(0xF); 387 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx), reg); 388 389 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(port->idx), 390 0x002008EE); 391 392 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 393 reg &= ~ELPG_PROGRAM_SSP_ELPG_VCORE_DOWN(port->idx); 394 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 395 DELAY(100); 396 397 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 398 reg &= ~ELPG_PROGRAM_SSP_ELPG_CLAMP_EN_EARLY(port->idx); 399 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 400 DELAY(100); 401 402 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 403 reg &= ~ELPG_PROGRAM_SSP_ELPG_CLAMP_EN(port->idx); 404 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 405 DELAY(100); 406 407 return (0); 408 } 409 410 static int 411 pcie_powerup(struct padctl_softc *sc, struct padctl_lane *lane) 412 { 413 uint32_t reg; 414 int i; 415 416 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 417 reg &= ~IOPHY_PLL_P0_CTL1_REFCLK_SEL(~0); 418 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg); 419 DELAY(100); 420 421 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); 422 reg |= IOPHY_PLL_P0_CTL2_REFCLKBUF_EN; 423 reg |= IOPHY_PLL_P0_CTL2_TXCLKREF_EN; 424 reg |= IOPHY_PLL_P0_CTL2_TXCLKREF_SEL; 425 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2, reg); 426 DELAY(100); 427 428 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 429 reg |= IOPHY_PLL_P0_CTL1_PLL_RST; 430 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg); 431 DELAY(100); 432 433 for (i = 100; i > 0; i--) { 434 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 435 if (reg & IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) 436 break; 437 DELAY(10); 438 } 439 if (i <= 0) { 440 device_printf(sc->dev, "Failed to power up PCIe phy\n"); 441 return (ETIMEDOUT); 442 } 443 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 444 reg |= USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx); 445 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 446 447 return (0); 448 } 449 450 static int 451 pcie_powerdown(struct padctl_softc *sc, struct padctl_lane *lane) 452 { 453 uint32_t reg; 454 455 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 456 reg &= ~USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx); 457 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 458 459 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 460 reg &= ~IOPHY_PLL_P0_CTL1_PLL_RST; 461 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg); 462 DELAY(100); 463 464 return (0); 465 466 } 467 468 static int 469 sata_powerup(struct padctl_softc *sc, struct padctl_lane *lane) 470 { 471 uint32_t reg; 472 int i; 473 474 reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 475 reg &= ~IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; 476 reg &= ~IOPHY_MISC_PAD_S0_CTL1_IDDQ; 477 WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg); 478 479 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 480 reg &= ~IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; 481 reg &= ~IOPHY_PLL_S0_CTL1_PLL_IDDQ; 482 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 483 484 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 485 reg |= IOPHY_PLL_S0_CTL1_PLL1_MODE; 486 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 487 488 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 489 reg |= IOPHY_PLL_S0_CTL1_PLL_RST_L; 490 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 491 492 for (i = 100; i >= 0; i--) { 493 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 494 if (reg & IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) 495 break; 496 DELAY(100); 497 } 498 if (i <= 0) { 499 device_printf(sc->dev, "Failed to power up SATA phy\n"); 500 return (ETIMEDOUT); 501 } 502 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 503 reg |= IOPHY_PLL_S0_CTL1_PLL_RST_L; 504 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 505 506 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 507 reg |= USB3_PAD_MUX_SATA_IDDQ_DISABLE; 508 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 509 510 return (0); 511 } 512 513 static int 514 sata_powerdown(struct padctl_softc *sc, struct padctl_lane *lane) 515 { 516 uint32_t reg; 517 518 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 519 reg &= ~USB3_PAD_MUX_SATA_IDDQ_DISABLE; 520 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 521 522 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 523 reg &= ~IOPHY_PLL_S0_CTL1_PLL_RST_L; 524 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 525 DELAY(100); 526 527 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 528 reg &= ~IOPHY_PLL_S0_CTL1_PLL1_MODE; 529 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 530 DELAY(100); 531 532 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 533 reg |= IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; 534 reg |= IOPHY_PLL_S0_CTL1_PLL_IDDQ; 535 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 536 DELAY(100); 537 538 reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 539 reg |= IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; 540 reg |= IOPHY_MISC_PAD_S0_CTL1_IDDQ; 541 WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg); 542 DELAY(100); 543 544 return (0); 545 } 546 547 static int 548 usb2_powerup(struct padctl_softc *sc, struct padctl_lane *lane) 549 { 550 uint32_t reg; 551 struct padctl_port *port; 552 int rv; 553 554 port = search_lane_port(sc, lane); 555 if (port == NULL) { 556 device_printf(sc->dev, "Cannot find port for lane: %s\n", 557 lane->name); 558 } 559 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 560 reg &= ~USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(~0); 561 reg &= ~USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(~0); 562 reg |= USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(sc->hs_squelch_level); 563 reg |= USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(5); 564 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg); 565 566 reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP); 567 reg &= ~USB2_PORT_CAP_PORT_CAP(lane->idx, ~0); 568 reg |= USB2_PORT_CAP_PORT_CAP(lane->idx, USB2_PORT_CAP_PORT_CAP_HOST); 569 WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg); 570 571 reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx)); 572 reg &= ~USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(~0); 573 reg &= ~USB2_OTG_PAD_CTL0_HS_SLEW(~0); 574 reg &= ~USB2_OTG_PAD_CTL0_LS_RSLEW(~0); 575 reg &= ~USB2_OTG_PAD_CTL0_PD; 576 reg &= ~USB2_OTG_PAD_CTL0_PD2; 577 reg &= ~USB2_OTG_PAD_CTL0_PD_ZI; 578 579 reg |= USB2_OTG_PAD_CTL0_HS_SLEW(14); 580 if (lane->idx == 0) { 581 reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level_0); 582 reg |= USB2_OTG_PAD_CTL0_LS_RSLEW(3); 583 } else { 584 reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level_123); 585 reg |= USB2_OTG_PAD_CTL0_LS_RSLEW(0); 586 } 587 WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg); 588 589 reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx)); 590 reg &= ~USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(~0); 591 reg &= ~USB2_OTG_PAD_CTL1_HS_IREF_CAP(~0); 592 reg &= ~USB2_OTG_PAD_CTL1_PD_DR; 593 reg &= ~USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP; 594 reg &= ~USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP; 595 596 reg |= USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(sc->hs_term_range_adj); 597 reg |= USB2_OTG_PAD_CTL1_HS_IREF_CAP(sc->hs_iref_cap); 598 WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg); 599 600 if (port != NULL && port->supply_vbus != NULL) { 601 rv = regulator_enable(port->supply_vbus); 602 if (rv != 0) { 603 device_printf(sc->dev, 604 "Cannot enable vbus regulator\n"); 605 return (rv); 606 } 607 } 608 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 609 reg &= ~USB2_BIAS_PAD_CTL0_PD; 610 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg); 611 612 return (0); 613 } 614 615 static int 616 usb2_powerdown(struct padctl_softc *sc, struct padctl_lane *lane) 617 { 618 uint32_t reg; 619 struct padctl_port *port; 620 int rv; 621 622 port = search_lane_port(sc, lane); 623 if (port == NULL) { 624 device_printf(sc->dev, "Cannot find port for lane: %s\n", 625 lane->name); 626 } 627 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 628 reg |= USB2_BIAS_PAD_CTL0_PD; 629 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg); 630 631 if (port != NULL && port->supply_vbus != NULL) { 632 rv = regulator_enable(port->supply_vbus); 633 if (rv != 0) { 634 device_printf(sc->dev, 635 "Cannot disable vbus regulator\n"); 636 return (rv); 637 } 638 } 639 return (0); 640 } 641 642 static int 643 phy_powerup(struct padctl_softc *sc) 644 { 645 uint32_t reg; 646 647 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 648 reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; 649 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 650 DELAY(100); 651 652 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 653 reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; 654 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 655 DELAY(100); 656 657 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 658 reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; 659 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 660 DELAY(100); 661 662 return (0); 663 } 664 665 static int 666 phy_powerdown(struct padctl_softc *sc) 667 { 668 uint32_t reg; 669 670 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 671 reg |= ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; 672 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 673 DELAY(100); 674 675 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 676 reg |= ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; 677 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 678 DELAY(100); 679 680 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 681 reg |= ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; 682 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 683 DELAY(100); 684 685 return (0); 686 } 687 688 static int 689 xusbpadctl_phy_enable(struct phynode *phy, bool enable) 690 { 691 device_t dev; 692 intptr_t id; 693 struct padctl_softc *sc; 694 struct padctl_lane *lane; 695 struct padctl_pad *pad; 696 int rv; 697 698 dev = phynode_get_device(phy); 699 id = phynode_get_id(phy); 700 sc = device_get_softc(dev); 701 702 if (id < 0 || id >= nitems(lanes_tbl)) { 703 device_printf(dev, "Unknown phy: %d\n", id); 704 return (ENXIO); 705 } 706 lane = lanes_tbl + id; 707 if (!lane->enabled) { 708 device_printf(dev, "Lane is not enabled/configured: %s\n", 709 lane->name); 710 return (ENXIO); 711 } 712 pad = lane->pad; 713 if (enable) { 714 if (sc->phy_ena_cnt == 0) { 715 rv = phy_powerup(sc); 716 if (rv != 0) 717 return (rv); 718 } 719 sc->phy_ena_cnt++; 720 } 721 722 if (enable) 723 rv = pad->powerup(sc, lane); 724 else 725 rv = pad->powerdown(sc, lane); 726 if (rv != 0) 727 return (rv); 728 729 if (!enable) { 730 if (sc->phy_ena_cnt == 1) { 731 rv = phy_powerdown(sc); 732 if (rv != 0) 733 return (rv); 734 } 735 sc->phy_ena_cnt--; 736 } 737 738 return (0); 739 } 740 741 /* ------------------------------------------------------------------------- 742 * 743 * FDT processing 744 */ 745 static struct padctl_port * 746 search_port(struct padctl_softc *sc, char *port_name) 747 { 748 int i; 749 750 for (i = 0; i < nitems(ports_tbl); i++) { 751 if (strcmp(port_name, ports_tbl[i].name) == 0) 752 return (&ports_tbl[i]); 753 } 754 return (NULL); 755 } 756 757 static struct padctl_port * 758 search_lane_port(struct padctl_softc *sc, struct padctl_lane *lane) 759 { 760 int i; 761 762 for (i = 0; i < nitems(ports_tbl); i++) { 763 if (!ports_tbl[i].enabled) 764 continue; 765 if (ports_tbl[i].lane == lane) 766 return (ports_tbl + i); 767 } 768 return (NULL); 769 } 770 771 static struct padctl_lane * 772 search_lane(struct padctl_softc *sc, char *lane_name) 773 { 774 int i; 775 776 for (i = 0; i < nitems(lanes_tbl); i++) { 777 if (strcmp(lane_name, lanes_tbl[i].name) == 0) 778 return (lanes_tbl + i); 779 } 780 return (NULL); 781 } 782 783 static struct padctl_lane * 784 search_pad_lane(struct padctl_softc *sc, enum padctl_pad_type type, int idx) 785 { 786 int i; 787 788 for (i = 0; i < nitems(lanes_tbl); i++) { 789 if (!lanes_tbl[i].enabled) 790 continue; 791 if (type == lanes_tbl[i].pad->type && idx == lanes_tbl[i].idx) 792 return (lanes_tbl + i); 793 } 794 return (NULL); 795 } 796 797 static struct padctl_lane * 798 search_usb3_pad_lane(struct padctl_softc *sc, int idx) 799 { 800 int i; 801 struct padctl_lane *lane, *tmp; 802 803 lane = NULL; 804 for (i = 0; i < nitems(lane_map_tbl); i++) { 805 if (idx != lane_map_tbl[i].port_idx) 806 continue; 807 tmp = search_pad_lane(sc, lane_map_tbl[i].pad_type, 808 lane_map_tbl[i].lane_idx); 809 if (tmp == NULL) 810 continue; 811 if (strcmp(tmp->mux[tmp->mux_idx], "usb3-ss") != 0) 812 continue; 813 if (lane != NULL) { 814 device_printf(sc->dev, "Duplicated mappings found for" 815 " lanes: %s and %s\n", lane->name, tmp->name); 816 return (NULL); 817 } 818 lane = tmp; 819 } 820 return (lane); 821 } 822 823 static struct padctl_pad * 824 search_pad(struct padctl_softc *sc, char *pad_name) 825 { 826 int i; 827 828 for (i = 0; i < nitems(pads_tbl); i++) { 829 if (strcmp(pad_name, pads_tbl[i].name) == 0) 830 return (pads_tbl + i); 831 } 832 return (NULL); 833 } 834 835 static int 836 search_mux(struct padctl_softc *sc, struct padctl_lane *lane, char *fnc_name) 837 { 838 int i; 839 840 for (i = 0; i < lane->nmux; i++) { 841 if (strcmp(fnc_name, lane->mux[i]) == 0) 842 return (i); 843 } 844 return (-1); 845 } 846 847 static int 848 config_lane(struct padctl_softc *sc, struct padctl_lane *lane) 849 { 850 uint32_t reg; 851 852 reg = RD4(sc, lane->reg); 853 reg &= ~(lane->mask << lane->shift); 854 reg |= (lane->mux_idx & lane->mask) << lane->shift; 855 WR4(sc, lane->reg, reg); 856 return (0); 857 } 858 859 static int 860 process_lane(struct padctl_softc *sc, phandle_t node, struct padctl_pad *pad) 861 { 862 struct padctl_lane *lane; 863 struct phynode *phynode; 864 struct phynode_init_def phy_init; 865 char *name; 866 char *function; 867 int rv; 868 869 name = NULL; 870 function = NULL; 871 rv = OF_getprop_alloc(node, "name", (void **)&name); 872 if (rv <= 0) { 873 device_printf(sc->dev, "Cannot read lane name.\n"); 874 return (ENXIO); 875 } 876 877 lane = search_lane(sc, name); 878 if (lane == NULL) { 879 device_printf(sc->dev, "Unknown lane: %s\n", name); 880 rv = ENXIO; 881 goto end; 882 } 883 884 /* Read function (mux) settings. */ 885 rv = OF_getprop_alloc(node, "nvidia,function", (void **)&function); 886 if (rv <= 0) { 887 device_printf(sc->dev, "Cannot read lane function.\n"); 888 rv = ENXIO; 889 goto end; 890 } 891 892 lane->mux_idx = search_mux(sc, lane, function); 893 if (lane->mux_idx == ~0) { 894 device_printf(sc->dev, "Unknown function %s for lane %s\n", 895 function, name); 896 rv = ENXIO; 897 goto end; 898 } 899 900 rv = config_lane(sc, lane); 901 if (rv != 0) { 902 device_printf(sc->dev, "Cannot configure lane: %s: %d\n", 903 name, rv); 904 rv = ENXIO; 905 goto end; 906 } 907 lane->pad = pad; 908 lane->enabled = true; 909 pad->lanes[pad->nlanes++] = lane; 910 911 /* Create and register phy. */ 912 bzero(&phy_init, sizeof(phy_init)); 913 phy_init.id = lane - lanes_tbl; 914 phy_init.ofw_node = node; 915 phynode = phynode_create(sc->dev, &xusbpadctl_phynode_class, &phy_init); 916 if (phynode == NULL) { 917 device_printf(sc->dev, "Cannot create phy\n"); 918 rv = ENXIO; 919 goto end; 920 } 921 if (phynode_register(phynode) == NULL) { 922 device_printf(sc->dev, "Cannot create phy\n"); 923 return (ENXIO); 924 } 925 926 rv = 0; 927 928 end: 929 if (name != NULL) 930 OF_prop_free(name); 931 if (function != NULL) 932 OF_prop_free(function); 933 return (rv); 934 } 935 936 static int 937 process_pad(struct padctl_softc *sc, phandle_t node) 938 { 939 struct padctl_pad *pad; 940 char *name; 941 int rv; 942 943 name = NULL; 944 rv = OF_getprop_alloc(node, "name", (void **)&name); 945 if (rv <= 0) { 946 device_printf(sc->dev, "Cannot read pad name.\n"); 947 return (ENXIO); 948 } 949 pad = search_pad(sc, name); 950 if (pad == NULL) { 951 device_printf(sc->dev, "Unknown pad: %s\n", name); 952 rv = ENXIO; 953 goto end; 954 } 955 956 /* Read and process associated lanes. */ 957 node = ofw_bus_find_child(node, "lanes"); 958 if (node <= 0) { 959 device_printf(sc->dev, "Cannot find regulators subnode\n"); 960 rv = ENXIO; 961 goto end; 962 } 963 964 for (node = OF_child(node); node != 0; node = OF_peer(node)) { 965 if (!ofw_bus_node_status_okay(node)) 966 continue; 967 968 rv = process_lane(sc, node, pad); 969 if (rv != 0) 970 goto end; 971 } 972 pad->enabled = true; 973 rv = 0; 974 end: 975 if (name != NULL) 976 OF_prop_free(name); 977 return (rv); 978 } 979 980 static int 981 process_port(struct padctl_softc *sc, phandle_t node) 982 { 983 984 struct padctl_port *port; 985 char *name; 986 int rv; 987 988 name = NULL; 989 rv = OF_getprop_alloc(node, "name", (void **)&name); 990 if (rv <= 0) { 991 device_printf(sc->dev, "Cannot read port name.\n"); 992 return (ENXIO); 993 } 994 995 port = search_port(sc, name); 996 if (port == NULL) { 997 device_printf(sc->dev, "Unknown port: %s\n", name); 998 rv = ENXIO; 999 goto end; 1000 } 1001 1002 if (port->type == PADCTL_PORT_USB3) { 1003 rv = OF_getencprop(node, "nvidia,usb2-companion", 1004 &(port->companion), sizeof(port->companion)); 1005 if (rv <= 0) { 1006 device_printf(sc->dev, 1007 "Missing 'nvidia,usb2-companion' property " 1008 "for port: %s\n", name); 1009 rv = ENXIO; 1010 goto end; 1011 } 1012 } 1013 1014 if (OF_hasprop(node, "vbus-supply")) { 1015 rv = regulator_get_by_ofw_property(sc->dev, 0, 1016 "vbus-supply", &port->supply_vbus); 1017 if (rv <= 0) { 1018 device_printf(sc->dev, 1019 "Cannot get 'vbus-supply' regulator " 1020 "for port: %s\n", name); 1021 rv = ENXIO; 1022 goto end; 1023 } 1024 } 1025 1026 if (OF_hasprop(node, "nvidia,internal")) 1027 port->internal = true; 1028 /* Find assigned lane */ 1029 if (port->lane == NULL) { 1030 switch(port->type) { 1031 /* Routing is fixed for USB2, ULPI AND HSIC. */ 1032 case PADCTL_PORT_USB2: 1033 port->lane = search_pad_lane(sc, PADCTL_PAD_USB2, 1034 port->idx); 1035 break; 1036 case PADCTL_PORT_ULPI: 1037 port->lane = search_pad_lane(sc, PADCTL_PAD_ULPI, 1038 port->idx); 1039 break; 1040 case PADCTL_PORT_HSIC: 1041 port->lane = search_pad_lane(sc, PADCTL_PAD_HSIC, 1042 port->idx); 1043 break; 1044 case PADCTL_PORT_USB3: 1045 port->lane = search_usb3_pad_lane(sc, port->idx); 1046 break; 1047 } 1048 } 1049 if (port->lane == NULL) { 1050 device_printf(sc->dev, "Cannot find lane for port: %s\n", name); 1051 rv = ENXIO; 1052 goto end; 1053 } 1054 port->enabled = true; 1055 rv = 0; 1056 end: 1057 if (name != NULL) 1058 OF_prop_free(name); 1059 return (rv); 1060 } 1061 1062 static int 1063 parse_fdt(struct padctl_softc *sc, phandle_t base_node) 1064 { 1065 phandle_t node; 1066 int rv; 1067 1068 rv = 0; 1069 node = ofw_bus_find_child(base_node, "pads"); 1070 1071 if (node <= 0) { 1072 device_printf(sc->dev, "Cannot find pads subnode.\n"); 1073 return (ENXIO); 1074 } 1075 for (node = OF_child(node); node != 0; node = OF_peer(node)) { 1076 if (!ofw_bus_node_status_okay(node)) 1077 continue; 1078 rv = process_pad(sc, node); 1079 if (rv != 0) 1080 return (rv); 1081 } 1082 1083 node = ofw_bus_find_child(base_node, "ports"); 1084 if (node <= 0) { 1085 device_printf(sc->dev, "Cannot find ports subnode.\n"); 1086 return (ENXIO); 1087 } 1088 for (node = OF_child(node); node != 0; node = OF_peer(node)) { 1089 if (!ofw_bus_node_status_okay(node)) 1090 continue; 1091 rv = process_port(sc, node); 1092 if (rv != 0) 1093 return (rv); 1094 } 1095 1096 return (0); 1097 } 1098 1099 static void 1100 load_calibration(struct padctl_softc *sc) 1101 { 1102 uint32_t reg; 1103 1104 /* All XUSB pad calibrations are packed into single dword.*/ 1105 reg = tegra_fuse_read_4(FUSE_XUSB_CALIB); 1106 sc->hs_curr_level_0 = FUSE_XUSB_CALIB_HS_CURR_LEVEL_0(reg); 1107 sc->hs_curr_level_123 = FUSE_XUSB_CALIB_HS_CURR_LEVEL_123(reg); 1108 sc->hs_iref_cap = FUSE_XUSB_CALIB_HS_IREF_CAP(reg); 1109 sc->hs_squelch_level = FUSE_XUSB_CALIB_HS_SQUELCH_LEVEL(reg); 1110 sc->hs_term_range_adj = FUSE_XUSB_CALIB_HS_TERM_RANGE_ADJ(reg); 1111 } 1112 1113 /* ------------------------------------------------------------------------- 1114 * 1115 * BUS functions 1116 */ 1117 static int 1118 xusbpadctl_probe(device_t dev) 1119 { 1120 1121 if (!ofw_bus_status_okay(dev)) 1122 return (ENXIO); 1123 1124 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 1125 return (ENXIO); 1126 1127 device_set_desc(dev, "Tegra XUSB phy"); 1128 return (BUS_PROBE_DEFAULT); 1129 } 1130 1131 static int 1132 xusbpadctl_detach(device_t dev) 1133 { 1134 1135 /* This device is always present. */ 1136 return (EBUSY); 1137 } 1138 1139 static int 1140 xusbpadctl_attach(device_t dev) 1141 { 1142 struct padctl_softc * sc; 1143 int i, rid, rv; 1144 struct padctl_port *port; 1145 phandle_t node; 1146 1147 sc = device_get_softc(dev); 1148 sc->dev = dev; 1149 node = ofw_bus_get_node(dev); 1150 1151 rid = 0; 1152 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1153 RF_ACTIVE); 1154 if (sc->mem_res == NULL) { 1155 device_printf(dev, "Cannot allocate memory resources\n"); 1156 return (ENXIO); 1157 } 1158 1159 rv = hwreset_get_by_ofw_name(dev, 0, "padctl", &sc->rst); 1160 if (rv != 0) { 1161 device_printf(dev, "Cannot get 'padctl' reset: %d\n", rv); 1162 return (rv); 1163 } 1164 rv = hwreset_deassert(sc->rst); 1165 if (rv != 0) { 1166 device_printf(dev, "Cannot unreset 'padctl' reset: %d\n", rv); 1167 return (rv); 1168 } 1169 1170 load_calibration(sc); 1171 1172 rv = parse_fdt(sc, node); 1173 if (rv != 0) { 1174 device_printf(dev, "Cannot parse fdt configuration: %d\n", rv); 1175 return (rv); 1176 } 1177 for (i = 0; i < nitems(ports_tbl); i++) { 1178 port = ports_tbl + i; 1179 if (!port->enabled) 1180 continue; 1181 if (port->init == NULL) 1182 continue; 1183 rv = port->init(sc, port); 1184 if (rv != 0) { 1185 device_printf(dev, "Cannot init port '%s'\n", 1186 port->name); 1187 return (rv); 1188 } 1189 } 1190 return (0); 1191 } 1192 1193 static device_method_t tegra_xusbpadctl_methods[] = { 1194 /* Device interface */ 1195 DEVMETHOD(device_probe, xusbpadctl_probe), 1196 DEVMETHOD(device_attach, xusbpadctl_attach), 1197 DEVMETHOD(device_detach, xusbpadctl_detach), 1198 1199 DEVMETHOD_END 1200 }; 1201 1202 static DEFINE_CLASS_0(xusbpadctl, tegra_xusbpadctl_driver, 1203 tegra_xusbpadctl_methods, sizeof(struct padctl_softc)); 1204 EARLY_DRIVER_MODULE(tegra_xusbpadctl, simplebus, tegra_xusbpadctl_driver, 1205 NULL, NULL, 73);
Cache object: 1cf78ce86f39a377c0bbb43546ef27aa
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