tegra_gpio.c

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    1 /*-
    2  * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD$");
   29 
   30 /*
   31  * Tegra GPIO driver.
   32  */
   33 #include "opt_platform.h"
   34 #include <sys/param.h>
   35 #include <sys/systm.h>
   36 #include <sys/bus.h>
   37 #include <sys/gpio.h>
   38 #include <sys/kernel.h>
   39 #include <sys/proc.h>
   40 #include <sys/rman.h>
   41 #include <sys/lock.h>
   42 #include <sys/module.h>
   43 #include <sys/mutex.h>
   44 
   45 #include <machine/bus.h>
   46 #include <machine/intr.h>
   47 #include <machine/resource.h>
   48 
   49 #include <dev/gpio/gpiobusvar.h>
   50 #include <dev/ofw/openfirm.h>
   51 #include <dev/ofw/ofw_bus.h>
   52 #include <dev/ofw/ofw_bus_subr.h>
   53 
   54 #include "pic_if.h"
   55 
   56 #define GPIO_LOCK(_sc)          mtx_lock(&(_sc)->mtx)
   57 #define GPIO_UNLOCK(_sc)        mtx_unlock(&(_sc)->mtx)
   58 #define GPIO_LOCK_INIT(_sc)     mtx_init(&_sc->mtx,                     \
   59             device_get_nameunit(_sc->dev), "tegra_gpio", MTX_DEF)
   60 #define GPIO_LOCK_DESTROY(_sc)  mtx_destroy(&_sc->mtx);
   61 #define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED);
   62 #define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED);
   63 
   64 #define WR4(_sc, _r, _v)        bus_write_4((_sc)->mem_res, (_r), (_v))
   65 #define RD4(_sc, _r)            bus_read_4((_sc)->mem_res, (_r))
   66 
   67 #define GPIO_BANK_OFFS          0x100   /* Bank offset */
   68 #define GPIO_NUM_BANKS          8       /* Total number per bank */
   69 #define GPIO_REGS_IN_BANK       4       /* Total registers in bank */
   70 #define GPIO_PINS_IN_REG        8       /* Total pin in register */
   71 
   72 #define GPIO_BANKNUM(n)         ((n) / (GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG))
   73 #define GPIO_PORTNUM(n)         (((n) / GPIO_PINS_IN_REG) % GPIO_REGS_IN_BANK)
   74 #define GPIO_BIT(n)             ((n) % GPIO_PINS_IN_REG)
   75 
   76 #define GPIO_REGNUM(n)          (GPIO_BANKNUM(n) * GPIO_BANK_OFFS + \
   77                                     GPIO_PORTNUM(n) * 4)
   78 
   79 #define NGPIO   ((GPIO_NUM_BANKS * GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG) - 8)
   80 
   81 /* Register offsets */
   82 #define GPIO_CNF                0x00
   83 #define GPIO_OE                 0x10
   84 #define GPIO_OUT                0x20
   85 #define GPIO_IN                 0x30
   86 #define GPIO_INT_STA            0x40
   87 #define GPIO_INT_ENB            0x50
   88 #define GPIO_INT_LVL            0x60
   89 #define  GPIO_INT_LVL_DELTA             (1 << 16)
   90 #define  GPIO_INT_LVL_EDGE              (1 << 8)
   91 #define  GPIO_INT_LVL_HIGH              (1 << 0)
   92 #define  GPIO_INT_LVL_MASK              (GPIO_INT_LVL_DELTA |           \
   93                                          GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH)
   94 #define GPIO_INT_CLR            0x70
   95 #define GPIO_MSK_CNF            0x80
   96 #define GPIO_MSK_OE             0x90
   97 #define GPIO_MSK_OUT            0xA0
   98 #define GPIO_MSK_INT_STA        0xC0
   99 #define GPIO_MSK_INT_ENB        0xD0
  100 #define GPIO_MSK_INT_LVL        0xE0
  101 
  102 char *tegra_gpio_port_names[] = {
  103          "A",  "B",  "C",  "D", /* Bank 0 */
  104          "E",  "F",  "G",  "H", /* Bank 1 */
  105          "I",  "J",  "K",  "L", /* Bank 2 */
  106          "M",  "N",  "O",  "P", /* Bank 3 */
  107          "Q",  "R",  "S",  "T", /* Bank 4 */
  108          "U",  "V",  "W",  "X", /* Bank 5 */
  109          "Y",  "Z", "AA", "BB", /* Bank 6 */
  110         "CC", "DD", "EE"        /* Bank 7 */
  111 };
  112 
  113 struct tegra_gpio_irqsrc {
  114         struct intr_irqsrc      isrc;
  115         u_int                   irq;
  116         uint32_t                cfgreg;
  117 };
  118 
  119 struct tegra_gpio_softc;
  120 struct tegra_gpio_irq_cookie {
  121         struct tegra_gpio_softc *sc;
  122         int                     bank_num;
  123 };
  124 
  125 struct tegra_gpio_softc {
  126         device_t                dev;
  127         device_t                busdev;
  128         struct mtx              mtx;
  129         struct resource         *mem_res;
  130         struct resource         *irq_res[GPIO_NUM_BANKS];
  131         void                    *irq_ih[GPIO_NUM_BANKS];
  132         struct tegra_gpio_irq_cookie irq_cookies[GPIO_NUM_BANKS];
  133         int                     gpio_npins;
  134         struct gpio_pin         gpio_pins[NGPIO];
  135         struct tegra_gpio_irqsrc *isrcs;
  136 };
  137 
  138 static struct ofw_compat_data compat_data[] = {
  139         {"nvidia,tegra124-gpio", 1},
  140         {"nvidia,tegra210-gpio", 1},
  141         {NULL,                  0}
  142 };
  143 
  144 /* --------------------------------------------------------------------------
  145  *
  146  * GPIO
  147  *
  148  */
  149 static inline void
  150 gpio_write_masked(struct tegra_gpio_softc *sc, bus_size_t reg,
  151     struct gpio_pin *pin, uint32_t val)
  152 {
  153         uint32_t tmp;
  154         int bit;
  155 
  156         bit = GPIO_BIT(pin->gp_pin);
  157         tmp = 0x100 << bit;             /* mask */
  158         tmp |= (val & 1) << bit;        /* value */
  159         bus_write_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin), tmp);
  160 }
  161 
  162 static inline uint32_t
  163 gpio_read(struct tegra_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin)
  164 {
  165         int bit;
  166         uint32_t val;
  167 
  168         bit = GPIO_BIT(pin->gp_pin);
  169         val = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin));
  170         return (val >> bit) & 1;
  171 }
  172 
  173 static void
  174 tegra_gpio_pin_configure(struct tegra_gpio_softc *sc, struct gpio_pin *pin,
  175     unsigned int flags)
  176 {
  177 
  178         if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0)
  179                 return;
  180 
  181         /* Manage input/output */
  182         pin->gp_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
  183         if (flags & GPIO_PIN_OUTPUT) {
  184                 pin->gp_flags |= GPIO_PIN_OUTPUT;
  185                 gpio_write_masked(sc, GPIO_MSK_OE, pin, 1);
  186         } else {
  187                 pin->gp_flags |= GPIO_PIN_INPUT;
  188                 gpio_write_masked(sc, GPIO_MSK_OE, pin, 0);
  189         }
  190 }
  191 
  192 static device_t
  193 tegra_gpio_get_bus(device_t dev)
  194 {
  195         struct tegra_gpio_softc *sc;
  196 
  197         sc = device_get_softc(dev);
  198         return (sc->busdev);
  199 }
  200 
  201 static int
  202 tegra_gpio_pin_max(device_t dev, int *maxpin)
  203 {
  204 
  205         *maxpin = NGPIO - 1;
  206         return (0);
  207 }
  208 
  209 static int
  210 tegra_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
  211 {
  212         struct tegra_gpio_softc *sc;
  213 
  214         sc = device_get_softc(dev);
  215         if (pin >= sc->gpio_npins)
  216                 return (EINVAL);
  217 
  218         GPIO_LOCK(sc);
  219         *caps = sc->gpio_pins[pin].gp_caps;
  220         GPIO_UNLOCK(sc);
  221 
  222         return (0);
  223 }
  224 
  225 static int
  226 tegra_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
  227 {
  228         struct tegra_gpio_softc *sc;
  229         int cnf;
  230 
  231         sc = device_get_softc(dev);
  232         if (pin >= sc->gpio_npins)
  233                 return (EINVAL);
  234 
  235         GPIO_LOCK(sc);
  236         cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]);
  237         if (cnf == 0) {
  238                 GPIO_UNLOCK(sc);
  239                 return (ENXIO);
  240         }
  241         *flags = sc->gpio_pins[pin].gp_flags;
  242         GPIO_UNLOCK(sc);
  243 
  244         return (0);
  245 }
  246 
  247 static int
  248 tegra_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
  249 {
  250         struct tegra_gpio_softc *sc;
  251 
  252         sc = device_get_softc(dev);
  253         if (pin >= sc->gpio_npins)
  254                 return (EINVAL);
  255 
  256         GPIO_LOCK(sc);
  257         memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME);
  258         GPIO_UNLOCK(sc);
  259 
  260         return (0);
  261 }
  262 
  263 static int
  264 tegra_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
  265 {
  266         struct tegra_gpio_softc *sc;
  267         int cnf;
  268 
  269         sc = device_get_softc(dev);
  270         if (pin >= sc->gpio_npins)
  271                 return (EINVAL);
  272 
  273         GPIO_LOCK(sc);
  274         cnf = gpio_read(sc, GPIO_CNF,  &sc->gpio_pins[pin]);
  275         if (cnf == 0) {
  276                 /* XXX - allow this for while ....
  277                 GPIO_UNLOCK(sc);
  278                 return (ENXIO);
  279                 */
  280                 gpio_write_masked(sc, GPIO_MSK_CNF,  &sc->gpio_pins[pin], 1);
  281         }
  282         tegra_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags);
  283         GPIO_UNLOCK(sc);
  284 
  285         return (0);
  286 }
  287 
  288 static int
  289 tegra_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
  290 {
  291         struct tegra_gpio_softc *sc;
  292 
  293         sc = device_get_softc(dev);
  294         if (pin >= sc->gpio_npins)
  295                 return (EINVAL);
  296         GPIO_LOCK(sc);
  297         gpio_write_masked(sc, GPIO_MSK_OUT, &sc->gpio_pins[pin], value);
  298         GPIO_UNLOCK(sc);
  299 
  300         return (0);
  301 }
  302 
  303 static int
  304 tegra_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
  305 {
  306         struct tegra_gpio_softc *sc;
  307 
  308         sc = device_get_softc(dev);
  309         if (pin >= sc->gpio_npins)
  310                 return (EINVAL);
  311 
  312         GPIO_LOCK(sc);
  313         *val = gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]);
  314         GPIO_UNLOCK(sc);
  315 
  316         return (0);
  317 }
  318 
  319 static int
  320 tegra_gpio_pin_toggle(device_t dev, uint32_t pin)
  321 {
  322         struct tegra_gpio_softc *sc;
  323 
  324         sc = device_get_softc(dev);
  325         if (pin >= sc->gpio_npins)
  326                 return (EINVAL);
  327 
  328         GPIO_LOCK(sc);
  329         gpio_write_masked(sc, GPIO_MSK_OE, &sc->gpio_pins[pin],
  330              gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]) ^ 1);
  331         GPIO_UNLOCK(sc);
  332 
  333         return (0);
  334 }
  335 
  336 /* --------------------------------------------------------------------------
  337  *
  338  * Interrupts
  339  *
  340  */
  341 static inline void
  342 intr_write_masked(struct tegra_gpio_softc *sc, bus_addr_t reg,
  343     struct tegra_gpio_irqsrc *tgi, uint32_t val)
  344 {
  345         uint32_t tmp;
  346         int bit;
  347 
  348         bit = GPIO_BIT(tgi->irq);
  349         tmp = 0x100 << bit;             /* mask */
  350         tmp |= (val & 1) << bit;        /* value */
  351         bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp);
  352 }
  353 
  354 static inline void
  355 intr_write_modify(struct tegra_gpio_softc *sc, bus_addr_t reg,
  356     struct tegra_gpio_irqsrc *tgi, uint32_t val, uint32_t mask)
  357 {
  358         uint32_t tmp;
  359         int bit;
  360 
  361         bit = GPIO_BIT(tgi->irq);
  362         GPIO_LOCK(sc);
  363         tmp = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq));
  364         tmp &= ~(mask << bit);
  365         tmp |= val << bit;
  366         bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp);
  367         GPIO_UNLOCK(sc);
  368 }
  369 
  370 static inline void
  371 tegra_gpio_isrc_mask(struct tegra_gpio_softc *sc,
  372      struct tegra_gpio_irqsrc *tgi, uint32_t val)
  373 {
  374 
  375         intr_write_masked(sc, GPIO_MSK_INT_ENB, tgi, val);
  376 }
  377 
  378 static inline void
  379 tegra_gpio_isrc_eoi(struct tegra_gpio_softc *sc,
  380      struct tegra_gpio_irqsrc *tgi)
  381 {
  382 
  383         intr_write_masked(sc, GPIO_INT_CLR, tgi, 1);
  384 }
  385 
  386 static inline bool
  387 tegra_gpio_isrc_is_level(struct tegra_gpio_irqsrc *tgi)
  388 {
  389 
  390         return (tgi->cfgreg & GPIO_INT_LVL_EDGE);
  391 }
  392 
  393 static int
  394 tegra_gpio_intr(void *arg)
  395 {
  396         u_int irq, i, j, val, basepin;
  397         struct tegra_gpio_softc *sc;
  398         struct trapframe *tf;
  399         struct tegra_gpio_irqsrc *tgi;
  400         struct tegra_gpio_irq_cookie *cookie;
  401 
  402         cookie = (struct tegra_gpio_irq_cookie *)arg;
  403         sc = cookie->sc;
  404         tf = curthread->td_intr_frame;
  405 
  406         for (i = 0; i < GPIO_REGS_IN_BANK; i++) {
  407                 basepin  = cookie->bank_num * GPIO_REGS_IN_BANK *
  408                     GPIO_PINS_IN_REG + i * GPIO_PINS_IN_REG;
  409 
  410                 val = bus_read_4(sc->mem_res, GPIO_INT_STA +
  411                     GPIO_REGNUM(basepin));
  412                 val &= bus_read_4(sc->mem_res, GPIO_INT_ENB +
  413                     GPIO_REGNUM(basepin));
  414                 /* Interrupt handling */
  415                 for (j = 0; j < GPIO_PINS_IN_REG; j++) {
  416                         if ((val & (1 << j)) == 0)
  417                                 continue;
  418                         irq = basepin + j;
  419                         tgi = &sc->isrcs[irq];
  420                         if (!tegra_gpio_isrc_is_level(tgi))
  421                                 tegra_gpio_isrc_eoi(sc, tgi);
  422                         if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) {
  423                                 tegra_gpio_isrc_mask(sc, tgi, 0);
  424                                 if (tegra_gpio_isrc_is_level(tgi))
  425                                         tegra_gpio_isrc_eoi(sc, tgi);
  426                                 device_printf(sc->dev,
  427                                     "Stray irq %u disabled\n", irq);
  428                         }
  429                 }
  430         }
  431 
  432         return (FILTER_HANDLED);
  433 }
  434 
  435 static int
  436 tegra_gpio_pic_attach(struct tegra_gpio_softc *sc)
  437 {
  438         int error;
  439         uint32_t irq;
  440         const char *name;
  441 
  442         sc->isrcs = malloc(sizeof(*sc->isrcs) * sc->gpio_npins, M_DEVBUF,
  443             M_WAITOK | M_ZERO);
  444 
  445         name = device_get_nameunit(sc->dev);
  446         for (irq = 0; irq < sc->gpio_npins; irq++) {
  447                 sc->isrcs[irq].irq = irq;
  448                 sc->isrcs[irq].cfgreg = 0;
  449                 error = intr_isrc_register(&sc->isrcs[irq].isrc,
  450                     sc->dev, 0, "%s,%u", name, irq);
  451                 if (error != 0)
  452                         return (error); /* XXX deregister ISRCs */
  453         }
  454         if (intr_pic_register(sc->dev,
  455             OF_xref_from_node(ofw_bus_get_node(sc->dev))) == NULL)
  456                 return (ENXIO);
  457 
  458         return (0);
  459 }
  460 
  461 static int
  462 tegra_gpio_pic_detach(struct tegra_gpio_softc *sc)
  463 {
  464 
  465         /*
  466          *  There has not been established any procedure yet
  467          *  how to detach PIC from living system correctly.
  468          */
  469         device_printf(sc->dev, "%s: not implemented yet\n", __func__);
  470         return (EBUSY);
  471 }
  472 
  473 static void
  474 tegra_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
  475 {
  476         struct tegra_gpio_softc *sc;
  477         struct tegra_gpio_irqsrc *tgi;
  478 
  479         sc = device_get_softc(dev);
  480         tgi = (struct tegra_gpio_irqsrc *)isrc;
  481         tegra_gpio_isrc_mask(sc, tgi, 0);
  482 }
  483 
  484 static void
  485 tegra_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
  486 {
  487         struct tegra_gpio_softc *sc;
  488         struct tegra_gpio_irqsrc *tgi;
  489 
  490         sc = device_get_softc(dev);
  491         tgi = (struct tegra_gpio_irqsrc *)isrc;
  492         tegra_gpio_isrc_mask(sc, tgi, 1);
  493 }
  494 
  495 static int
  496 tegra_gpio_pic_map_fdt(struct tegra_gpio_softc *sc, u_int ncells,
  497     pcell_t *cells, u_int *irqp, uint32_t *regp)
  498 {
  499         uint32_t reg;
  500 
  501         /*
  502          * The first cell is the interrupt number.
  503          * The second cell is used to specify flags:
  504          *      bits[3:0] trigger type and level flags:
  505          *              1 = low-to-high edge triggered.
  506          *              2 = high-to-low edge triggered.
  507          *              4 = active high level-sensitive.
  508          *              8 = active low level-sensitive.
  509          */
  510         if (ncells != 2 || cells[0] >= sc->gpio_npins)
  511                 return (EINVAL);
  512 
  513         /*
  514          * All interrupt types could be set for an interrupt at one moment.
  515          * At least, the combination of 'low-to-high' and 'high-to-low' edge
  516          * triggered interrupt types can make a sense.
  517          */
  518         if (cells[1] == 1)
  519                 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH;
  520         else if (cells[1] == 2)
  521                 reg = GPIO_INT_LVL_EDGE;
  522         else if (cells[1] == 3)
  523                 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_DELTA;
  524         else if (cells[1] == 4)
  525                 reg = GPIO_INT_LVL_HIGH;
  526         else if (cells[1] == 8)
  527                 reg = 0;
  528         else
  529                 return (EINVAL);
  530 
  531         *irqp = cells[0];
  532         if (regp != NULL)
  533                 *regp = reg;
  534         return (0);
  535 }
  536 
  537 static int
  538 tegra_gpio_pic_map_gpio(struct tegra_gpio_softc *sc, u_int gpio_pin_num,
  539     u_int gpio_pin_flags, u_int intr_mode, u_int *irqp, uint32_t *regp)
  540 {
  541 
  542         uint32_t reg;
  543 
  544         if (gpio_pin_num >= sc->gpio_npins)
  545                 return (EINVAL);
  546         switch (intr_mode) {
  547         case GPIO_INTR_CONFORM:
  548         case GPIO_INTR_LEVEL_LOW:
  549                 reg = 0;
  550                 break;
  551         case GPIO_INTR_LEVEL_HIGH:
  552                 reg = GPIO_INT_LVL_HIGH;
  553                 break;
  554         case GPIO_INTR_EDGE_RISING:
  555                 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH;
  556                 break;
  557         case GPIO_INTR_EDGE_FALLING:
  558                 reg = GPIO_INT_LVL_EDGE;
  559                 break;
  560         case GPIO_INTR_EDGE_BOTH:
  561                 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_DELTA;
  562                 break;
  563         default:
  564                 return (EINVAL);
  565         }
  566         *irqp = gpio_pin_num;
  567         if (regp != NULL)
  568                 *regp = reg;
  569         return (0);
  570 }
  571 
  572 static int
  573 tegra_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
  574     struct intr_irqsrc **isrcp)
  575 {
  576         int rv;
  577         u_int irq;
  578         struct tegra_gpio_softc *sc;
  579 
  580         sc = device_get_softc(dev);
  581 
  582         if (data->type == INTR_MAP_DATA_FDT) {
  583                 struct intr_map_data_fdt *daf;
  584 
  585                 daf = (struct intr_map_data_fdt *)data;
  586                 rv = tegra_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq,
  587                     NULL);
  588         } else if (data->type == INTR_MAP_DATA_GPIO) {
  589                 struct intr_map_data_gpio *dag;
  590 
  591                 dag = (struct intr_map_data_gpio *)data;
  592                 rv = tegra_gpio_pic_map_gpio(sc, dag->gpio_pin_num,
  593                    dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, NULL);
  594         } else
  595                 return (ENOTSUP);
  596 
  597         if (rv == 0)
  598                 *isrcp = &sc->isrcs[irq].isrc;
  599         return (rv);
  600 }
  601 
  602 static void
  603 tegra_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
  604 {
  605         struct tegra_gpio_softc *sc;
  606         struct tegra_gpio_irqsrc *tgi;
  607 
  608         sc = device_get_softc(dev);
  609         tgi = (struct tegra_gpio_irqsrc *)isrc;
  610         if (tegra_gpio_isrc_is_level(tgi))
  611                 tegra_gpio_isrc_eoi(sc, tgi);
  612 }
  613 
  614 static void
  615 tegra_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
  616 {
  617         struct tegra_gpio_softc *sc;
  618         struct tegra_gpio_irqsrc *tgi;
  619 
  620         sc = device_get_softc(dev);
  621         tgi = (struct tegra_gpio_irqsrc *)isrc;
  622         tegra_gpio_isrc_mask(sc, tgi, 1);
  623 }
  624 
  625 static void
  626 tegra_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
  627 {
  628         struct tegra_gpio_softc *sc;
  629         struct tegra_gpio_irqsrc *tgi;
  630 
  631         sc = device_get_softc(dev);
  632         tgi = (struct tegra_gpio_irqsrc *)isrc;
  633 
  634         tegra_gpio_isrc_mask(sc, tgi, 0);
  635         if (tegra_gpio_isrc_is_level(tgi))
  636                 tegra_gpio_isrc_eoi(sc, tgi);
  637 }
  638 
  639 static int
  640 tegra_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
  641     struct resource *res, struct intr_map_data *data)
  642 {
  643         u_int irq;
  644         uint32_t cfgreg;
  645         int rv;
  646         struct tegra_gpio_softc *sc;
  647         struct tegra_gpio_irqsrc *tgi;
  648 
  649         sc = device_get_softc(dev);
  650         tgi = (struct tegra_gpio_irqsrc *)isrc;
  651 
  652         if (data == NULL)
  653                 return (ENOTSUP);
  654 
  655         /* Get and check config for an interrupt. */
  656         if (data->type == INTR_MAP_DATA_FDT) {
  657                 struct intr_map_data_fdt *daf;
  658 
  659                 daf = (struct intr_map_data_fdt *)data;
  660                 rv = tegra_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq,
  661                     &cfgreg);
  662         } else if (data->type == INTR_MAP_DATA_GPIO) {
  663                 struct intr_map_data_gpio *dag;
  664 
  665                 dag = (struct intr_map_data_gpio *)data;
  666                 rv = tegra_gpio_pic_map_gpio(sc, dag->gpio_pin_num,
  667                    dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, &cfgreg);
  668         } else
  669                 return (ENOTSUP);
  670         if (rv != 0)
  671                 return (EINVAL);
  672 
  673         /*
  674          * If this is a setup for another handler,
  675          * only check that its configuration match.
  676          */
  677         if (isrc->isrc_handlers != 0)
  678                 return (tgi->cfgreg == cfgreg ? 0 : EINVAL);
  679 
  680         tgi->cfgreg = cfgreg;
  681         intr_write_modify(sc, GPIO_INT_LVL, tgi, cfgreg, GPIO_INT_LVL_MASK);
  682         tegra_gpio_pic_enable_intr(dev, isrc);
  683 
  684         return (0);
  685 }
  686 
  687 static int
  688 tegra_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
  689     struct resource *res, struct intr_map_data *data)
  690 {
  691         struct tegra_gpio_softc *sc;
  692         struct tegra_gpio_irqsrc *tgi;
  693 
  694         sc = device_get_softc(dev);
  695         tgi = (struct tegra_gpio_irqsrc *)isrc;
  696 
  697         if (isrc->isrc_handlers == 0)
  698                 tegra_gpio_isrc_mask(sc, tgi, 0);
  699         return (0);
  700 }
  701 
  702 static int
  703 tegra_gpio_probe(device_t dev)
  704 {
  705 
  706         if (!ofw_bus_status_okay(dev))
  707                 return (ENXIO);
  708         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
  709                 device_set_desc(dev, "Tegra GPIO Controller");
  710                 return (BUS_PROBE_DEFAULT);
  711         }
  712 
  713         return (ENXIO);
  714 }
  715 
  716 /* --------------------------------------------------------------------------
  717  *
  718  * Bus
  719  *
  720  */
  721 static int
  722 tegra_gpio_detach(device_t dev)
  723 {
  724         struct tegra_gpio_softc *sc;
  725         int i;
  726 
  727         sc = device_get_softc(dev);
  728 
  729         KASSERT(mtx_initialized(&sc->mtx), ("gpio mutex not initialized"));
  730 
  731         for (i = 0; i < GPIO_NUM_BANKS; i++) {
  732                 if (sc->irq_ih[i] != NULL)
  733                         bus_teardown_intr(dev, sc->irq_res[i], sc->irq_ih[i]);
  734         }
  735 
  736         if (sc->isrcs != NULL)
  737                 tegra_gpio_pic_detach(sc);
  738 
  739         gpiobus_detach_bus(dev);
  740 
  741         for (i = 0; i < GPIO_NUM_BANKS; i++) {
  742                 if (sc->irq_res[i] != NULL)
  743                         bus_release_resource(dev, SYS_RES_IRQ, 0,
  744                             sc->irq_res[i]);
  745         }
  746         if (sc->mem_res != NULL)
  747                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
  748         GPIO_LOCK_DESTROY(sc);
  749 
  750         return(0);
  751 }
  752 
  753 static int
  754 tegra_gpio_attach(device_t dev)
  755 {
  756         struct tegra_gpio_softc *sc;
  757         int i, rid;
  758 
  759         sc = device_get_softc(dev);
  760         sc->dev = dev;
  761         GPIO_LOCK_INIT(sc);
  762 
  763         /* Allocate bus_space resources. */
  764         rid = 0;
  765         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
  766             RF_ACTIVE);
  767         if (sc->mem_res == NULL) {
  768                 device_printf(dev, "Cannot allocate memory resources\n");
  769                 tegra_gpio_detach(dev);
  770                 return (ENXIO);
  771         }
  772 
  773         sc->gpio_npins = NGPIO;
  774         for (i = 0; i < sc->gpio_npins; i++) {
  775                 sc->gpio_pins[i].gp_pin = i;
  776                 sc->gpio_pins[i].gp_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
  777                     GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | 
  778                     GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING |
  779                     GPIO_INTR_EDGE_BOTH;
  780                 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, "gpio_%s.%d",
  781                     tegra_gpio_port_names[ i / GPIO_PINS_IN_REG],
  782                     i % GPIO_PINS_IN_REG);
  783                 sc->gpio_pins[i].gp_flags =
  784                     gpio_read(sc, GPIO_OE, &sc->gpio_pins[i]) != 0 ?
  785                     GPIO_PIN_OUTPUT : GPIO_PIN_INPUT;
  786         }
  787 
  788         /* Init interrupt related registes. */
  789         for (i = 0; i < sc->gpio_npins; i += GPIO_PINS_IN_REG) {
  790                 bus_write_4(sc->mem_res, GPIO_INT_ENB + GPIO_REGNUM(i), 0);
  791                 bus_write_4(sc->mem_res, GPIO_INT_STA + GPIO_REGNUM(i), 0xFF);
  792                 bus_write_4(sc->mem_res, GPIO_INT_CLR + GPIO_REGNUM(i), 0xFF);
  793         }
  794 
  795         /* Allocate interrupts. */
  796         for (i = 0; i < GPIO_NUM_BANKS; i++) {
  797                 sc->irq_cookies[i].sc = sc;
  798                 sc->irq_cookies[i].bank_num = i;
  799                 rid = i;
  800                 sc->irq_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ,
  801                     &rid, RF_ACTIVE);
  802                 if (sc->irq_res[i] == NULL) {
  803                         device_printf(dev, "Cannot allocate IRQ resources\n");
  804                         tegra_gpio_detach(dev);
  805                         return (ENXIO);
  806                 }
  807                 if ((bus_setup_intr(dev, sc->irq_res[i],
  808                     INTR_TYPE_MISC | INTR_MPSAFE, tegra_gpio_intr, NULL,
  809                     &sc->irq_cookies[i], &sc->irq_ih[i]))) {
  810                         device_printf(dev,
  811                             "WARNING: unable to register interrupt handler\n");
  812                         tegra_gpio_detach(dev);
  813                         return (ENXIO);
  814                 }
  815         }
  816 
  817         if (tegra_gpio_pic_attach(sc) != 0) {
  818                 device_printf(dev, "WARNING: unable to attach PIC\n");
  819                 tegra_gpio_detach(dev);
  820                 return (ENXIO);
  821         }
  822 
  823         sc->busdev = gpiobus_attach_bus(dev);
  824         if (sc->busdev == NULL) {
  825                 tegra_gpio_detach(dev);
  826                 return (ENXIO);
  827         }
  828 
  829         return (bus_generic_attach(dev));
  830 }
  831 
  832 static int
  833 tegra_map_gpios(device_t dev, phandle_t pdev, phandle_t gparent,
  834     int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags)
  835 {
  836 
  837         if (gcells != 2)
  838                 return (ERANGE);
  839         *pin = gpios[0];
  840         *flags= gpios[1];
  841         return (0);
  842 }
  843 
  844 static phandle_t
  845 tegra_gpio_get_node(device_t bus, device_t dev)
  846 {
  847 
  848         /* We only have one child, the GPIO bus, which needs our own node. */
  849         return (ofw_bus_get_node(bus));
  850 }
  851 
  852 static device_method_t tegra_gpio_methods[] = {
  853         DEVMETHOD(device_probe,         tegra_gpio_probe),
  854         DEVMETHOD(device_attach,        tegra_gpio_attach),
  855         DEVMETHOD(device_detach,        tegra_gpio_detach),
  856 
  857         /* Interrupt controller interface */
  858         DEVMETHOD(pic_disable_intr,     tegra_gpio_pic_disable_intr),
  859         DEVMETHOD(pic_enable_intr,      tegra_gpio_pic_enable_intr),
  860         DEVMETHOD(pic_map_intr,         tegra_gpio_pic_map_intr),
  861         DEVMETHOD(pic_setup_intr,       tegra_gpio_pic_setup_intr),
  862         DEVMETHOD(pic_teardown_intr,    tegra_gpio_pic_teardown_intr),
  863         DEVMETHOD(pic_post_filter,      tegra_gpio_pic_post_filter),
  864         DEVMETHOD(pic_post_ithread,     tegra_gpio_pic_post_ithread),
  865         DEVMETHOD(pic_pre_ithread,      tegra_gpio_pic_pre_ithread),
  866 
  867         /* GPIO protocol */
  868         DEVMETHOD(gpio_get_bus,         tegra_gpio_get_bus),
  869         DEVMETHOD(gpio_pin_max,         tegra_gpio_pin_max),
  870         DEVMETHOD(gpio_pin_getname,     tegra_gpio_pin_getname),
  871         DEVMETHOD(gpio_pin_getflags,    tegra_gpio_pin_getflags),
  872         DEVMETHOD(gpio_pin_getcaps,     tegra_gpio_pin_getcaps),
  873         DEVMETHOD(gpio_pin_setflags,    tegra_gpio_pin_setflags),
  874         DEVMETHOD(gpio_pin_get,         tegra_gpio_pin_get),
  875         DEVMETHOD(gpio_pin_set,         tegra_gpio_pin_set),
  876         DEVMETHOD(gpio_pin_toggle,      tegra_gpio_pin_toggle),
  877         DEVMETHOD(gpio_map_gpios,       tegra_map_gpios),
  878 
  879         /* ofw_bus interface */
  880         DEVMETHOD(ofw_bus_get_node,     tegra_gpio_get_node),
  881 
  882         DEVMETHOD_END
  883 };
  884 
  885 static devclass_t tegra_gpio_devclass;
  886 static DEFINE_CLASS_0(gpio, tegra_gpio_driver, tegra_gpio_methods,
  887     sizeof(struct tegra_gpio_softc));
  888 EARLY_DRIVER_MODULE(tegra_gpio, simplebus, tegra_gpio_driver,
  889     tegra_gpio_devclass, NULL, NULL, 70);
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FreeBSD/Linux Kernel Cross Reference sys/arm/nvidia/tegra_gpio.c

FreeBSD/Linux Kernel Cross Reference
sys/arm/nvidia/tegra_gpio.c
