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sys/arm/nvidia/tegra_pcie.c
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1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Nvidia Integrated PCI/PCI-Express controller driver. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/devmap.h> 38 #include <sys/proc.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 45 #include <machine/intr.h> 46 47 #include <vm/vm.h> 48 #include <vm/vm_extern.h> 49 #include <vm/vm_kern.h> 50 #include <vm/pmap.h> 51 52 #include <dev/extres/clk/clk.h> 53 #include <dev/extres/hwreset/hwreset.h> 54 #include <dev/extres/phy/phy.h> 55 #include <dev/extres/regulator/regulator.h> 56 #include <dev/ofw/ofw_bus.h> 57 #include <dev/ofw/ofw_bus_subr.h> 58 #include <dev/ofw/ofw_pci.h> 59 #include <dev/ofw/ofwpci.h> 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcib_private.h> 63 64 #include <machine/resource.h> 65 #include <machine/bus.h> 66 67 #include <arm/nvidia/tegra_pmc.h> 68 69 #include "ofw_bus_if.h" 70 #include "msi_if.h" 71 #include "pcib_if.h" 72 #include "pic_if.h" 73 74 #define AFI_AXI_BAR0_SZ 0x000 75 #define AFI_AXI_BAR1_SZ 0x004 76 #define AFI_AXI_BAR2_SZ 0x008 77 #define AFI_AXI_BAR3_SZ 0x00c 78 #define AFI_AXI_BAR4_SZ 0x010 79 #define AFI_AXI_BAR5_SZ 0x014 80 #define AFI_AXI_BAR0_START 0x018 81 #define AFI_AXI_BAR1_START 0x01c 82 #define AFI_AXI_BAR2_START 0x020 83 #define AFI_AXI_BAR3_START 0x024 84 #define AFI_AXI_BAR4_START 0x028 85 #define AFI_AXI_BAR5_START 0x02c 86 #define AFI_FPCI_BAR0 0x030 87 #define AFI_FPCI_BAR1 0x034 88 #define AFI_FPCI_BAR2 0x038 89 #define AFI_FPCI_BAR3 0x03c 90 #define AFI_FPCI_BAR4 0x040 91 #define AFI_FPCI_BAR5 0x044 92 #define AFI_MSI_BAR_SZ 0x060 93 #define AFI_MSI_FPCI_BAR_ST 0x064 94 #define AFI_MSI_AXI_BAR_ST 0x068 95 #define AFI_MSI_VEC(x) (0x06c + 4 * (x)) 96 #define AFI_MSI_EN_VEC(x) (0x08c + 4 * (x)) 97 #define AFI_MSI_INTR_IN_REG 32 98 #define AFI_MSI_REGS 8 99 100 #define AFI_CONFIGURATION 0x0ac 101 #define AFI_CONFIGURATION_EN_FPCI (1 << 0) 102 103 #define AFI_FPCI_ERROR_MASKS 0x0b0 104 #define AFI_INTR_MASK 0x0b4 105 #define AFI_INTR_MASK_MSI_MASK (1 << 8) 106 #define AFI_INTR_MASK_INT_MASK (1 << 0) 107 108 #define AFI_INTR_CODE 0x0b8 109 #define AFI_INTR_CODE_MASK 0xf 110 #define AFI_INTR_CODE_INT_CODE_INI_SLVERR 1 111 #define AFI_INTR_CODE_INT_CODE_INI_DECERR 2 112 #define AFI_INTR_CODE_INT_CODE_TGT_SLVERR 3 113 #define AFI_INTR_CODE_INT_CODE_TGT_DECERR 4 114 #define AFI_INTR_CODE_INT_CODE_TGT_WRERR 5 115 #define AFI_INTR_CODE_INT_CODE_SM_MSG 6 116 #define AFI_INTR_CODE_INT_CODE_DFPCI_DECERR 7 117 #define AFI_INTR_CODE_INT_CODE_AXI_DECERR 8 118 #define AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT 9 119 #define AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE 10 120 #define AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE 11 121 #define AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE 12 122 #define AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE 13 123 #define AFI_INTR_CODE_INT_CODE_P2P_ERROR 14 124 125 #define AFI_INTR_SIGNATURE 0x0bc 126 #define AFI_UPPER_FPCI_ADDRESS 0x0c0 127 #define AFI_SM_INTR_ENABLE 0x0c4 128 #define AFI_SM_INTR_RP_DEASSERT (1 << 14) 129 #define AFI_SM_INTR_RP_ASSERT (1 << 13) 130 #define AFI_SM_INTR_HOTPLUG (1 << 12) 131 #define AFI_SM_INTR_PME (1 << 11) 132 #define AFI_SM_INTR_FATAL_ERROR (1 << 10) 133 #define AFI_SM_INTR_UNCORR_ERROR (1 << 9) 134 #define AFI_SM_INTR_CORR_ERROR (1 << 8) 135 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 136 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 137 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 138 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 139 #define AFI_SM_INTR_INTD_ASSERT (1 << 3) 140 #define AFI_SM_INTR_INTC_ASSERT (1 << 2) 141 #define AFI_SM_INTR_INTB_ASSERT (1 << 1) 142 #define AFI_SM_INTR_INTA_ASSERT (1 << 0) 143 144 #define AFI_AFI_INTR_ENABLE 0x0c8 145 #define AFI_AFI_INTR_ENABLE_CODE(code) (1 << (code)) 146 147 #define AFI_PCIE_CONFIG 0x0f8 148 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 149 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0x6 150 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 151 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1 (0x0 << 20) 152 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1 (0x1 << 20) 153 154 #define AFI_FUSE 0x104 155 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 156 157 #define AFI_PEX0_CTRL 0x110 158 #define AFI_PEX1_CTRL 0x118 159 #define AFI_PEX2_CTRL 0x128 160 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 161 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 162 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 163 #define AFI_PEX_CTRL_RST_L (1 << 0) 164 165 #define AFI_AXI_BAR6_SZ 0x134 166 #define AFI_AXI_BAR7_SZ 0x138 167 #define AFI_AXI_BAR8_SZ 0x13c 168 #define AFI_AXI_BAR6_START 0x140 169 #define AFI_AXI_BAR7_START 0x144 170 #define AFI_AXI_BAR8_START 0x148 171 #define AFI_FPCI_BAR6 0x14c 172 #define AFI_FPCI_BAR7 0x150 173 #define AFI_FPCI_BAR8 0x154 174 #define AFI_PLLE_CONTROL 0x160 175 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 176 #define AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL (1 << 8) 177 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 178 #define AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN (1 << 0) 179 180 #define AFI_PEXBIAS_CTRL 0x168 181 182 /* Configuration space */ 183 #define RP_VEND_XP 0x0F00 184 #define RP_VEND_XP_DL_UP (1 << 30) 185 186 #define RP_VEND_CTL2 0x0fa8 187 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) 188 189 #define RP_PRIV_MISC 0x0FE0 190 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 191 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 192 193 #define RP_LINK_CONTROL_STATUS 0x0090 194 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 195 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 196 197 /* PADS space */ 198 #define PADS_REFCLK_CFG0 0x000c8 199 #define PADS_REFCLK_CFG1 0x000cc 200 201 202 /* Wait 50 ms (per port) for link. */ 203 #define TEGRA_PCIE_LINKUP_TIMEOUT 50000 204 205 /* FPCI Address space */ 206 #define FPCI_MAP_IO 0xFDFC000000ULL 207 #define FPCI_MAP_TYPE0_CONFIG 0xFDFC000000ULL 208 #define FPCI_MAP_TYPE1_CONFIG 0xFDFF000000ULL 209 #define FPCI_MAP_EXT_TYPE0_CONFIG 0xFE00000000ULL 210 #define FPCI_MAP_EXT_TYPE1_CONFIG 0xFE10000000ULL 211 212 #define TEGRA_PCIB_MSI_ENABLE 213 214 #define DEBUG 215 #ifdef DEBUG 216 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 217 #else 218 #define debugf(fmt, args...) 219 #endif 220 221 /* 222 * Configuration space format: 223 * [27:24] extended register 224 * [23:16] bus 225 * [15:11] slot (device) 226 * [10: 8] function 227 * [ 7: 0] register 228 */ 229 #define PCI_CFG_EXT_REG(reg) ((((reg) >> 8) & 0x0f) << 24) 230 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 231 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 232 #define PCI_CFG_FUN(fun) (((fun) & 0x07) << 8) 233 #define PCI_CFG_BASE_REG(reg) ((reg) & 0xff) 234 235 #define PADS_WR4(_sc, _r, _v) bus_write_4((_sc)->pads_mem_res, (_r), (_v)) 236 #define PADS_RD4(_sc, _r) bus_read_4((_sc)->pads_mem_res, (_r)) 237 #define AFI_WR4(_sc, _r, _v) bus_write_4((_sc)->afi_mem_res, (_r), (_v)) 238 #define AFI_RD4(_sc, _r) bus_read_4((_sc)->afi_mem_res, (_r)) 239 240 static struct { 241 bus_size_t axi_start; 242 bus_size_t fpci_start; 243 bus_size_t size; 244 } bars[] = { 245 {AFI_AXI_BAR0_START, AFI_FPCI_BAR0, AFI_AXI_BAR0_SZ}, /* BAR 0 */ 246 {AFI_AXI_BAR1_START, AFI_FPCI_BAR1, AFI_AXI_BAR1_SZ}, /* BAR 1 */ 247 {AFI_AXI_BAR2_START, AFI_FPCI_BAR2, AFI_AXI_BAR2_SZ}, /* BAR 2 */ 248 {AFI_AXI_BAR3_START, AFI_FPCI_BAR3, AFI_AXI_BAR3_SZ}, /* BAR 3 */ 249 {AFI_AXI_BAR4_START, AFI_FPCI_BAR4, AFI_AXI_BAR4_SZ}, /* BAR 4 */ 250 {AFI_AXI_BAR5_START, AFI_FPCI_BAR5, AFI_AXI_BAR5_SZ}, /* BAR 5 */ 251 {AFI_AXI_BAR6_START, AFI_FPCI_BAR6, AFI_AXI_BAR6_SZ}, /* BAR 6 */ 252 {AFI_AXI_BAR7_START, AFI_FPCI_BAR7, AFI_AXI_BAR7_SZ}, /* BAR 7 */ 253 {AFI_AXI_BAR8_START, AFI_FPCI_BAR8, AFI_AXI_BAR8_SZ}, /* BAR 8 */ 254 {AFI_MSI_AXI_BAR_ST, AFI_MSI_FPCI_BAR_ST, AFI_MSI_BAR_SZ}, /* MSI 9 */ 255 }; 256 257 258 struct pcie_soc { 259 char **regulator_names; 260 bool cml_clk; 261 bool pca_enable; 262 uint32_t pads_refclk_cfg0; 263 uint32_t pads_refclk_cfg1; 264 }; 265 266 /* Tegra 124 config. */ 267 static char *tegra124_reg_names[] = { 268 "avddio-pex-supply", 269 "dvddio-pex-supply", 270 "avdd-pex-pll-supply", 271 "hvdd-pex-supply", 272 "hvdd-pex-pll-e-supply", 273 "vddio-pex-ctl-supply", 274 "avdd-pll-erefe-supply", 275 NULL 276 }; 277 278 static struct pcie_soc tegra124_soc = { 279 .regulator_names = tegra124_reg_names, 280 .cml_clk = true, 281 .pca_enable = false, 282 .pads_refclk_cfg0 = 0x44ac44ac, 283 }; 284 285 /* Tegra 210 config. */ 286 static char *tegra210_reg_names[] = { 287 "avdd-pll-uerefe-supply", 288 "hvddio-pex-supply", 289 "dvddio-pex-supply", 290 "dvdd-pex-pll-supply", 291 "hvdd-pex-pll-e-supply", 292 "vddio-pex-ctl-supply", 293 NULL 294 }; 295 296 static struct pcie_soc tegra210_soc = { 297 .regulator_names = tegra210_reg_names, 298 .cml_clk = true, 299 .pca_enable = true, 300 .pads_refclk_cfg0 = 0x90b890b8, 301 }; 302 303 /* Compatible devices. */ 304 static struct ofw_compat_data compat_data[] = { 305 {"nvidia,tegra124-pcie", (uintptr_t)&tegra124_soc}, 306 {"nvidia,tegra210-pcie", (uintptr_t)&tegra210_soc}, 307 {NULL, 0}, 308 }; 309 310 #define TEGRA_FLAG_MSI_USED 0x0001 311 struct tegra_pcib_irqsrc { 312 struct intr_irqsrc isrc; 313 u_int irq; 314 u_int flags; 315 }; 316 317 struct tegra_pcib_port { 318 int enabled; 319 int port_idx; /* chip port index */ 320 int num_lanes; /* number of lanes */ 321 bus_size_t afi_pex_ctrl; /* offset of afi_pex_ctrl */ 322 phy_t phy; /* port phy */ 323 324 /* Config space properties. */ 325 bus_addr_t rp_base_addr; /* PA of config window */ 326 bus_size_t rp_size; /* size of config window */ 327 bus_space_handle_t cfg_handle; /* handle of config window */ 328 }; 329 330 #define TEGRA_PCIB_MAX_PORTS 3 331 #define TEGRA_PCIB_MAX_MSI AFI_MSI_INTR_IN_REG * AFI_MSI_REGS 332 struct tegra_pcib_softc { 333 struct ofw_pci_softc ofw_pci; 334 device_t dev; 335 struct pcie_soc *soc; 336 struct mtx mtx; 337 struct resource *pads_mem_res; 338 struct resource *afi_mem_res; 339 struct resource *cfg_mem_res; 340 struct resource *irq_res; 341 struct resource *msi_irq_res; 342 void *intr_cookie; 343 void *msi_intr_cookie; 344 345 struct ofw_pci_range mem_range; 346 struct ofw_pci_range pref_mem_range; 347 struct ofw_pci_range io_range; 348 349 clk_t clk_pex; 350 clk_t clk_afi; 351 clk_t clk_pll_e; 352 clk_t clk_cml; 353 hwreset_t hwreset_pex; 354 hwreset_t hwreset_afi; 355 hwreset_t hwreset_pcie_x; 356 regulator_t regulators[16]; /* Safe maximum */ 357 358 vm_offset_t msi_page; /* VA of MSI page */ 359 bus_addr_t cfg_base_addr; /* base address of config */ 360 bus_size_t cfg_cur_offs; /* currently mapped window */ 361 bus_space_handle_t cfg_handle; /* handle of config window */ 362 bus_space_tag_t bus_tag; /* tag of config window */ 363 int lanes_cfg; 364 int num_ports; 365 struct tegra_pcib_port *ports[TEGRA_PCIB_MAX_PORTS]; 366 struct tegra_pcib_irqsrc *isrcs; 367 }; 368 369 static int 370 tegra_pcib_maxslots(device_t dev) 371 { 372 return (16); 373 } 374 375 static int 376 tegra_pcib_route_interrupt(device_t bus, device_t dev, int pin) 377 { 378 struct tegra_pcib_softc *sc; 379 u_int irq; 380 381 sc = device_get_softc(bus); 382 irq = intr_map_clone_irq(rman_get_start(sc->irq_res)); 383 device_printf(bus, "route pin %d for device %d.%d to %u\n", 384 pin, pci_get_slot(dev), pci_get_function(dev), 385 irq); 386 387 return (irq); 388 } 389 390 static int 391 tegra_pcbib_map_cfg(struct tegra_pcib_softc *sc, u_int bus, u_int slot, 392 u_int func, u_int reg) 393 { 394 bus_size_t offs; 395 int rv; 396 397 offs = sc->cfg_base_addr; 398 offs |= PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | PCI_CFG_FUN(func) | 399 PCI_CFG_EXT_REG(reg); 400 if ((sc->cfg_handle != 0) && (sc->cfg_cur_offs == offs)) 401 return (0); 402 if (sc->cfg_handle != 0) 403 bus_space_unmap(sc->bus_tag, sc->cfg_handle, 0x800); 404 405 rv = bus_space_map(sc->bus_tag, offs, 0x800, 0, &sc->cfg_handle); 406 if (rv != 0) 407 device_printf(sc->dev, "Cannot map config space\n"); 408 else 409 sc->cfg_cur_offs = offs; 410 return (rv); 411 } 412 413 static uint32_t 414 tegra_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 415 u_int reg, int bytes) 416 { 417 struct tegra_pcib_softc *sc; 418 bus_space_handle_t hndl; 419 uint32_t off; 420 uint32_t val; 421 int rv, i; 422 423 sc = device_get_softc(dev); 424 if (bus == 0) { 425 if (func != 0) 426 return (0xFFFFFFFF); 427 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 428 if ((sc->ports[i] != NULL) && 429 (sc->ports[i]->port_idx == slot)) { 430 hndl = sc->ports[i]->cfg_handle; 431 off = reg & 0xFFF; 432 break; 433 } 434 } 435 if (i >= TEGRA_PCIB_MAX_PORTS) 436 return (0xFFFFFFFF); 437 } else { 438 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 439 if (rv != 0) 440 return (0xFFFFFFFF); 441 hndl = sc->cfg_handle; 442 off = PCI_CFG_BASE_REG(reg); 443 } 444 445 val = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 446 switch (bytes) { 447 case 4: 448 break; 449 case 2: 450 if (off & 3) 451 val >>= 16; 452 val &= 0xffff; 453 break; 454 case 1: 455 val >>= ((off & 3) << 3); 456 val &= 0xff; 457 break; 458 } 459 return val; 460 } 461 462 static void 463 tegra_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 464 u_int reg, uint32_t val, int bytes) 465 { 466 struct tegra_pcib_softc *sc; 467 bus_space_handle_t hndl; 468 uint32_t off; 469 uint32_t val2; 470 int rv, i; 471 472 sc = device_get_softc(dev); 473 if (bus == 0) { 474 if (func != 0) 475 return; 476 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 477 if ((sc->ports[i] != NULL) && 478 (sc->ports[i]->port_idx == slot)) { 479 hndl = sc->ports[i]->cfg_handle; 480 off = reg & 0xFFF; 481 break; 482 } 483 } 484 if (i >= TEGRA_PCIB_MAX_PORTS) 485 return; 486 } else { 487 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 488 if (rv != 0) 489 return; 490 hndl = sc->cfg_handle; 491 off = PCI_CFG_BASE_REG(reg); 492 } 493 494 switch (bytes) { 495 case 4: 496 bus_space_write_4(sc->bus_tag, hndl, off, val); 497 break; 498 case 2: 499 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 500 val2 &= ~(0xffff << ((off & 3) << 3)); 501 val2 |= ((val & 0xffff) << ((off & 3) << 3)); 502 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 503 break; 504 case 1: 505 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 506 val2 &= ~(0xff << ((off & 3) << 3)); 507 val2 |= ((val & 0xff) << ((off & 3) << 3)); 508 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 509 break; 510 } 511 } 512 513 static int tegra_pci_intr(void *arg) 514 { 515 struct tegra_pcib_softc *sc = arg; 516 uint32_t code, signature; 517 518 code = bus_read_4(sc->afi_mem_res, AFI_INTR_CODE) & AFI_INTR_CODE_MASK; 519 signature = bus_read_4(sc->afi_mem_res, AFI_INTR_SIGNATURE); 520 bus_write_4(sc->afi_mem_res, AFI_INTR_CODE, 0); 521 if (code == AFI_INTR_CODE_INT_CODE_SM_MSG) 522 return(FILTER_STRAY); 523 524 printf("tegra_pci_intr: code %x sig %x\n", code, signature); 525 return (FILTER_HANDLED); 526 } 527 528 /* ----------------------------------------------------------------------- 529 * 530 * PCI MSI interface 531 */ 532 static int 533 tegra_pcib_alloc_msi(device_t pci, device_t child, int count, int maxcount, 534 int *irqs) 535 { 536 phandle_t msi_parent; 537 538 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 539 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 540 NULL); 541 */ 542 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 543 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 544 irqs)); 545 } 546 547 static int 548 tegra_pcib_release_msi(device_t pci, device_t child, int count, int *irqs) 549 { 550 phandle_t msi_parent; 551 552 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 553 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 554 NULL); 555 */ 556 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 557 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 558 } 559 560 static int 561 tegra_pcib_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 562 uint32_t *data) 563 { 564 phandle_t msi_parent; 565 566 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 567 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 568 NULL); 569 */ 570 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 571 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 572 } 573 574 #ifdef TEGRA_PCIB_MSI_ENABLE 575 576 /* -------------------------------------------------------------------------- 577 * 578 * Interrupts 579 * 580 */ 581 582 static inline void 583 tegra_pcib_isrc_mask(struct tegra_pcib_softc *sc, 584 struct tegra_pcib_irqsrc *tgi, uint32_t val) 585 { 586 uint32_t reg; 587 int offs, bit; 588 589 offs = tgi->irq / AFI_MSI_INTR_IN_REG; 590 bit = 1 << (tgi->irq % AFI_MSI_INTR_IN_REG); 591 592 if (val != 0) 593 AFI_WR4(sc, AFI_MSI_VEC(offs), bit); 594 reg = AFI_RD4(sc, AFI_MSI_EN_VEC(offs)); 595 if (val != 0) 596 reg |= bit; 597 else 598 reg &= ~bit; 599 AFI_WR4(sc, AFI_MSI_EN_VEC(offs), reg); 600 } 601 602 static int 603 tegra_pcib_msi_intr(void *arg) 604 { 605 u_int irq, i, bit, reg; 606 struct tegra_pcib_softc *sc; 607 struct trapframe *tf; 608 struct tegra_pcib_irqsrc *tgi; 609 610 sc = (struct tegra_pcib_softc *)arg; 611 tf = curthread->td_intr_frame; 612 613 for (i = 0; i < AFI_MSI_REGS; i++) { 614 reg = AFI_RD4(sc, AFI_MSI_VEC(i)); 615 /* Handle one vector. */ 616 while (reg != 0) { 617 bit = ffs(reg) - 1; 618 /* Send EOI */ 619 AFI_WR4(sc, AFI_MSI_VEC(i), 1 << bit); 620 irq = i * AFI_MSI_INTR_IN_REG + bit; 621 tgi = &sc->isrcs[irq]; 622 if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) { 623 /* Disable stray. */ 624 tegra_pcib_isrc_mask(sc, tgi, 0); 625 device_printf(sc->dev, 626 "Stray irq %u disabled\n", irq); 627 } 628 reg = AFI_RD4(sc, AFI_MSI_VEC(i)); 629 } 630 } 631 return (FILTER_HANDLED); 632 } 633 634 static int 635 tegra_pcib_msi_attach(struct tegra_pcib_softc *sc) 636 { 637 int error; 638 uint32_t irq; 639 const char *name; 640 641 sc->isrcs = malloc(sizeof(*sc->isrcs) * TEGRA_PCIB_MAX_MSI, M_DEVBUF, 642 M_WAITOK | M_ZERO); 643 644 name = device_get_nameunit(sc->dev); 645 for (irq = 0; irq < TEGRA_PCIB_MAX_MSI; irq++) { 646 sc->isrcs[irq].irq = irq; 647 error = intr_isrc_register(&sc->isrcs[irq].isrc, 648 sc->dev, 0, "%s,%u", name, irq); 649 if (error != 0) 650 return (error); /* XXX deregister ISRCs */ 651 } 652 if (intr_msi_register(sc->dev, 653 OF_xref_from_node(ofw_bus_get_node(sc->dev))) != 0) 654 return (ENXIO); 655 656 return (0); 657 } 658 659 static int 660 tegra_pcib_msi_detach(struct tegra_pcib_softc *sc) 661 { 662 663 /* 664 * There has not been established any procedure yet 665 * how to detach PIC from living system correctly. 666 */ 667 device_printf(sc->dev, "%s: not implemented yet\n", __func__); 668 return (EBUSY); 669 } 670 671 static void 672 tegra_pcib_msi_disable_intr(device_t dev, struct intr_irqsrc *isrc) 673 { 674 struct tegra_pcib_softc *sc; 675 struct tegra_pcib_irqsrc *tgi; 676 677 sc = device_get_softc(dev); 678 tgi = (struct tegra_pcib_irqsrc *)isrc; 679 tegra_pcib_isrc_mask(sc, tgi, 0); 680 } 681 682 static void 683 tegra_pcib_msi_enable_intr(device_t dev, struct intr_irqsrc *isrc) 684 { 685 struct tegra_pcib_softc *sc; 686 struct tegra_pcib_irqsrc *tgi; 687 688 sc = device_get_softc(dev); 689 tgi = (struct tegra_pcib_irqsrc *)isrc; 690 tegra_pcib_isrc_mask(sc, tgi, 1); 691 } 692 693 /* MSI interrupts are edge trigered -> do nothing */ 694 static void 695 tegra_pcib_msi_post_filter(device_t dev, struct intr_irqsrc *isrc) 696 { 697 } 698 699 static void 700 tegra_pcib_msi_post_ithread(device_t dev, struct intr_irqsrc *isrc) 701 { 702 } 703 704 static void 705 tegra_pcib_msi_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 706 { 707 } 708 709 static int 710 tegra_pcib_msi_setup_intr(device_t dev, struct intr_irqsrc *isrc, 711 struct resource *res, struct intr_map_data *data) 712 { 713 if (data == NULL || data->type != INTR_MAP_DATA_MSI) 714 return (ENOTSUP); 715 716 if (isrc->isrc_handlers == 0) 717 tegra_pcib_msi_enable_intr(dev, isrc); 718 719 return (0); 720 } 721 722 static int 723 tegra_pcib_msi_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 724 struct resource *res, struct intr_map_data *data) 725 { 726 struct tegra_pcib_softc *sc; 727 struct tegra_pcib_irqsrc *tgi; 728 729 sc = device_get_softc(dev); 730 tgi = (struct tegra_pcib_irqsrc *)isrc; 731 732 if (isrc->isrc_handlers == 0) 733 tegra_pcib_isrc_mask(sc, tgi, 0); 734 return (0); 735 } 736 737 static int 738 tegra_pcib_msi_alloc_msi(device_t dev, device_t child, int count, int maxcount, 739 device_t *pic, struct intr_irqsrc **srcs) 740 { 741 struct tegra_pcib_softc *sc; 742 int i, irq, end_irq; 743 bool found; 744 745 KASSERT(powerof2(count), ("%s: bad count", __func__)); 746 KASSERT(powerof2(maxcount), ("%s: bad maxcount", __func__)); 747 748 sc = device_get_softc(dev); 749 mtx_lock(&sc->mtx); 750 751 found = false; 752 for (irq = 0; (irq + count - 1) < TEGRA_PCIB_MAX_MSI; irq++) { 753 /* Start on an aligned interrupt */ 754 if ((irq & (maxcount - 1)) != 0) 755 continue; 756 757 /* Assume we found a valid range until shown otherwise */ 758 found = true; 759 760 /* Check this range is valid */ 761 for (end_irq = irq; end_irq < irq + count; end_irq++) { 762 /* This is already used */ 763 if ((sc->isrcs[end_irq].flags & TEGRA_FLAG_MSI_USED) == 764 TEGRA_FLAG_MSI_USED) { 765 found = false; 766 break; 767 } 768 } 769 770 if (found) 771 break; 772 } 773 774 /* Not enough interrupts were found */ 775 if (!found || irq == (TEGRA_PCIB_MAX_MSI - 1)) { 776 mtx_unlock(&sc->mtx); 777 return (ENXIO); 778 } 779 780 for (i = 0; i < count; i++) { 781 /* Mark the interrupt as used */ 782 sc->isrcs[irq + i].flags |= TEGRA_FLAG_MSI_USED; 783 } 784 mtx_unlock(&sc->mtx); 785 786 for (i = 0; i < count; i++) 787 srcs[i] = (struct intr_irqsrc *)&sc->isrcs[irq + i]; 788 *pic = device_get_parent(dev); 789 return (0); 790 } 791 792 static int 793 tegra_pcib_msi_release_msi(device_t dev, device_t child, int count, 794 struct intr_irqsrc **isrc) 795 { 796 struct tegra_pcib_softc *sc; 797 struct tegra_pcib_irqsrc *ti; 798 int i; 799 800 sc = device_get_softc(dev); 801 mtx_lock(&sc->mtx); 802 for (i = 0; i < count; i++) { 803 ti = (struct tegra_pcib_irqsrc *)isrc[i]; 804 805 KASSERT((ti->flags & TEGRA_FLAG_MSI_USED) == TEGRA_FLAG_MSI_USED, 806 ("%s: Trying to release an unused MSI-X interrupt", 807 __func__)); 808 809 ti->flags &= ~TEGRA_FLAG_MSI_USED; 810 } 811 mtx_unlock(&sc->mtx); 812 return (0); 813 } 814 815 static int 816 tegra_pcib_msi_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc, 817 uint64_t *addr, uint32_t *data) 818 { 819 struct tegra_pcib_softc *sc = device_get_softc(dev); 820 struct tegra_pcib_irqsrc *ti = (struct tegra_pcib_irqsrc *)isrc; 821 822 *addr = vtophys(sc->msi_page); 823 *data = ti->irq; 824 return (0); 825 } 826 #endif 827 828 /* ------------------------------------------------------------------- */ 829 static bus_size_t 830 tegra_pcib_pex_ctrl(struct tegra_pcib_softc *sc, int port) 831 { 832 switch (port) { 833 case 0: 834 return (AFI_PEX0_CTRL); 835 case 1: 836 return (AFI_PEX1_CTRL); 837 case 2: 838 return (AFI_PEX2_CTRL); 839 default: 840 panic("invalid port number: %d\n", port); 841 } 842 } 843 844 static int 845 tegra_pcib_enable_fdt_resources(struct tegra_pcib_softc *sc) 846 { 847 int i, rv; 848 849 rv = hwreset_assert(sc->hwreset_pcie_x); 850 if (rv != 0) { 851 device_printf(sc->dev, "Cannot assert 'pcie_x' reset\n"); 852 return (rv); 853 } 854 rv = hwreset_assert(sc->hwreset_afi); 855 if (rv != 0) { 856 device_printf(sc->dev, "Cannot assert 'afi' reset\n"); 857 return (rv); 858 } 859 rv = hwreset_assert(sc->hwreset_pex); 860 if (rv != 0) { 861 device_printf(sc->dev, "Cannot assert 'pex' reset\n"); 862 return (rv); 863 } 864 865 tegra_powergate_power_off(TEGRA_POWERGATE_PCX); 866 867 /* Regulators. */ 868 for (i = 0; i < nitems(sc->regulators); i++) { 869 if (sc->regulators[i] == NULL) 870 continue; 871 rv = regulator_enable(sc->regulators[i]); 872 if (rv != 0) { 873 device_printf(sc->dev, 874 "Cannot enable '%s' regulator\n", 875 sc->soc->regulator_names[i]); 876 return (rv); 877 } 878 } 879 880 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCX, 881 sc->clk_pex, sc->hwreset_pex); 882 if (rv != 0) { 883 device_printf(sc->dev, "Cannot enable 'PCX' powergate\n"); 884 return (rv); 885 } 886 887 rv = hwreset_deassert(sc->hwreset_afi); 888 if (rv != 0) { 889 device_printf(sc->dev, "Cannot unreset 'afi' reset\n"); 890 return (rv); 891 } 892 893 rv = clk_enable(sc->clk_afi); 894 if (rv != 0) { 895 device_printf(sc->dev, "Cannot enable 'afi' clock\n"); 896 return (rv); 897 } 898 if (sc->soc->cml_clk) { 899 rv = clk_enable(sc->clk_cml); 900 if (rv != 0) { 901 device_printf(sc->dev, "Cannot enable 'cml' clock\n"); 902 return (rv); 903 } 904 } 905 rv = clk_enable(sc->clk_pll_e); 906 if (rv != 0) { 907 device_printf(sc->dev, "Cannot enable 'pll_e' clock\n"); 908 return (rv); 909 } 910 911 return (0); 912 } 913 914 static struct tegra_pcib_port * 915 tegra_pcib_parse_port(struct tegra_pcib_softc *sc, phandle_t node) 916 { 917 struct tegra_pcib_port *port; 918 uint32_t tmp[5]; 919 char tmpstr[6]; 920 int rv; 921 922 port = malloc(sizeof(struct tegra_pcib_port), M_DEVBUF, M_WAITOK); 923 924 rv = OF_getprop(node, "status", tmpstr, sizeof(tmpstr)); 925 if (rv <= 0 || strcmp(tmpstr, "okay") == 0 || 926 strcmp(tmpstr, "ok") == 0) 927 port->enabled = 1; 928 else 929 port->enabled = 0; 930 931 rv = OF_getencprop(node, "assigned-addresses", tmp, sizeof(tmp)); 932 if (rv != sizeof(tmp)) { 933 device_printf(sc->dev, "Cannot parse assigned-address: %d\n", 934 rv); 935 goto fail; 936 } 937 port->rp_base_addr = tmp[2]; 938 port->rp_size = tmp[4]; 939 port->port_idx = OFW_PCI_PHYS_HI_DEVICE(tmp[0]) - 1; 940 if (port->port_idx >= TEGRA_PCIB_MAX_PORTS) { 941 device_printf(sc->dev, "Invalid port index: %d\n", 942 port->port_idx); 943 goto fail; 944 } 945 /* XXX - TODO: 946 * Implement proper function for parsing pci "reg" property: 947 * - it have PCI bus format 948 * - its relative to matching "assigned-addresses" 949 */ 950 rv = OF_getencprop(node, "reg", tmp, sizeof(tmp)); 951 if (rv != sizeof(tmp)) { 952 device_printf(sc->dev, "Cannot parse reg: %d\n", rv); 953 goto fail; 954 } 955 port->rp_base_addr += tmp[2]; 956 957 rv = OF_getencprop(node, "nvidia,num-lanes", &port->num_lanes, 958 sizeof(port->num_lanes)); 959 if (rv != sizeof(port->num_lanes)) { 960 device_printf(sc->dev, "Cannot parse nvidia,num-lanes: %d\n", 961 rv); 962 goto fail; 963 } 964 if (port->num_lanes > 4) { 965 device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n", 966 port->num_lanes); 967 goto fail; 968 } 969 970 port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx); 971 sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx); 972 973 /* Phy. */ 974 rv = phy_get_by_ofw_name(sc->dev, node, "pcie-0", &port->phy); 975 if (rv != 0) { 976 device_printf(sc->dev, 977 "Cannot get 'pcie-0' phy for port %d\n", 978 port->port_idx); 979 goto fail; 980 } 981 982 return (port); 983 fail: 984 free(port, M_DEVBUF); 985 return (NULL); 986 } 987 988 static int 989 tegra_pcib_parse_fdt_resources(struct tegra_pcib_softc *sc, phandle_t node) 990 { 991 phandle_t child; 992 struct tegra_pcib_port *port; 993 int i, rv; 994 995 /* Regulators. */ 996 for (i = 0; sc->soc->regulator_names[i] != NULL; i++) { 997 if (i >= nitems(sc->regulators)) { 998 device_printf(sc->dev, 999 "Too many regulators present in DT.\n"); 1000 return (EOVERFLOW); 1001 } 1002 rv = regulator_get_by_ofw_property(sc->dev, 0, 1003 sc->soc->regulator_names[i], sc->regulators + i); 1004 if (rv != 0) { 1005 device_printf(sc->dev, 1006 "Cannot get '%s' regulator\n", 1007 sc->soc->regulator_names[i]); 1008 return (ENXIO); 1009 } 1010 } 1011 1012 /* Resets. */ 1013 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pex", &sc->hwreset_pex); 1014 if (rv != 0) { 1015 device_printf(sc->dev, "Cannot get 'pex' reset\n"); 1016 return (ENXIO); 1017 } 1018 rv = hwreset_get_by_ofw_name(sc->dev, 0, "afi", &sc->hwreset_afi); 1019 if (rv != 0) { 1020 device_printf(sc->dev, "Cannot get 'afi' reset\n"); 1021 return (ENXIO); 1022 } 1023 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pcie_x", &sc->hwreset_pcie_x); 1024 if (rv != 0) { 1025 device_printf(sc->dev, "Cannot get 'pcie_x' reset\n"); 1026 return (ENXIO); 1027 } 1028 1029 /* Clocks. */ 1030 rv = clk_get_by_ofw_name(sc->dev, 0, "pex", &sc->clk_pex); 1031 if (rv != 0) { 1032 device_printf(sc->dev, "Cannot get 'pex' clock\n"); 1033 return (ENXIO); 1034 } 1035 rv = clk_get_by_ofw_name(sc->dev, 0, "afi", &sc->clk_afi); 1036 if (rv != 0) { 1037 device_printf(sc->dev, "Cannot get 'afi' clock\n"); 1038 return (ENXIO); 1039 } 1040 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e); 1041 if (rv != 0) { 1042 device_printf(sc->dev, "Cannot get 'pll_e' clock\n"); 1043 return (ENXIO); 1044 } 1045 if (sc->soc->cml_clk) { 1046 rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml); 1047 if (rv != 0) { 1048 device_printf(sc->dev, "Cannot get 'cml' clock\n"); 1049 return (ENXIO); 1050 } 1051 } 1052 1053 /* Ports */ 1054 sc->num_ports = 0; 1055 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 1056 port = tegra_pcib_parse_port(sc, child); 1057 if (port == NULL) { 1058 device_printf(sc->dev, "Cannot parse PCIe port node\n"); 1059 return (ENXIO); 1060 } 1061 sc->ports[sc->num_ports++] = port; 1062 } 1063 1064 return (0); 1065 } 1066 1067 static int 1068 tegra_pcib_decode_ranges(struct tegra_pcib_softc *sc, 1069 struct ofw_pci_range *ranges, int nranges) 1070 { 1071 int i; 1072 1073 for (i = 2; i < nranges; i++) { 1074 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 1075 OFW_PCI_PHYS_HI_SPACE_IO) { 1076 if (sc->io_range.size != 0) { 1077 device_printf(sc->dev, 1078 "Duplicated IO range found in DT\n"); 1079 return (ENXIO); 1080 } 1081 sc->io_range = ranges[i]; 1082 } 1083 if (((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 1084 OFW_PCI_PHYS_HI_SPACE_MEM32)) { 1085 if (ranges[i].pci_hi & OFW_PCI_PHYS_HI_PREFETCHABLE) { 1086 if (sc->pref_mem_range.size != 0) { 1087 device_printf(sc->dev, 1088 "Duplicated memory range found " 1089 "in DT\n"); 1090 return (ENXIO); 1091 } 1092 sc->pref_mem_range = ranges[i]; 1093 } else { 1094 if (sc->mem_range.size != 0) { 1095 device_printf(sc->dev, 1096 "Duplicated memory range found " 1097 "in DT\n"); 1098 return (ENXIO); 1099 } 1100 sc->mem_range = ranges[i]; 1101 } 1102 } 1103 } 1104 if ((sc->io_range.size == 0) || (sc->mem_range.size == 0) 1105 || (sc->pref_mem_range.size == 0)) { 1106 device_printf(sc->dev, 1107 " Not all required ranges are found in DT\n"); 1108 return (ENXIO); 1109 } 1110 return (0); 1111 } 1112 1113 /* 1114 * Hardware config. 1115 */ 1116 static int 1117 tegra_pcib_wait_for_link(struct tegra_pcib_softc *sc, 1118 struct tegra_pcib_port *port) 1119 { 1120 uint32_t reg; 1121 int i; 1122 1123 /* Setup link detection. */ 1124 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1125 RP_PRIV_MISC, 4); 1126 reg &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 1127 reg |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 1128 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0, 1129 RP_PRIV_MISC, reg, 4); 1130 1131 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1132 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1133 RP_VEND_XP, 4); 1134 if (reg & RP_VEND_XP_DL_UP) 1135 break; 1136 DELAY(1); 1137 } 1138 if (i <= 0) 1139 return (ETIMEDOUT); 1140 1141 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1142 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1143 RP_LINK_CONTROL_STATUS, 4); 1144 if (reg & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 1145 break; 1146 1147 DELAY(1); 1148 } 1149 if (i <= 0) 1150 return (ETIMEDOUT); 1151 return (0); 1152 } 1153 1154 static void 1155 tegra_pcib_port_enable(struct tegra_pcib_softc *sc, int port_num) 1156 { 1157 struct tegra_pcib_port *port; 1158 uint32_t reg; 1159 int rv; 1160 1161 port = sc->ports[port_num]; 1162 1163 /* Put port to reset. */ 1164 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1165 reg &= ~AFI_PEX_CTRL_RST_L; 1166 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1167 AFI_RD4(sc, port->afi_pex_ctrl); 1168 DELAY(10); 1169 1170 /* Enable clocks. */ 1171 reg |= AFI_PEX_CTRL_REFCLK_EN; 1172 reg |= AFI_PEX_CTRL_CLKREQ_EN; 1173 reg |= AFI_PEX_CTRL_OVERRIDE_EN; 1174 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1175 AFI_RD4(sc, port->afi_pex_ctrl); 1176 DELAY(100); 1177 1178 /* Release reset. */ 1179 reg |= AFI_PEX_CTRL_RST_L; 1180 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1181 1182 if (sc->soc->pca_enable) { 1183 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1184 RP_VEND_CTL2, 4); 1185 reg |= RP_VEND_CTL2_PCA_ENABLE; 1186 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0, 1187 RP_VEND_CTL2, reg, 4); 1188 } 1189 1190 rv = tegra_pcib_wait_for_link(sc, port); 1191 if (bootverbose) 1192 device_printf(sc->dev, " port %d (%d lane%s): Link is %s\n", 1193 port->port_idx, port->num_lanes, 1194 port->num_lanes > 1 ? "s": "", 1195 rv == 0 ? "up": "down"); 1196 } 1197 1198 static void 1199 tegra_pcib_port_disable(struct tegra_pcib_softc *sc, uint32_t port_num) 1200 { 1201 struct tegra_pcib_port *port; 1202 uint32_t reg; 1203 1204 port = sc->ports[port_num]; 1205 1206 /* Put port to reset. */ 1207 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1208 reg &= ~AFI_PEX_CTRL_RST_L; 1209 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1210 AFI_RD4(sc, port->afi_pex_ctrl); 1211 DELAY(10); 1212 1213 /* Disable clocks. */ 1214 reg &= ~AFI_PEX_CTRL_CLKREQ_EN; 1215 reg &= ~AFI_PEX_CTRL_REFCLK_EN; 1216 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1217 1218 if (bootverbose) 1219 device_printf(sc->dev, " port %d (%d lane%s): Disabled\n", 1220 port->port_idx, port->num_lanes, 1221 port->num_lanes > 1 ? "s": ""); 1222 } 1223 1224 static void 1225 tegra_pcib_set_bar(struct tegra_pcib_softc *sc, int bar, uint32_t axi, 1226 uint64_t fpci, uint32_t size, int is_memory) 1227 { 1228 uint32_t fpci_reg; 1229 uint32_t axi_reg; 1230 uint32_t size_reg; 1231 1232 axi_reg = axi & ~0xFFF; 1233 size_reg = size >> 12; 1234 fpci_reg = (uint32_t)(fpci >> 8) & ~0xF; 1235 fpci_reg |= is_memory ? 0x1 : 0x0; 1236 AFI_WR4(sc, bars[bar].axi_start, axi_reg); 1237 AFI_WR4(sc, bars[bar].size, size_reg); 1238 AFI_WR4(sc, bars[bar].fpci_start, fpci_reg); 1239 } 1240 1241 static int 1242 tegra_pcib_enable(struct tegra_pcib_softc *sc) 1243 { 1244 int rv; 1245 int i; 1246 uint32_t reg; 1247 1248 rv = tegra_pcib_enable_fdt_resources(sc); 1249 if (rv != 0) { 1250 device_printf(sc->dev, "Cannot enable FDT resources\n"); 1251 return (rv); 1252 } 1253 1254 /* Enable PLLE control. */ 1255 reg = AFI_RD4(sc, AFI_PLLE_CONTROL); 1256 reg &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 1257 reg |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 1258 AFI_WR4(sc, AFI_PLLE_CONTROL, reg); 1259 1260 /* Set bias pad. */ 1261 AFI_WR4(sc, AFI_PEXBIAS_CTRL, 0); 1262 1263 /* Configure mode and ports. */ 1264 reg = AFI_RD4(sc, AFI_PCIE_CONFIG); 1265 reg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 1266 if (sc->lanes_cfg == 0x14) { 1267 if (bootverbose) 1268 device_printf(sc->dev, 1269 "Using x1,x4 configuration\n"); 1270 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1; 1271 } else if (sc->lanes_cfg == 0x12) { 1272 if (bootverbose) 1273 device_printf(sc->dev, 1274 "Using x1,x2 configuration\n"); 1275 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1; 1276 } else { 1277 device_printf(sc->dev, 1278 "Unsupported lanes configuration: 0x%X\n", sc->lanes_cfg); 1279 } 1280 reg |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL; 1281 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1282 if ((sc->ports[i] != NULL)) 1283 reg &= 1284 ~AFI_PCIE_CONFIG_PCIE_DISABLE(sc->ports[i]->port_idx); 1285 } 1286 AFI_WR4(sc, AFI_PCIE_CONFIG, reg); 1287 1288 /* Enable Gen2 support. */ 1289 reg = AFI_RD4(sc, AFI_FUSE); 1290 reg &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 1291 AFI_WR4(sc, AFI_FUSE, reg); 1292 1293 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1294 if (sc->ports[i] != NULL) { 1295 rv = phy_enable(sc->ports[i]->phy); 1296 if (rv != 0) { 1297 device_printf(sc->dev, 1298 "Cannot enable phy for port %d\n", 1299 sc->ports[i]->port_idx); 1300 return (rv); 1301 } 1302 } 1303 } 1304 1305 /* Configure PCIe reference clock */ 1306 PADS_WR4(sc, PADS_REFCLK_CFG0, sc->soc->pads_refclk_cfg0); 1307 if (sc->num_ports > 2) 1308 PADS_WR4(sc, PADS_REFCLK_CFG1, sc->soc->pads_refclk_cfg1); 1309 1310 rv = hwreset_deassert(sc->hwreset_pcie_x); 1311 if (rv != 0) { 1312 device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n"); 1313 return (rv); 1314 } 1315 1316 /* Enable config space. */ 1317 reg = AFI_RD4(sc, AFI_CONFIGURATION); 1318 reg |= AFI_CONFIGURATION_EN_FPCI; 1319 AFI_WR4(sc, AFI_CONFIGURATION, reg); 1320 1321 /* Enable AFI errors. */ 1322 reg = 0; 1323 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_SLVERR); 1324 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_DECERR); 1325 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_SLVERR); 1326 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_DECERR); 1327 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_WRERR); 1328 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_SM_MSG); 1329 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_DFPCI_DECERR); 1330 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_AXI_DECERR); 1331 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT); 1332 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE); 1333 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE); 1334 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE); 1335 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE); 1336 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_P2P_ERROR); 1337 AFI_WR4(sc, AFI_AFI_INTR_ENABLE, reg); 1338 AFI_WR4(sc, AFI_SM_INTR_ENABLE, 0xffffffff); 1339 1340 /* Enable INT, disable MSI. */ 1341 AFI_WR4(sc, AFI_INTR_MASK, AFI_INTR_MASK_INT_MASK); 1342 1343 /* Mask all FPCI errors. */ 1344 AFI_WR4(sc, AFI_FPCI_ERROR_MASKS, 0); 1345 1346 /* Setup AFI translation windows. */ 1347 /* BAR 0 - type 1 extended configuration. */ 1348 tegra_pcib_set_bar(sc, 0, rman_get_start(sc->cfg_mem_res), 1349 FPCI_MAP_EXT_TYPE1_CONFIG, rman_get_size(sc->cfg_mem_res), 0); 1350 1351 /* BAR 1 - downstream I/O. */ 1352 tegra_pcib_set_bar(sc, 1, sc->io_range.host, FPCI_MAP_IO, 1353 sc->io_range.size, 0); 1354 1355 /* BAR 2 - downstream prefetchable memory 1:1. */ 1356 tegra_pcib_set_bar(sc, 2, sc->pref_mem_range.host, 1357 sc->pref_mem_range.host, sc->pref_mem_range.size, 1); 1358 1359 /* BAR 3 - downstream not prefetchable memory 1:1 .*/ 1360 tegra_pcib_set_bar(sc, 3, sc->mem_range.host, 1361 sc->mem_range.host, sc->mem_range.size, 1); 1362 1363 /* BAR 3-8 clear. */ 1364 tegra_pcib_set_bar(sc, 4, 0, 0, 0, 0); 1365 tegra_pcib_set_bar(sc, 5, 0, 0, 0, 0); 1366 tegra_pcib_set_bar(sc, 6, 0, 0, 0, 0); 1367 tegra_pcib_set_bar(sc, 7, 0, 0, 0, 0); 1368 tegra_pcib_set_bar(sc, 8, 0, 0, 0, 0); 1369 1370 /* MSI BAR - clear. */ 1371 tegra_pcib_set_bar(sc, 9, 0, 0, 0, 0); 1372 return(0); 1373 } 1374 1375 #ifdef TEGRA_PCIB_MSI_ENABLE 1376 static int 1377 tegra_pcib_attach_msi(device_t dev) 1378 { 1379 struct tegra_pcib_softc *sc; 1380 uint32_t reg; 1381 int i, rv; 1382 1383 sc = device_get_softc(dev); 1384 1385 sc->msi_page = (uintptr_t)kmem_alloc_contig(PAGE_SIZE, M_WAITOK, 0, 1386 BUS_SPACE_MAXADDR, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT); 1387 1388 /* MSI BAR */ 1389 tegra_pcib_set_bar(sc, 9, vtophys(sc->msi_page), vtophys(sc->msi_page), 1390 PAGE_SIZE, 0); 1391 1392 /* Disable and clear all interrupts. */ 1393 for (i = 0; i < AFI_MSI_REGS; i++) { 1394 AFI_WR4(sc, AFI_MSI_EN_VEC(i), 0); 1395 AFI_WR4(sc, AFI_MSI_VEC(i), 0xFFFFFFFF); 1396 } 1397 rv = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1398 tegra_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie); 1399 if (rv != 0) { 1400 device_printf(dev, "cannot setup MSI interrupt handler\n"); 1401 rv = ENXIO; 1402 goto out; 1403 } 1404 1405 if (tegra_pcib_msi_attach(sc) != 0) { 1406 device_printf(dev, "WARNING: unable to attach PIC\n"); 1407 tegra_pcib_msi_detach(sc); 1408 goto out; 1409 } 1410 1411 /* Unmask MSI interrupt. */ 1412 reg = AFI_RD4(sc, AFI_INTR_MASK); 1413 reg |= AFI_INTR_MASK_MSI_MASK; 1414 AFI_WR4(sc, AFI_INTR_MASK, reg); 1415 1416 out: 1417 return (rv); 1418 } 1419 #endif 1420 1421 static int 1422 tegra_pcib_probe(device_t dev) 1423 { 1424 if (!ofw_bus_status_okay(dev)) 1425 return (ENXIO); 1426 1427 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 1428 device_set_desc(dev, "Nvidia Integrated PCI/PCI-E Controller"); 1429 return (BUS_PROBE_DEFAULT); 1430 } 1431 return (ENXIO); 1432 } 1433 1434 static int 1435 tegra_pcib_attach(device_t dev) 1436 { 1437 struct tegra_pcib_softc *sc; 1438 phandle_t node; 1439 int rv; 1440 int rid; 1441 struct tegra_pcib_port *port; 1442 int i; 1443 1444 sc = device_get_softc(dev); 1445 sc->dev = dev; 1446 mtx_init(&sc->mtx, "msi_mtx", NULL, MTX_DEF); 1447 1448 node = ofw_bus_get_node(dev); 1449 sc->soc = (struct pcie_soc *)ofw_bus_search_compatible(dev, 1450 compat_data)->ocd_data; 1451 1452 rv = tegra_pcib_parse_fdt_resources(sc, node); 1453 if (rv != 0) { 1454 device_printf(dev, "Cannot get FDT resources\n"); 1455 return (rv); 1456 } 1457 1458 /* Allocate bus_space resources. */ 1459 rid = 0; 1460 sc->pads_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1461 RF_ACTIVE); 1462 if (sc->pads_mem_res == NULL) { 1463 device_printf(dev, "Cannot allocate PADS register\n"); 1464 rv = ENXIO; 1465 goto out; 1466 } 1467 /* 1468 * XXX - FIXME 1469 * tag for config space is not filled when RF_ALLOCATED flag is used. 1470 */ 1471 sc->bus_tag = rman_get_bustag(sc->pads_mem_res); 1472 1473 rid = 1; 1474 sc->afi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1475 RF_ACTIVE); 1476 if (sc->afi_mem_res == NULL) { 1477 device_printf(dev, "Cannot allocate AFI register\n"); 1478 rv = ENXIO; 1479 goto out; 1480 } 1481 1482 rid = 2; 1483 sc->cfg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1484 RF_ALLOCATED); 1485 if (sc->cfg_mem_res == NULL) { 1486 device_printf(dev, "Cannot allocate config space memory\n"); 1487 rv = ENXIO; 1488 goto out; 1489 } 1490 sc->cfg_base_addr = rman_get_start(sc->cfg_mem_res); 1491 1492 /* Map RP slots */ 1493 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1494 if (sc->ports[i] == NULL) 1495 continue; 1496 port = sc->ports[i]; 1497 rv = bus_space_map(sc->bus_tag, port->rp_base_addr, 1498 port->rp_size, 0, &port->cfg_handle); 1499 if (rv != 0) { 1500 device_printf(sc->dev, "Cannot allocate memory for " 1501 "port: %d\n", i); 1502 rv = ENXIO; 1503 goto out; 1504 } 1505 } 1506 1507 /* 1508 * Get PCI interrupt 1509 */ 1510 rid = 0; 1511 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1512 RF_ACTIVE | RF_SHAREABLE); 1513 if (sc->irq_res == NULL) { 1514 device_printf(dev, "Cannot allocate IRQ resources\n"); 1515 rv = ENXIO; 1516 goto out; 1517 } 1518 1519 rid = 1; 1520 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1521 RF_ACTIVE); 1522 if (sc->irq_res == NULL) { 1523 device_printf(dev, "Cannot allocate MSI IRQ resources\n"); 1524 rv = ENXIO; 1525 goto out; 1526 } 1527 1528 sc->ofw_pci.sc_range_mask = 0x3; 1529 rv = ofw_pcib_init(dev); 1530 if (rv != 0) 1531 goto out; 1532 1533 rv = tegra_pcib_decode_ranges(sc, sc->ofw_pci.sc_range, 1534 sc->ofw_pci.sc_nrange); 1535 if (rv != 0) 1536 goto out; 1537 1538 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1539 tegra_pci_intr, NULL, sc, &sc->intr_cookie)) { 1540 device_printf(dev, "cannot setup interrupt handler\n"); 1541 rv = ENXIO; 1542 goto out; 1543 } 1544 1545 /* 1546 * Enable PCIE device. 1547 */ 1548 rv = tegra_pcib_enable(sc); 1549 if (rv != 0) 1550 goto out; 1551 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1552 if (sc->ports[i] == NULL) 1553 continue; 1554 if (sc->ports[i]->enabled) 1555 tegra_pcib_port_enable(sc, i); 1556 else 1557 tegra_pcib_port_disable(sc, i); 1558 } 1559 1560 #ifdef TEGRA_PCIB_MSI_ENABLE 1561 rv = tegra_pcib_attach_msi(dev); 1562 if (rv != 0) 1563 goto out; 1564 #endif 1565 device_add_child(dev, "pci", -1); 1566 1567 return (bus_generic_attach(dev)); 1568 1569 out: 1570 1571 return (rv); 1572 } 1573 1574 static device_method_t tegra_pcib_methods[] = { 1575 /* Device interface */ 1576 DEVMETHOD(device_probe, tegra_pcib_probe), 1577 DEVMETHOD(device_attach, tegra_pcib_attach), 1578 1579 /* Bus interface */ 1580 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1581 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1582 1583 /* pcib interface */ 1584 DEVMETHOD(pcib_maxslots, tegra_pcib_maxslots), 1585 DEVMETHOD(pcib_read_config, tegra_pcib_read_config), 1586 DEVMETHOD(pcib_write_config, tegra_pcib_write_config), 1587 DEVMETHOD(pcib_route_interrupt, tegra_pcib_route_interrupt), 1588 DEVMETHOD(pcib_alloc_msi, tegra_pcib_alloc_msi), 1589 DEVMETHOD(pcib_release_msi, tegra_pcib_release_msi), 1590 DEVMETHOD(pcib_map_msi, tegra_pcib_map_msi), 1591 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 1592 1593 #ifdef TEGRA_PCIB_MSI_ENABLE 1594 /* MSI/MSI-X */ 1595 DEVMETHOD(msi_alloc_msi, tegra_pcib_msi_alloc_msi), 1596 DEVMETHOD(msi_release_msi, tegra_pcib_msi_release_msi), 1597 DEVMETHOD(msi_map_msi, tegra_pcib_msi_map_msi), 1598 1599 /* Interrupt controller interface */ 1600 DEVMETHOD(pic_disable_intr, tegra_pcib_msi_disable_intr), 1601 DEVMETHOD(pic_enable_intr, tegra_pcib_msi_enable_intr), 1602 DEVMETHOD(pic_setup_intr, tegra_pcib_msi_setup_intr), 1603 DEVMETHOD(pic_teardown_intr, tegra_pcib_msi_teardown_intr), 1604 DEVMETHOD(pic_post_filter, tegra_pcib_msi_post_filter), 1605 DEVMETHOD(pic_post_ithread, tegra_pcib_msi_post_ithread), 1606 DEVMETHOD(pic_pre_ithread, tegra_pcib_msi_pre_ithread), 1607 #endif 1608 1609 /* OFW bus interface */ 1610 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 1611 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 1612 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 1613 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 1614 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 1615 1616 DEVMETHOD_END 1617 }; 1618 1619 DEFINE_CLASS_1(pcib, tegra_pcib_driver, tegra_pcib_methods, 1620 sizeof(struct tegra_pcib_softc), ofw_pcib_driver); 1621 DRIVER_MODULE(tegra_pcib, simplebus, tegra_pcib_driver, NULL, NULL);
Cache object: 28545338412496953525028655a26281
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