1 /*-
2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 /*
31 * Nvidia Integrated PCI/PCI-Express controller driver.
32 */
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/devmap.h>
38 #include <sys/proc.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
43 #include <sys/rman.h>
44
45 #include <machine/intr.h>
46
47 #include <vm/vm.h>
48 #include <vm/vm_extern.h>
49 #include <vm/vm_kern.h>
50 #include <vm/pmap.h>
51
52 #include <dev/extres/clk/clk.h>
53 #include <dev/extres/hwreset/hwreset.h>
54 #include <dev/extres/phy/phy.h>
55 #include <dev/extres/regulator/regulator.h>
56 #include <dev/ofw/ofw_bus.h>
57 #include <dev/ofw/ofw_bus_subr.h>
58 #include <dev/ofw/ofw_pci.h>
59 #include <dev/ofw/ofwpci.h>
60 #include <dev/pci/pcivar.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcib_private.h>
63
64 #include <machine/resource.h>
65 #include <machine/bus.h>
66
67 #include <arm/nvidia/tegra_pmc.h>
68
69 #include "ofw_bus_if.h"
70 #include "msi_if.h"
71 #include "pcib_if.h"
72 #include "pic_if.h"
73
74 #define AFI_AXI_BAR0_SZ 0x000
75 #define AFI_AXI_BAR1_SZ 0x004
76 #define AFI_AXI_BAR2_SZ 0x008
77 #define AFI_AXI_BAR3_SZ 0x00c
78 #define AFI_AXI_BAR4_SZ 0x010
79 #define AFI_AXI_BAR5_SZ 0x014
80 #define AFI_AXI_BAR0_START 0x018
81 #define AFI_AXI_BAR1_START 0x01c
82 #define AFI_AXI_BAR2_START 0x020
83 #define AFI_AXI_BAR3_START 0x024
84 #define AFI_AXI_BAR4_START 0x028
85 #define AFI_AXI_BAR5_START 0x02c
86 #define AFI_FPCI_BAR0 0x030
87 #define AFI_FPCI_BAR1 0x034
88 #define AFI_FPCI_BAR2 0x038
89 #define AFI_FPCI_BAR3 0x03c
90 #define AFI_FPCI_BAR4 0x040
91 #define AFI_FPCI_BAR5 0x044
92 #define AFI_MSI_BAR_SZ 0x060
93 #define AFI_MSI_FPCI_BAR_ST 0x064
94 #define AFI_MSI_AXI_BAR_ST 0x068
95 #define AFI_MSI_VEC(x) (0x06c + 4 * (x))
96 #define AFI_MSI_EN_VEC(x) (0x08c + 4 * (x))
97 #define AFI_MSI_INTR_IN_REG 32
98 #define AFI_MSI_REGS 8
99
100 #define AFI_CONFIGURATION 0x0ac
101 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
102
103 #define AFI_FPCI_ERROR_MASKS 0x0b0
104 #define AFI_INTR_MASK 0x0b4
105 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
106 #define AFI_INTR_MASK_INT_MASK (1 << 0)
107
108 #define AFI_INTR_CODE 0x0b8
109 #define AFI_INTR_CODE_MASK 0xf
110 #define AFI_INTR_CODE_INT_CODE_INI_SLVERR 1
111 #define AFI_INTR_CODE_INT_CODE_INI_DECERR 2
112 #define AFI_INTR_CODE_INT_CODE_TGT_SLVERR 3
113 #define AFI_INTR_CODE_INT_CODE_TGT_DECERR 4
114 #define AFI_INTR_CODE_INT_CODE_TGT_WRERR 5
115 #define AFI_INTR_CODE_INT_CODE_SM_MSG 6
116 #define AFI_INTR_CODE_INT_CODE_DFPCI_DECERR 7
117 #define AFI_INTR_CODE_INT_CODE_AXI_DECERR 8
118 #define AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT 9
119 #define AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE 10
120 #define AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE 11
121 #define AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE 12
122 #define AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE 13
123 #define AFI_INTR_CODE_INT_CODE_P2P_ERROR 14
124
125 #define AFI_INTR_SIGNATURE 0x0bc
126 #define AFI_UPPER_FPCI_ADDRESS 0x0c0
127 #define AFI_SM_INTR_ENABLE 0x0c4
128 #define AFI_SM_INTR_RP_DEASSERT (1 << 14)
129 #define AFI_SM_INTR_RP_ASSERT (1 << 13)
130 #define AFI_SM_INTR_HOTPLUG (1 << 12)
131 #define AFI_SM_INTR_PME (1 << 11)
132 #define AFI_SM_INTR_FATAL_ERROR (1 << 10)
133 #define AFI_SM_INTR_UNCORR_ERROR (1 << 9)
134 #define AFI_SM_INTR_CORR_ERROR (1 << 8)
135 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
136 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
137 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
138 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
139 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
140 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
141 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
142 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
143
144 #define AFI_AFI_INTR_ENABLE 0x0c8
145 #define AFI_AFI_INTR_ENABLE_CODE(code) (1 << (code))
146
147 #define AFI_PCIE_CONFIG 0x0f8
148 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
149 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0x6
150 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
151 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1 (0x0 << 20)
152 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1 (0x1 << 20)
153
154 #define AFI_FUSE 0x104
155 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
156
157 #define AFI_PEX0_CTRL 0x110
158 #define AFI_PEX1_CTRL 0x118
159 #define AFI_PEX2_CTRL 0x128
160 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
161 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
162 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
163 #define AFI_PEX_CTRL_RST_L (1 << 0)
164
165 #define AFI_AXI_BAR6_SZ 0x134
166 #define AFI_AXI_BAR7_SZ 0x138
167 #define AFI_AXI_BAR8_SZ 0x13c
168 #define AFI_AXI_BAR6_START 0x140
169 #define AFI_AXI_BAR7_START 0x144
170 #define AFI_AXI_BAR8_START 0x148
171 #define AFI_FPCI_BAR6 0x14c
172 #define AFI_FPCI_BAR7 0x150
173 #define AFI_FPCI_BAR8 0x154
174 #define AFI_PLLE_CONTROL 0x160
175 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
176 #define AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL (1 << 8)
177 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
178 #define AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN (1 << 0)
179
180 #define AFI_PEXBIAS_CTRL 0x168
181
182 /* Configuration space */
183 #define RP_VEND_XP 0x0F00
184 #define RP_VEND_XP_DL_UP (1 << 30)
185
186 #define RP_VEND_CTL2 0x0fa8
187 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
188
189 #define RP_PRIV_MISC 0x0FE0
190 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
191 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
192
193 #define RP_LINK_CONTROL_STATUS 0x0090
194 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
195 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
196
197 /* PADS space */
198 #define PADS_REFCLK_CFG0 0x000c8
199 #define PADS_REFCLK_CFG1 0x000cc
200
201
202 /* Wait 50 ms (per port) for link. */
203 #define TEGRA_PCIE_LINKUP_TIMEOUT 50000
204
205 /* FPCI Address space */
206 #define FPCI_MAP_IO 0xFDFC000000ULL
207 #define FPCI_MAP_TYPE0_CONFIG 0xFDFC000000ULL
208 #define FPCI_MAP_TYPE1_CONFIG 0xFDFF000000ULL
209 #define FPCI_MAP_EXT_TYPE0_CONFIG 0xFE00000000ULL
210 #define FPCI_MAP_EXT_TYPE1_CONFIG 0xFE10000000ULL
211
212 #define TEGRA_PCIB_MSI_ENABLE
213
214 #define DEBUG
215 #ifdef DEBUG
216 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0)
217 #else
218 #define debugf(fmt, args...)
219 #endif
220
221 /*
222 * Configuration space format:
223 * [27:24] extended register
224 * [23:16] bus
225 * [15:11] slot (device)
226 * [10: 8] function
227 * [ 7: 0] register
228 */
229 #define PCI_CFG_EXT_REG(reg) ((((reg) >> 8) & 0x0f) << 24)
230 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16)
231 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11)
232 #define PCI_CFG_FUN(fun) (((fun) & 0x07) << 8)
233 #define PCI_CFG_BASE_REG(reg) ((reg) & 0xff)
234
235 #define PADS_WR4(_sc, _r, _v) bus_write_4((_sc)->pads_mem_res, (_r), (_v))
236 #define PADS_RD4(_sc, _r) bus_read_4((_sc)->pads_mem_res, (_r))
237 #define AFI_WR4(_sc, _r, _v) bus_write_4((_sc)->afi_mem_res, (_r), (_v))
238 #define AFI_RD4(_sc, _r) bus_read_4((_sc)->afi_mem_res, (_r))
239
240 static struct {
241 bus_size_t axi_start;
242 bus_size_t fpci_start;
243 bus_size_t size;
244 } bars[] = {
245 {AFI_AXI_BAR0_START, AFI_FPCI_BAR0, AFI_AXI_BAR0_SZ}, /* BAR 0 */
246 {AFI_AXI_BAR1_START, AFI_FPCI_BAR1, AFI_AXI_BAR1_SZ}, /* BAR 1 */
247 {AFI_AXI_BAR2_START, AFI_FPCI_BAR2, AFI_AXI_BAR2_SZ}, /* BAR 2 */
248 {AFI_AXI_BAR3_START, AFI_FPCI_BAR3, AFI_AXI_BAR3_SZ}, /* BAR 3 */
249 {AFI_AXI_BAR4_START, AFI_FPCI_BAR4, AFI_AXI_BAR4_SZ}, /* BAR 4 */
250 {AFI_AXI_BAR5_START, AFI_FPCI_BAR5, AFI_AXI_BAR5_SZ}, /* BAR 5 */
251 {AFI_AXI_BAR6_START, AFI_FPCI_BAR6, AFI_AXI_BAR6_SZ}, /* BAR 6 */
252 {AFI_AXI_BAR7_START, AFI_FPCI_BAR7, AFI_AXI_BAR7_SZ}, /* BAR 7 */
253 {AFI_AXI_BAR8_START, AFI_FPCI_BAR8, AFI_AXI_BAR8_SZ}, /* BAR 8 */
254 {AFI_MSI_AXI_BAR_ST, AFI_MSI_FPCI_BAR_ST, AFI_MSI_BAR_SZ}, /* MSI 9 */
255 };
256
257
258 struct pcie_soc {
259 char **regulator_names;
260 bool cml_clk;
261 bool pca_enable;
262 uint32_t pads_refclk_cfg0;
263 uint32_t pads_refclk_cfg1;
264 };
265
266 /* Tegra 124 config. */
267 static char *tegra124_reg_names[] = {
268 "avddio-pex-supply",
269 "dvddio-pex-supply",
270 "avdd-pex-pll-supply",
271 "hvdd-pex-supply",
272 "hvdd-pex-pll-e-supply",
273 "vddio-pex-ctl-supply",
274 "avdd-pll-erefe-supply",
275 NULL
276 };
277
278 static struct pcie_soc tegra124_soc = {
279 .regulator_names = tegra124_reg_names,
280 .cml_clk = true,
281 .pca_enable = false,
282 .pads_refclk_cfg0 = 0x44ac44ac,
283 };
284
285 /* Tegra 210 config. */
286 static char *tegra210_reg_names[] = {
287 "avdd-pll-uerefe-supply",
288 "hvddio-pex-supply",
289 "dvddio-pex-supply",
290 "dvdd-pex-pll-supply",
291 "hvdd-pex-pll-e-supply",
292 "vddio-pex-ctl-supply",
293 NULL
294 };
295
296 static struct pcie_soc tegra210_soc = {
297 .regulator_names = tegra210_reg_names,
298 .cml_clk = true,
299 .pca_enable = true,
300 .pads_refclk_cfg0 = 0x90b890b8,
301 };
302
303 /* Compatible devices. */
304 static struct ofw_compat_data compat_data[] = {
305 {"nvidia,tegra124-pcie", (uintptr_t)&tegra124_soc},
306 {"nvidia,tegra210-pcie", (uintptr_t)&tegra210_soc},
307 {NULL, 0},
308 };
309
310 #define TEGRA_FLAG_MSI_USED 0x0001
311 struct tegra_pcib_irqsrc {
312 struct intr_irqsrc isrc;
313 u_int irq;
314 u_int flags;
315 };
316
317 struct tegra_pcib_port {
318 int enabled;
319 int port_idx; /* chip port index */
320 int num_lanes; /* number of lanes */
321 bus_size_t afi_pex_ctrl; /* offset of afi_pex_ctrl */
322 phy_t phy; /* port phy */
323
324 /* Config space properties. */
325 bus_addr_t rp_base_addr; /* PA of config window */
326 bus_size_t rp_size; /* size of config window */
327 bus_space_handle_t cfg_handle; /* handle of config window */
328 };
329
330 #define TEGRA_PCIB_MAX_PORTS 3
331 #define TEGRA_PCIB_MAX_MSI AFI_MSI_INTR_IN_REG * AFI_MSI_REGS
332 struct tegra_pcib_softc {
333 struct ofw_pci_softc ofw_pci;
334 device_t dev;
335 struct pcie_soc *soc;
336 struct mtx mtx;
337 struct resource *pads_mem_res;
338 struct resource *afi_mem_res;
339 struct resource *cfg_mem_res;
340 struct resource *irq_res;
341 struct resource *msi_irq_res;
342 void *intr_cookie;
343 void *msi_intr_cookie;
344
345 struct ofw_pci_range mem_range;
346 struct ofw_pci_range pref_mem_range;
347 struct ofw_pci_range io_range;
348
349 clk_t clk_pex;
350 clk_t clk_afi;
351 clk_t clk_pll_e;
352 clk_t clk_cml;
353 hwreset_t hwreset_pex;
354 hwreset_t hwreset_afi;
355 hwreset_t hwreset_pcie_x;
356 regulator_t regulators[16]; /* Safe maximum */
357
358 vm_offset_t msi_page; /* VA of MSI page */
359 bus_addr_t cfg_base_addr; /* base address of config */
360 bus_size_t cfg_cur_offs; /* currently mapped window */
361 bus_space_handle_t cfg_handle; /* handle of config window */
362 bus_space_tag_t bus_tag; /* tag of config window */
363 int lanes_cfg;
364 int num_ports;
365 struct tegra_pcib_port *ports[TEGRA_PCIB_MAX_PORTS];
366 struct tegra_pcib_irqsrc *isrcs;
367 };
368
369 static int
370 tegra_pcib_maxslots(device_t dev)
371 {
372 return (16);
373 }
374
375 static int
376 tegra_pcib_route_interrupt(device_t bus, device_t dev, int pin)
377 {
378 struct tegra_pcib_softc *sc;
379 u_int irq;
380
381 sc = device_get_softc(bus);
382 irq = intr_map_clone_irq(rman_get_start(sc->irq_res));
383 device_printf(bus, "route pin %d for device %d.%d to %u\n",
384 pin, pci_get_slot(dev), pci_get_function(dev),
385 irq);
386
387 return (irq);
388 }
389
390 static int
391 tegra_pcbib_map_cfg(struct tegra_pcib_softc *sc, u_int bus, u_int slot,
392 u_int func, u_int reg)
393 {
394 bus_size_t offs;
395 int rv;
396
397 offs = sc->cfg_base_addr;
398 offs |= PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | PCI_CFG_FUN(func) |
399 PCI_CFG_EXT_REG(reg);
400 if ((sc->cfg_handle != 0) && (sc->cfg_cur_offs == offs))
401 return (0);
402 if (sc->cfg_handle != 0)
403 bus_space_unmap(sc->bus_tag, sc->cfg_handle, 0x800);
404
405 rv = bus_space_map(sc->bus_tag, offs, 0x800, 0, &sc->cfg_handle);
406 if (rv != 0)
407 device_printf(sc->dev, "Cannot map config space\n");
408 else
409 sc->cfg_cur_offs = offs;
410 return (rv);
411 }
412
413 static uint32_t
414 tegra_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
415 u_int reg, int bytes)
416 {
417 struct tegra_pcib_softc *sc;
418 bus_space_handle_t hndl;
419 uint32_t off;
420 uint32_t val;
421 int rv, i;
422
423 sc = device_get_softc(dev);
424 if (bus == 0) {
425 if (func != 0)
426 return (0xFFFFFFFF);
427 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
428 if ((sc->ports[i] != NULL) &&
429 (sc->ports[i]->port_idx == slot)) {
430 hndl = sc->ports[i]->cfg_handle;
431 off = reg & 0xFFF;
432 break;
433 }
434 }
435 if (i >= TEGRA_PCIB_MAX_PORTS)
436 return (0xFFFFFFFF);
437 } else {
438 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg);
439 if (rv != 0)
440 return (0xFFFFFFFF);
441 hndl = sc->cfg_handle;
442 off = PCI_CFG_BASE_REG(reg);
443 }
444
445 val = bus_space_read_4(sc->bus_tag, hndl, off & ~3);
446 switch (bytes) {
447 case 4:
448 break;
449 case 2:
450 if (off & 3)
451 val >>= 16;
452 val &= 0xffff;
453 break;
454 case 1:
455 val >>= ((off & 3) << 3);
456 val &= 0xff;
457 break;
458 }
459 return val;
460 }
461
462 static void
463 tegra_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
464 u_int reg, uint32_t val, int bytes)
465 {
466 struct tegra_pcib_softc *sc;
467 bus_space_handle_t hndl;
468 uint32_t off;
469 uint32_t val2;
470 int rv, i;
471
472 sc = device_get_softc(dev);
473 if (bus == 0) {
474 if (func != 0)
475 return;
476 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
477 if ((sc->ports[i] != NULL) &&
478 (sc->ports[i]->port_idx == slot)) {
479 hndl = sc->ports[i]->cfg_handle;
480 off = reg & 0xFFF;
481 break;
482 }
483 }
484 if (i >= TEGRA_PCIB_MAX_PORTS)
485 return;
486 } else {
487 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg);
488 if (rv != 0)
489 return;
490 hndl = sc->cfg_handle;
491 off = PCI_CFG_BASE_REG(reg);
492 }
493
494 switch (bytes) {
495 case 4:
496 bus_space_write_4(sc->bus_tag, hndl, off, val);
497 break;
498 case 2:
499 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3);
500 val2 &= ~(0xffff << ((off & 3) << 3));
501 val2 |= ((val & 0xffff) << ((off & 3) << 3));
502 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2);
503 break;
504 case 1:
505 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3);
506 val2 &= ~(0xff << ((off & 3) << 3));
507 val2 |= ((val & 0xff) << ((off & 3) << 3));
508 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2);
509 break;
510 }
511 }
512
513 static int tegra_pci_intr(void *arg)
514 {
515 struct tegra_pcib_softc *sc = arg;
516 uint32_t code, signature;
517
518 code = bus_read_4(sc->afi_mem_res, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
519 signature = bus_read_4(sc->afi_mem_res, AFI_INTR_SIGNATURE);
520 bus_write_4(sc->afi_mem_res, AFI_INTR_CODE, 0);
521 if (code == AFI_INTR_CODE_INT_CODE_SM_MSG)
522 return(FILTER_STRAY);
523
524 printf("tegra_pci_intr: code %x sig %x\n", code, signature);
525 return (FILTER_HANDLED);
526 }
527
528 /* -----------------------------------------------------------------------
529 *
530 * PCI MSI interface
531 */
532 static int
533 tegra_pcib_alloc_msi(device_t pci, device_t child, int count, int maxcount,
534 int *irqs)
535 {
536 phandle_t msi_parent;
537
538 /* XXXX ofw_bus_msimap() don't works for Tegra DT.
539 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent,
540 NULL);
541 */
542 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci));
543 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount,
544 irqs));
545 }
546
547 static int
548 tegra_pcib_release_msi(device_t pci, device_t child, int count, int *irqs)
549 {
550 phandle_t msi_parent;
551
552 /* XXXX ofw_bus_msimap() don't works for Tegra DT.
553 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent,
554 NULL);
555 */
556 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci));
557 return (intr_release_msi(pci, child, msi_parent, count, irqs));
558 }
559
560 static int
561 tegra_pcib_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
562 uint32_t *data)
563 {
564 phandle_t msi_parent;
565
566 /* XXXX ofw_bus_msimap() don't works for Tegra DT.
567 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent,
568 NULL);
569 */
570 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci));
571 return (intr_map_msi(pci, child, msi_parent, irq, addr, data));
572 }
573
574 #ifdef TEGRA_PCIB_MSI_ENABLE
575
576 /* --------------------------------------------------------------------------
577 *
578 * Interrupts
579 *
580 */
581
582 static inline void
583 tegra_pcib_isrc_mask(struct tegra_pcib_softc *sc,
584 struct tegra_pcib_irqsrc *tgi, uint32_t val)
585 {
586 uint32_t reg;
587 int offs, bit;
588
589 offs = tgi->irq / AFI_MSI_INTR_IN_REG;
590 bit = 1 << (tgi->irq % AFI_MSI_INTR_IN_REG);
591
592 if (val != 0)
593 AFI_WR4(sc, AFI_MSI_VEC(offs), bit);
594 reg = AFI_RD4(sc, AFI_MSI_EN_VEC(offs));
595 if (val != 0)
596 reg |= bit;
597 else
598 reg &= ~bit;
599 AFI_WR4(sc, AFI_MSI_EN_VEC(offs), reg);
600 }
601
602 static int
603 tegra_pcib_msi_intr(void *arg)
604 {
605 u_int irq, i, bit, reg;
606 struct tegra_pcib_softc *sc;
607 struct trapframe *tf;
608 struct tegra_pcib_irqsrc *tgi;
609
610 sc = (struct tegra_pcib_softc *)arg;
611 tf = curthread->td_intr_frame;
612
613 for (i = 0; i < AFI_MSI_REGS; i++) {
614 reg = AFI_RD4(sc, AFI_MSI_VEC(i));
615 /* Handle one vector. */
616 while (reg != 0) {
617 bit = ffs(reg) - 1;
618 /* Send EOI */
619 AFI_WR4(sc, AFI_MSI_VEC(i), 1 << bit);
620 irq = i * AFI_MSI_INTR_IN_REG + bit;
621 tgi = &sc->isrcs[irq];
622 if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) {
623 /* Disable stray. */
624 tegra_pcib_isrc_mask(sc, tgi, 0);
625 device_printf(sc->dev,
626 "Stray irq %u disabled\n", irq);
627 }
628 reg = AFI_RD4(sc, AFI_MSI_VEC(i));
629 }
630 }
631 return (FILTER_HANDLED);
632 }
633
634 static int
635 tegra_pcib_msi_attach(struct tegra_pcib_softc *sc)
636 {
637 int error;
638 uint32_t irq;
639 const char *name;
640
641 sc->isrcs = malloc(sizeof(*sc->isrcs) * TEGRA_PCIB_MAX_MSI, M_DEVBUF,
642 M_WAITOK | M_ZERO);
643
644 name = device_get_nameunit(sc->dev);
645 for (irq = 0; irq < TEGRA_PCIB_MAX_MSI; irq++) {
646 sc->isrcs[irq].irq = irq;
647 error = intr_isrc_register(&sc->isrcs[irq].isrc,
648 sc->dev, 0, "%s,%u", name, irq);
649 if (error != 0)
650 return (error); /* XXX deregister ISRCs */
651 }
652 if (intr_msi_register(sc->dev,
653 OF_xref_from_node(ofw_bus_get_node(sc->dev))) != 0)
654 return (ENXIO);
655
656 return (0);
657 }
658
659 static int
660 tegra_pcib_msi_detach(struct tegra_pcib_softc *sc)
661 {
662
663 /*
664 * There has not been established any procedure yet
665 * how to detach PIC from living system correctly.
666 */
667 device_printf(sc->dev, "%s: not implemented yet\n", __func__);
668 return (EBUSY);
669 }
670
671 static void
672 tegra_pcib_msi_disable_intr(device_t dev, struct intr_irqsrc *isrc)
673 {
674 struct tegra_pcib_softc *sc;
675 struct tegra_pcib_irqsrc *tgi;
676
677 sc = device_get_softc(dev);
678 tgi = (struct tegra_pcib_irqsrc *)isrc;
679 tegra_pcib_isrc_mask(sc, tgi, 0);
680 }
681
682 static void
683 tegra_pcib_msi_enable_intr(device_t dev, struct intr_irqsrc *isrc)
684 {
685 struct tegra_pcib_softc *sc;
686 struct tegra_pcib_irqsrc *tgi;
687
688 sc = device_get_softc(dev);
689 tgi = (struct tegra_pcib_irqsrc *)isrc;
690 tegra_pcib_isrc_mask(sc, tgi, 1);
691 }
692
693 /* MSI interrupts are edge trigered -> do nothing */
694 static void
695 tegra_pcib_msi_post_filter(device_t dev, struct intr_irqsrc *isrc)
696 {
697 }
698
699 static void
700 tegra_pcib_msi_post_ithread(device_t dev, struct intr_irqsrc *isrc)
701 {
702 }
703
704 static void
705 tegra_pcib_msi_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
706 {
707 }
708
709 static int
710 tegra_pcib_msi_setup_intr(device_t dev, struct intr_irqsrc *isrc,
711 struct resource *res, struct intr_map_data *data)
712 {
713 struct tegra_pcib_softc *sc;
714 struct tegra_pcib_irqsrc *tgi;
715
716 sc = device_get_softc(dev);
717 tgi = (struct tegra_pcib_irqsrc *)isrc;
718
719 if (data == NULL || data->type != INTR_MAP_DATA_MSI)
720 return (ENOTSUP);
721
722 if (isrc->isrc_handlers == 0)
723 tegra_pcib_msi_enable_intr(dev, isrc);
724
725 return (0);
726 }
727
728 static int
729 tegra_pcib_msi_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
730 struct resource *res, struct intr_map_data *data)
731 {
732 struct tegra_pcib_softc *sc;
733 struct tegra_pcib_irqsrc *tgi;
734
735 sc = device_get_softc(dev);
736 tgi = (struct tegra_pcib_irqsrc *)isrc;
737
738 if (isrc->isrc_handlers == 0)
739 tegra_pcib_isrc_mask(sc, tgi, 0);
740 return (0);
741 }
742
743 static int
744 tegra_pcib_msi_alloc_msi(device_t dev, device_t child, int count, int maxcount,
745 device_t *pic, struct intr_irqsrc **srcs)
746 {
747 struct tegra_pcib_softc *sc;
748 int i, irq, end_irq;
749 bool found;
750
751 KASSERT(powerof2(count), ("%s: bad count", __func__));
752 KASSERT(powerof2(maxcount), ("%s: bad maxcount", __func__));
753
754 sc = device_get_softc(dev);
755 mtx_lock(&sc->mtx);
756
757 found = false;
758 for (irq = 0; (irq + count - 1) < TEGRA_PCIB_MAX_MSI; irq++) {
759 /* Start on an aligned interrupt */
760 if ((irq & (maxcount - 1)) != 0)
761 continue;
762
763 /* Assume we found a valid range until shown otherwise */
764 found = true;
765
766 /* Check this range is valid */
767 for (end_irq = irq; end_irq < irq + count; end_irq++) {
768 /* This is already used */
769 if ((sc->isrcs[end_irq].flags & TEGRA_FLAG_MSI_USED) ==
770 TEGRA_FLAG_MSI_USED) {
771 found = false;
772 break;
773 }
774 }
775
776 if (found)
777 break;
778 }
779
780 /* Not enough interrupts were found */
781 if (!found || irq == (TEGRA_PCIB_MAX_MSI - 1)) {
782 mtx_unlock(&sc->mtx);
783 return (ENXIO);
784 }
785
786 for (i = 0; i < count; i++) {
787 /* Mark the interrupt as used */
788 sc->isrcs[irq + i].flags |= TEGRA_FLAG_MSI_USED;
789 }
790 mtx_unlock(&sc->mtx);
791
792 for (i = 0; i < count; i++)
793 srcs[i] = (struct intr_irqsrc *)&sc->isrcs[irq + i];
794 *pic = device_get_parent(dev);
795 return (0);
796 }
797
798 static int
799 tegra_pcib_msi_release_msi(device_t dev, device_t child, int count,
800 struct intr_irqsrc **isrc)
801 {
802 struct tegra_pcib_softc *sc;
803 struct tegra_pcib_irqsrc *ti;
804 int i;
805
806 sc = device_get_softc(dev);
807 mtx_lock(&sc->mtx);
808 for (i = 0; i < count; i++) {
809 ti = (struct tegra_pcib_irqsrc *)isrc[i];
810
811 KASSERT((ti->flags & TEGRA_FLAG_MSI_USED) == TEGRA_FLAG_MSI_USED,
812 ("%s: Trying to release an unused MSI-X interrupt",
813 __func__));
814
815 ti->flags &= ~TEGRA_FLAG_MSI_USED;
816 }
817 mtx_unlock(&sc->mtx);
818 return (0);
819 }
820
821 static int
822 tegra_pcib_msi_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
823 uint64_t *addr, uint32_t *data)
824 {
825 struct tegra_pcib_softc *sc = device_get_softc(dev);
826 struct tegra_pcib_irqsrc *ti = (struct tegra_pcib_irqsrc *)isrc;
827
828 *addr = vtophys(sc->msi_page);
829 *data = ti->irq;
830 return (0);
831 }
832 #endif
833
834 /* ------------------------------------------------------------------- */
835 static bus_size_t
836 tegra_pcib_pex_ctrl(struct tegra_pcib_softc *sc, int port)
837 {
838 if (port >= TEGRA_PCIB_MAX_PORTS)
839 panic("invalid port number: %d\n", port);
840
841 if (port == 0)
842 return (AFI_PEX0_CTRL);
843 else if (port == 1)
844 return (AFI_PEX1_CTRL);
845 else if (port == 2)
846 return (AFI_PEX2_CTRL);
847 else
848 panic("invalid port number: %d\n", port);
849 }
850
851 static int
852 tegra_pcib_enable_fdt_resources(struct tegra_pcib_softc *sc)
853 {
854 int i, rv;
855
856 rv = hwreset_assert(sc->hwreset_pcie_x);
857 if (rv != 0) {
858 device_printf(sc->dev, "Cannot assert 'pcie_x' reset\n");
859 return (rv);
860 }
861 rv = hwreset_assert(sc->hwreset_afi);
862 if (rv != 0) {
863 device_printf(sc->dev, "Cannot assert 'afi' reset\n");
864 return (rv);
865 }
866 rv = hwreset_assert(sc->hwreset_pex);
867 if (rv != 0) {
868 device_printf(sc->dev, "Cannot assert 'pex' reset\n");
869 return (rv);
870 }
871
872 tegra_powergate_power_off(TEGRA_POWERGATE_PCX);
873
874 /* Regulators. */
875 for (i = 0; i < nitems(sc->regulators); i++) {
876 if (sc->regulators[i] == NULL)
877 continue;
878 rv = regulator_enable(sc->regulators[i]);
879 if (rv != 0) {
880 device_printf(sc->dev,
881 "Cannot enable '%s' regulator\n",
882 sc->soc->regulator_names[i]);
883 return (rv);
884 }
885 }
886
887 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCX,
888 sc->clk_pex, sc->hwreset_pex);
889 if (rv != 0) {
890 device_printf(sc->dev, "Cannot enable 'PCX' powergate\n");
891 return (rv);
892 }
893
894 rv = hwreset_deassert(sc->hwreset_afi);
895 if (rv != 0) {
896 device_printf(sc->dev, "Cannot unreset 'afi' reset\n");
897 return (rv);
898 }
899
900 rv = clk_enable(sc->clk_afi);
901 if (rv != 0) {
902 device_printf(sc->dev, "Cannot enable 'afi' clock\n");
903 return (rv);
904 }
905 if (sc->soc->cml_clk) {
906 rv = clk_enable(sc->clk_cml);
907 if (rv != 0) {
908 device_printf(sc->dev, "Cannot enable 'cml' clock\n");
909 return (rv);
910 }
911 }
912 rv = clk_enable(sc->clk_pll_e);
913 if (rv != 0) {
914 device_printf(sc->dev, "Cannot enable 'pll_e' clock\n");
915 return (rv);
916 }
917
918 return (0);
919 }
920
921 static struct tegra_pcib_port *
922 tegra_pcib_parse_port(struct tegra_pcib_softc *sc, phandle_t node)
923 {
924 struct tegra_pcib_port *port;
925 uint32_t tmp[5];
926 char tmpstr[6];
927 int rv;
928
929 port = malloc(sizeof(struct tegra_pcib_port), M_DEVBUF, M_WAITOK);
930
931 rv = OF_getprop(node, "status", tmpstr, sizeof(tmpstr));
932 if (rv <= 0 || strcmp(tmpstr, "okay") == 0 ||
933 strcmp(tmpstr, "ok") == 0)
934 port->enabled = 1;
935 else
936 port->enabled = 0;
937
938 rv = OF_getencprop(node, "assigned-addresses", tmp, sizeof(tmp));
939 if (rv != sizeof(tmp)) {
940 device_printf(sc->dev, "Cannot parse assigned-address: %d\n",
941 rv);
942 goto fail;
943 }
944 port->rp_base_addr = tmp[2];
945 port->rp_size = tmp[4];
946 port->port_idx = OFW_PCI_PHYS_HI_DEVICE(tmp[0]) - 1;
947 if (port->port_idx >= TEGRA_PCIB_MAX_PORTS) {
948 device_printf(sc->dev, "Invalid port index: %d\n",
949 port->port_idx);
950 goto fail;
951 }
952 /* XXX - TODO:
953 * Implement proper function for parsing pci "reg" property:
954 * - it have PCI bus format
955 * - its relative to matching "assigned-addresses"
956 */
957 rv = OF_getencprop(node, "reg", tmp, sizeof(tmp));
958 if (rv != sizeof(tmp)) {
959 device_printf(sc->dev, "Cannot parse reg: %d\n", rv);
960 goto fail;
961 }
962 port->rp_base_addr += tmp[2];
963
964 rv = OF_getencprop(node, "nvidia,num-lanes", &port->num_lanes,
965 sizeof(port->num_lanes));
966 if (rv != sizeof(port->num_lanes)) {
967 device_printf(sc->dev, "Cannot parse nvidia,num-lanes: %d\n",
968 rv);
969 goto fail;
970 }
971 if (port->num_lanes > 4) {
972 device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n",
973 port->num_lanes);
974 goto fail;
975 }
976
977 port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx);
978 sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx);
979
980 /* Phy. */
981 rv = phy_get_by_ofw_name(sc->dev, node, "pcie-0", &port->phy);
982 if (rv != 0) {
983 device_printf(sc->dev,
984 "Cannot get 'pcie-0' phy for port %d\n",
985 port->port_idx);
986 goto fail;
987 }
988
989 return (port);
990 fail:
991 free(port, M_DEVBUF);
992 return (NULL);
993 }
994
995 static int
996 tegra_pcib_parse_fdt_resources(struct tegra_pcib_softc *sc, phandle_t node)
997 {
998 phandle_t child;
999 struct tegra_pcib_port *port;
1000 int i, rv;
1001
1002 /* Regulators. */
1003 for (i = 0; sc->soc->regulator_names[i] != NULL; i++) {
1004 if (i >= nitems(sc->regulators)) {
1005 device_printf(sc->dev,
1006 "Too many regulators present in DT.\n");
1007 return (EOVERFLOW);
1008 }
1009 rv = regulator_get_by_ofw_property(sc->dev, 0,
1010 sc->soc->regulator_names[i], sc->regulators + i);
1011 if (rv != 0) {
1012 device_printf(sc->dev,
1013 "Cannot get '%s' regulator\n",
1014 sc->soc->regulator_names[i]);
1015 return (ENXIO);
1016 }
1017 }
1018
1019 /* Resets. */
1020 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pex", &sc->hwreset_pex);
1021 if (rv != 0) {
1022 device_printf(sc->dev, "Cannot get 'pex' reset\n");
1023 return (ENXIO);
1024 }
1025 rv = hwreset_get_by_ofw_name(sc->dev, 0, "afi", &sc->hwreset_afi);
1026 if (rv != 0) {
1027 device_printf(sc->dev, "Cannot get 'afi' reset\n");
1028 return (ENXIO);
1029 }
1030 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pcie_x", &sc->hwreset_pcie_x);
1031 if (rv != 0) {
1032 device_printf(sc->dev, "Cannot get 'pcie_x' reset\n");
1033 return (ENXIO);
1034 }
1035
1036 /* Clocks. */
1037 rv = clk_get_by_ofw_name(sc->dev, 0, "pex", &sc->clk_pex);
1038 if (rv != 0) {
1039 device_printf(sc->dev, "Cannot get 'pex' clock\n");
1040 return (ENXIO);
1041 }
1042 rv = clk_get_by_ofw_name(sc->dev, 0, "afi", &sc->clk_afi);
1043 if (rv != 0) {
1044 device_printf(sc->dev, "Cannot get 'afi' clock\n");
1045 return (ENXIO);
1046 }
1047 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e);
1048 if (rv != 0) {
1049 device_printf(sc->dev, "Cannot get 'pll_e' clock\n");
1050 return (ENXIO);
1051 }
1052 if (sc->soc->cml_clk) {
1053 rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml);
1054 if (rv != 0) {
1055 device_printf(sc->dev, "Cannot get 'cml' clock\n");
1056 return (ENXIO);
1057 }
1058 }
1059
1060 /* Ports */
1061 sc->num_ports = 0;
1062 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
1063 port = tegra_pcib_parse_port(sc, child);
1064 if (port == NULL) {
1065 device_printf(sc->dev, "Cannot parse PCIe port node\n");
1066 return (ENXIO);
1067 }
1068 sc->ports[sc->num_ports++] = port;
1069 }
1070
1071 return (0);
1072 }
1073
1074 static int
1075 tegra_pcib_decode_ranges(struct tegra_pcib_softc *sc,
1076 struct ofw_pci_range *ranges, int nranges)
1077 {
1078 int i;
1079
1080 for (i = 2; i < nranges; i++) {
1081 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) ==
1082 OFW_PCI_PHYS_HI_SPACE_IO) {
1083 if (sc->io_range.size != 0) {
1084 device_printf(sc->dev,
1085 "Duplicated IO range found in DT\n");
1086 return (ENXIO);
1087 }
1088 sc->io_range = ranges[i];
1089 }
1090 if (((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) ==
1091 OFW_PCI_PHYS_HI_SPACE_MEM32)) {
1092 if (ranges[i].pci_hi & OFW_PCI_PHYS_HI_PREFETCHABLE) {
1093 if (sc->pref_mem_range.size != 0) {
1094 device_printf(sc->dev,
1095 "Duplicated memory range found "
1096 "in DT\n");
1097 return (ENXIO);
1098 }
1099 sc->pref_mem_range = ranges[i];
1100 } else {
1101 if (sc->mem_range.size != 0) {
1102 device_printf(sc->dev,
1103 "Duplicated memory range found "
1104 "in DT\n");
1105 return (ENXIO);
1106 }
1107 sc->mem_range = ranges[i];
1108 }
1109 }
1110 }
1111 if ((sc->io_range.size == 0) || (sc->mem_range.size == 0)
1112 || (sc->pref_mem_range.size == 0)) {
1113 device_printf(sc->dev,
1114 " Not all required ranges are found in DT\n");
1115 return (ENXIO);
1116 }
1117 return (0);
1118 }
1119
1120 /*
1121 * Hardware config.
1122 */
1123 static int
1124 tegra_pcib_wait_for_link(struct tegra_pcib_softc *sc,
1125 struct tegra_pcib_port *port)
1126 {
1127 uint32_t reg;
1128 int i;
1129
1130 /* Setup link detection. */
1131 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,
1132 RP_PRIV_MISC, 4);
1133 reg &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
1134 reg |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
1135 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0,
1136 RP_PRIV_MISC, reg, 4);
1137
1138 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) {
1139 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,
1140 RP_VEND_XP, 4);
1141 if (reg & RP_VEND_XP_DL_UP)
1142 break;
1143 DELAY(1);
1144 }
1145 if (i <= 0)
1146 return (ETIMEDOUT);
1147
1148 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) {
1149 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,
1150 RP_LINK_CONTROL_STATUS, 4);
1151 if (reg & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
1152 break;
1153
1154 DELAY(1);
1155 }
1156 if (i <= 0)
1157 return (ETIMEDOUT);
1158 return (0);
1159 }
1160
1161 static void
1162 tegra_pcib_port_enable(struct tegra_pcib_softc *sc, int port_num)
1163 {
1164 struct tegra_pcib_port *port;
1165 uint32_t reg;
1166 int rv;
1167
1168 port = sc->ports[port_num];
1169
1170 /* Put port to reset. */
1171 reg = AFI_RD4(sc, port->afi_pex_ctrl);
1172 reg &= ~AFI_PEX_CTRL_RST_L;
1173 AFI_WR4(sc, port->afi_pex_ctrl, reg);
1174 AFI_RD4(sc, port->afi_pex_ctrl);
1175 DELAY(10);
1176
1177 /* Enable clocks. */
1178 reg |= AFI_PEX_CTRL_REFCLK_EN;
1179 reg |= AFI_PEX_CTRL_CLKREQ_EN;
1180 reg |= AFI_PEX_CTRL_OVERRIDE_EN;
1181 AFI_WR4(sc, port->afi_pex_ctrl, reg);
1182 AFI_RD4(sc, port->afi_pex_ctrl);
1183 DELAY(100);
1184
1185 /* Release reset. */
1186 reg |= AFI_PEX_CTRL_RST_L;
1187 AFI_WR4(sc, port->afi_pex_ctrl, reg);
1188
1189 if (sc->soc->pca_enable) {
1190 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,
1191 RP_VEND_CTL2, 4);
1192 reg |= RP_VEND_CTL2_PCA_ENABLE;
1193 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0,
1194 RP_VEND_CTL2, reg, 4);
1195 }
1196
1197 rv = tegra_pcib_wait_for_link(sc, port);
1198 if (bootverbose)
1199 device_printf(sc->dev, " port %d (%d lane%s): Link is %s\n",
1200 port->port_idx, port->num_lanes,
1201 port->num_lanes > 1 ? "s": "",
1202 rv == 0 ? "up": "down");
1203 }
1204
1205 static void
1206 tegra_pcib_port_disable(struct tegra_pcib_softc *sc, uint32_t port_num)
1207 {
1208 struct tegra_pcib_port *port;
1209 uint32_t reg;
1210
1211 port = sc->ports[port_num];
1212
1213 /* Put port to reset. */
1214 reg = AFI_RD4(sc, port->afi_pex_ctrl);
1215 reg &= ~AFI_PEX_CTRL_RST_L;
1216 AFI_WR4(sc, port->afi_pex_ctrl, reg);
1217 AFI_RD4(sc, port->afi_pex_ctrl);
1218 DELAY(10);
1219
1220 /* Disable clocks. */
1221 reg &= ~AFI_PEX_CTRL_CLKREQ_EN;
1222 reg &= ~AFI_PEX_CTRL_REFCLK_EN;
1223 AFI_WR4(sc, port->afi_pex_ctrl, reg);
1224
1225 if (bootverbose)
1226 device_printf(sc->dev, " port %d (%d lane%s): Disabled\n",
1227 port->port_idx, port->num_lanes,
1228 port->num_lanes > 1 ? "s": "");
1229 }
1230
1231 static void
1232 tegra_pcib_set_bar(struct tegra_pcib_softc *sc, int bar, uint32_t axi,
1233 uint64_t fpci, uint32_t size, int is_memory)
1234 {
1235 uint32_t fpci_reg;
1236 uint32_t axi_reg;
1237 uint32_t size_reg;
1238
1239 axi_reg = axi & ~0xFFF;
1240 size_reg = size >> 12;
1241 fpci_reg = (uint32_t)(fpci >> 8) & ~0xF;
1242 fpci_reg |= is_memory ? 0x1 : 0x0;
1243 AFI_WR4(sc, bars[bar].axi_start, axi_reg);
1244 AFI_WR4(sc, bars[bar].size, size_reg);
1245 AFI_WR4(sc, bars[bar].fpci_start, fpci_reg);
1246 }
1247
1248 static int
1249 tegra_pcib_enable(struct tegra_pcib_softc *sc)
1250 {
1251 int rv;
1252 int i;
1253 uint32_t reg;
1254
1255 rv = tegra_pcib_enable_fdt_resources(sc);
1256 if (rv != 0) {
1257 device_printf(sc->dev, "Cannot enable FDT resources\n");
1258 return (rv);
1259 }
1260
1261 /* Enable PLLE control. */
1262 reg = AFI_RD4(sc, AFI_PLLE_CONTROL);
1263 reg &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
1264 reg |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
1265 AFI_WR4(sc, AFI_PLLE_CONTROL, reg);
1266
1267 /* Set bias pad. */
1268 AFI_WR4(sc, AFI_PEXBIAS_CTRL, 0);
1269
1270 /* Configure mode and ports. */
1271 reg = AFI_RD4(sc, AFI_PCIE_CONFIG);
1272 reg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
1273 if (sc->lanes_cfg == 0x14) {
1274 if (bootverbose)
1275 device_printf(sc->dev,
1276 "Using x1,x4 configuration\n");
1277 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1;
1278 } else if (sc->lanes_cfg == 0x12) {
1279 if (bootverbose)
1280 device_printf(sc->dev,
1281 "Using x1,x2 configuration\n");
1282 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1;
1283 } else {
1284 device_printf(sc->dev,
1285 "Unsupported lanes configuration: 0x%X\n", sc->lanes_cfg);
1286 }
1287 reg |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL;
1288 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
1289 if ((sc->ports[i] != NULL))
1290 reg &=
1291 ~AFI_PCIE_CONFIG_PCIE_DISABLE(sc->ports[i]->port_idx);
1292 }
1293 AFI_WR4(sc, AFI_PCIE_CONFIG, reg);
1294
1295 /* Enable Gen2 support. */
1296 reg = AFI_RD4(sc, AFI_FUSE);
1297 reg &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
1298 AFI_WR4(sc, AFI_FUSE, reg);
1299
1300 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
1301 if (sc->ports[i] != NULL) {
1302 rv = phy_enable(sc->ports[i]->phy);
1303 if (rv != 0) {
1304 device_printf(sc->dev,
1305 "Cannot enable phy for port %d\n",
1306 sc->ports[i]->port_idx);
1307 return (rv);
1308 }
1309 }
1310 }
1311
1312 /* Configure PCIe reference clock */
1313 PADS_WR4(sc, PADS_REFCLK_CFG0, sc->soc->pads_refclk_cfg0);
1314 if (sc->num_ports > 2)
1315 PADS_WR4(sc, PADS_REFCLK_CFG1, sc->soc->pads_refclk_cfg1);
1316
1317 rv = hwreset_deassert(sc->hwreset_pcie_x);
1318 if (rv != 0) {
1319 device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n");
1320 return (rv);
1321 }
1322
1323 /* Enable config space. */
1324 reg = AFI_RD4(sc, AFI_CONFIGURATION);
1325 reg |= AFI_CONFIGURATION_EN_FPCI;
1326 AFI_WR4(sc, AFI_CONFIGURATION, reg);
1327
1328 /* Enable AFI errors. */
1329 reg = 0;
1330 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_SLVERR);
1331 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_DECERR);
1332 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_SLVERR);
1333 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_DECERR);
1334 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_WRERR);
1335 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_SM_MSG);
1336 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_DFPCI_DECERR);
1337 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_AXI_DECERR);
1338 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT);
1339 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE);
1340 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE);
1341 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE);
1342 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE);
1343 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_P2P_ERROR);
1344 AFI_WR4(sc, AFI_AFI_INTR_ENABLE, reg);
1345 AFI_WR4(sc, AFI_SM_INTR_ENABLE, 0xffffffff);
1346
1347 /* Enable INT, disable MSI. */
1348 AFI_WR4(sc, AFI_INTR_MASK, AFI_INTR_MASK_INT_MASK);
1349
1350 /* Mask all FPCI errors. */
1351 AFI_WR4(sc, AFI_FPCI_ERROR_MASKS, 0);
1352
1353 /* Setup AFI translation windows. */
1354 /* BAR 0 - type 1 extended configuration. */
1355 tegra_pcib_set_bar(sc, 0, rman_get_start(sc->cfg_mem_res),
1356 FPCI_MAP_EXT_TYPE1_CONFIG, rman_get_size(sc->cfg_mem_res), 0);
1357
1358 /* BAR 1 - downstream I/O. */
1359 tegra_pcib_set_bar(sc, 1, sc->io_range.host, FPCI_MAP_IO,
1360 sc->io_range.size, 0);
1361
1362 /* BAR 2 - downstream prefetchable memory 1:1. */
1363 tegra_pcib_set_bar(sc, 2, sc->pref_mem_range.host,
1364 sc->pref_mem_range.host, sc->pref_mem_range.size, 1);
1365
1366 /* BAR 3 - downstream not prefetchable memory 1:1 .*/
1367 tegra_pcib_set_bar(sc, 3, sc->mem_range.host,
1368 sc->mem_range.host, sc->mem_range.size, 1);
1369
1370 /* BAR 3-8 clear. */
1371 tegra_pcib_set_bar(sc, 4, 0, 0, 0, 0);
1372 tegra_pcib_set_bar(sc, 5, 0, 0, 0, 0);
1373 tegra_pcib_set_bar(sc, 6, 0, 0, 0, 0);
1374 tegra_pcib_set_bar(sc, 7, 0, 0, 0, 0);
1375 tegra_pcib_set_bar(sc, 8, 0, 0, 0, 0);
1376
1377 /* MSI BAR - clear. */
1378 tegra_pcib_set_bar(sc, 9, 0, 0, 0, 0);
1379 return(0);
1380 }
1381
1382 #ifdef TEGRA_PCIB_MSI_ENABLE
1383 static int
1384 tegra_pcib_attach_msi(device_t dev)
1385 {
1386 struct tegra_pcib_softc *sc;
1387 uint32_t reg;
1388 int i, rv;
1389
1390 sc = device_get_softc(dev);
1391
1392 sc->msi_page = kmem_alloc_contig(PAGE_SIZE, M_WAITOK, 0,
1393 BUS_SPACE_MAXADDR, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
1394
1395 /* MSI BAR */
1396 tegra_pcib_set_bar(sc, 9, vtophys(sc->msi_page), vtophys(sc->msi_page),
1397 PAGE_SIZE, 0);
1398
1399 /* Disble and clear all interrupts. */
1400 for (i = 0; i < AFI_MSI_REGS; i++) {
1401 AFI_WR4(sc, AFI_MSI_EN_VEC(i), 0);
1402 AFI_WR4(sc, AFI_MSI_VEC(i), 0xFFFFFFFF);
1403 }
1404 rv = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
1405 tegra_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie);
1406 if (rv != 0) {
1407 device_printf(dev, "cannot setup MSI interrupt handler\n");
1408 rv = ENXIO;
1409 goto out;
1410 }
1411
1412 if (tegra_pcib_msi_attach(sc) != 0) {
1413 device_printf(dev, "WARNING: unable to attach PIC\n");
1414 tegra_pcib_msi_detach(sc);
1415 goto out;
1416 }
1417
1418 /* Unmask MSI interrupt. */
1419 reg = AFI_RD4(sc, AFI_INTR_MASK);
1420 reg |= AFI_INTR_MASK_MSI_MASK;
1421 AFI_WR4(sc, AFI_INTR_MASK, reg);
1422
1423 out:
1424 return (rv);
1425 }
1426 #endif
1427
1428 static int
1429 tegra_pcib_probe(device_t dev)
1430 {
1431 if (!ofw_bus_status_okay(dev))
1432 return (ENXIO);
1433
1434 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
1435 device_set_desc(dev, "Nvidia Integrated PCI/PCI-E Controller");
1436 return (BUS_PROBE_DEFAULT);
1437 }
1438 return (ENXIO);
1439 }
1440
1441 static int
1442 tegra_pcib_attach(device_t dev)
1443 {
1444 struct tegra_pcib_softc *sc;
1445 phandle_t node;
1446 int rv;
1447 int rid;
1448 struct tegra_pcib_port *port;
1449 int i;
1450
1451 sc = device_get_softc(dev);
1452 sc->dev = dev;
1453 mtx_init(&sc->mtx, "msi_mtx", NULL, MTX_DEF);
1454
1455 node = ofw_bus_get_node(dev);
1456 sc->soc = (struct pcie_soc *)ofw_bus_search_compatible(dev,
1457 compat_data)->ocd_data;
1458
1459 rv = tegra_pcib_parse_fdt_resources(sc, node);
1460 if (rv != 0) {
1461 device_printf(dev, "Cannot get FDT resources\n");
1462 return (rv);
1463 }
1464
1465 /* Allocate bus_space resources. */
1466 rid = 0;
1467 sc->pads_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1468 RF_ACTIVE);
1469 if (sc->pads_mem_res == NULL) {
1470 device_printf(dev, "Cannot allocate PADS register\n");
1471 rv = ENXIO;
1472 goto out;
1473 }
1474 /*
1475 * XXX - FIXME
1476 * tag for config space is not filled when RF_ALLOCATED flag is used.
1477 */
1478 sc->bus_tag = rman_get_bustag(sc->pads_mem_res);
1479
1480 rid = 1;
1481 sc->afi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1482 RF_ACTIVE);
1483 if (sc->afi_mem_res == NULL) {
1484 device_printf(dev, "Cannot allocate AFI register\n");
1485 rv = ENXIO;
1486 goto out;
1487 }
1488
1489 rid = 2;
1490 sc->cfg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1491 RF_ALLOCATED);
1492 if (sc->cfg_mem_res == NULL) {
1493 device_printf(dev, "Cannot allocate config space memory\n");
1494 rv = ENXIO;
1495 goto out;
1496 }
1497 sc->cfg_base_addr = rman_get_start(sc->cfg_mem_res);
1498
1499 /* Map RP slots */
1500 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
1501 if (sc->ports[i] == NULL)
1502 continue;
1503 port = sc->ports[i];
1504 rv = bus_space_map(sc->bus_tag, port->rp_base_addr,
1505 port->rp_size, 0, &port->cfg_handle);
1506 if (rv != 0) {
1507 device_printf(sc->dev, "Cannot allocate memory for "
1508 "port: %d\n", i);
1509 rv = ENXIO;
1510 goto out;
1511 }
1512 }
1513
1514 /*
1515 * Get PCI interrupt
1516 */
1517 rid = 0;
1518 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1519 RF_ACTIVE | RF_SHAREABLE);
1520 if (sc->irq_res == NULL) {
1521 device_printf(dev, "Cannot allocate IRQ resources\n");
1522 rv = ENXIO;
1523 goto out;
1524 }
1525
1526 rid = 1;
1527 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1528 RF_ACTIVE);
1529 if (sc->irq_res == NULL) {
1530 device_printf(dev, "Cannot allocate MSI IRQ resources\n");
1531 rv = ENXIO;
1532 goto out;
1533 }
1534
1535 sc->ofw_pci.sc_range_mask = 0x3;
1536 rv = ofw_pci_init(dev);
1537 if (rv != 0)
1538 goto out;
1539
1540 rv = tegra_pcib_decode_ranges(sc, sc->ofw_pci.sc_range,
1541 sc->ofw_pci.sc_nrange);
1542 if (rv != 0)
1543 goto out;
1544
1545 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
1546 tegra_pci_intr, NULL, sc, &sc->intr_cookie)) {
1547 device_printf(dev, "cannot setup interrupt handler\n");
1548 rv = ENXIO;
1549 goto out;
1550 }
1551
1552 /*
1553 * Enable PCIE device.
1554 */
1555 rv = tegra_pcib_enable(sc);
1556 if (rv != 0)
1557 goto out;
1558 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
1559 if (sc->ports[i] == NULL)
1560 continue;
1561 if (sc->ports[i]->enabled)
1562 tegra_pcib_port_enable(sc, i);
1563 else
1564 tegra_pcib_port_disable(sc, i);
1565 }
1566
1567 #ifdef TEGRA_PCIB_MSI_ENABLE
1568 rv = tegra_pcib_attach_msi(dev);
1569 if (rv != 0)
1570 goto out;
1571 #endif
1572 device_add_child(dev, "pci", -1);
1573
1574 return (bus_generic_attach(dev));
1575
1576 out:
1577
1578 return (rv);
1579 }
1580
1581 static device_method_t tegra_pcib_methods[] = {
1582 /* Device interface */
1583 DEVMETHOD(device_probe, tegra_pcib_probe),
1584 DEVMETHOD(device_attach, tegra_pcib_attach),
1585
1586 /* Bus interface */
1587 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1588 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1589
1590 /* pcib interface */
1591 DEVMETHOD(pcib_maxslots, tegra_pcib_maxslots),
1592 DEVMETHOD(pcib_read_config, tegra_pcib_read_config),
1593 DEVMETHOD(pcib_write_config, tegra_pcib_write_config),
1594 DEVMETHOD(pcib_route_interrupt, tegra_pcib_route_interrupt),
1595 DEVMETHOD(pcib_alloc_msi, tegra_pcib_alloc_msi),
1596 DEVMETHOD(pcib_release_msi, tegra_pcib_release_msi),
1597 DEVMETHOD(pcib_map_msi, tegra_pcib_map_msi),
1598 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
1599
1600 #ifdef TEGRA_PCIB_MSI_ENABLE
1601 /* MSI/MSI-X */
1602 DEVMETHOD(msi_alloc_msi, tegra_pcib_msi_alloc_msi),
1603 DEVMETHOD(msi_release_msi, tegra_pcib_msi_release_msi),
1604 DEVMETHOD(msi_map_msi, tegra_pcib_msi_map_msi),
1605
1606 /* Interrupt controller interface */
1607 DEVMETHOD(pic_disable_intr, tegra_pcib_msi_disable_intr),
1608 DEVMETHOD(pic_enable_intr, tegra_pcib_msi_enable_intr),
1609 DEVMETHOD(pic_setup_intr, tegra_pcib_msi_setup_intr),
1610 DEVMETHOD(pic_teardown_intr, tegra_pcib_msi_teardown_intr),
1611 DEVMETHOD(pic_post_filter, tegra_pcib_msi_post_filter),
1612 DEVMETHOD(pic_post_ithread, tegra_pcib_msi_post_ithread),
1613 DEVMETHOD(pic_pre_ithread, tegra_pcib_msi_pre_ithread),
1614 #endif
1615
1616 /* OFW bus interface */
1617 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
1618 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
1619 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
1620 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
1621 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
1622
1623 DEVMETHOD_END
1624 };
1625
1626 static devclass_t pcib_devclass;
1627 DEFINE_CLASS_1(pcib, tegra_pcib_driver, tegra_pcib_methods,
1628 sizeof(struct tegra_pcib_softc), ofw_pci_driver);
1629 DRIVER_MODULE(tegra_pcib, simplebus, tegra_pcib_driver, pcib_devclass,
1630 NULL, NULL);
Cache object: 5202c12d97d3a5184c081b3b04e0de7c
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