1 /*-
2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 /*
31 * RTC driver for Tegra SoCs.
32 */
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/clock.h>
37 #include <sys/kernel.h>
38 #include <sys/limits.h>
39 #include <sys/lock.h>
40 #include <sys/mutex.h>
41 #include <sys/module.h>
42 #include <sys/resource.h>
43
44 #include <machine/bus.h>
45 #include <machine/resource.h>
46 #include <sys/rman.h>
47
48 #include <dev/extres/clk/clk.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
51
52 #include "clock_if.h"
53
54 #define RTC_CONTROL 0x00
55 #define RTC_BUSY 0x04
56 #define RTC_BUSY_STATUS (1 << 0)
57 #define RTC_SECONDS 0x08
58 #define RTC_SHADOW_SECONDS 0x0c
59 #define RTC_MILLI_SECONDS 0x10
60 #define RTC_SECONDS_ALARM0 0x14
61 #define RTC_SECONDS_ALARM1 0x18
62 #define RTC_MILLI_SECONDS_ALARM 0x1c
63 #define RTC_SECONDS_COUNTDOWN_ALARM 0x20
64 #define RTC_MILLI_SECONDS_COUNTDOW_ALARM 0x24
65 #define RTC_INTR_MASK 0x28
66 #define RTC_INTR_MSEC_CDN_ALARM (1 << 4)
67 #define RTC_INTR_SEC_CDN_ALARM (1 << 3)
68 #define RTC_INTR_MSEC_ALARM (1 << 2)
69 #define RTC_INTR_SEC_ALARM1 (1 << 1)
70 #define RTC_INTR_SEC_ALARM0 (1 << 0)
71
72 #define RTC_INTR_STATUS 0x2c
73 #define RTC_INTR_SOURCE 0x30
74 #define RTC_INTR_SET 0x34
75 #define RTC_CORRECTION_FACTOR 0x38
76
77 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
78 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))
79
80 #define LOCK(_sc) mtx_lock(&(_sc)->mtx)
81 #define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
82 #define SLEEP(_sc, timeout) \
83 mtx_sleep(sc, &sc->mtx, 0, "rtcwait", timeout);
84 #define LOCK_INIT(_sc) \
85 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "tegra_rtc", MTX_DEF)
86 #define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx)
87 #define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED)
88 #define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED)
89
90 static struct ofw_compat_data compat_data[] = {
91 {"nvidia,tegra124-rtc", 1},
92 {NULL, 0}
93 };
94
95 struct tegra_rtc_softc {
96 device_t dev;
97 struct mtx mtx;
98
99 struct resource *mem_res;
100 struct resource *irq_res;
101 void *irq_h;
102
103 clk_t clk;
104 uint32_t core_freq;
105 };
106
107 static void
108 tegra_rtc_wait(struct tegra_rtc_softc *sc)
109 {
110 int timeout;
111
112 for (timeout = 500; timeout >0; timeout--) {
113 if ((RD4(sc, RTC_BUSY) & RTC_BUSY_STATUS) == 0)
114 break;
115 DELAY(1);
116 }
117 if (timeout <= 0)
118 device_printf(sc->dev, "Device busy timeouted\n");
119
120 }
121
122 /*
123 * Get the time of day clock and return it in ts.
124 * Return 0 on success, an error number otherwise.
125 */
126 static int
127 tegra_rtc_gettime(device_t dev, struct timespec *ts)
128 {
129 struct tegra_rtc_softc *sc;
130 struct timeval tv;
131 uint32_t msec, sec;
132
133 sc = device_get_softc(dev);
134
135 LOCK(sc);
136 msec = RD4(sc, RTC_MILLI_SECONDS);
137 sec = RD4(sc, RTC_SHADOW_SECONDS);
138 UNLOCK(sc);
139 tv.tv_sec = sec;
140 tv.tv_usec = msec * 1000;
141 TIMEVAL_TO_TIMESPEC(&tv, ts);
142 return (0);
143 }
144
145 static int
146 tegra_rtc_settime(device_t dev, struct timespec *ts)
147 {
148 struct tegra_rtc_softc *sc;
149 struct timeval tv;
150
151 sc = device_get_softc(dev);
152
153 LOCK(sc);
154 TIMESPEC_TO_TIMEVAL(&tv, ts);
155 tegra_rtc_wait(sc);
156 WR4(sc, RTC_SECONDS, tv.tv_sec);
157 UNLOCK(sc);
158
159 return (0);
160 }
161
162 static void
163 tegra_rtc_intr(void *arg)
164 {
165 struct tegra_rtc_softc *sc;
166 uint32_t status;
167
168 sc = (struct tegra_rtc_softc *)arg;
169 LOCK(sc);
170 status = RD4(sc, RTC_INTR_STATUS);
171 WR4(sc, RTC_INTR_STATUS, status);
172 UNLOCK(sc);
173 }
174
175 static int
176 tegra_rtc_probe(device_t dev)
177 {
178 if (!ofw_bus_status_okay(dev))
179 return (ENXIO);
180
181 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
182 return (ENXIO);
183
184 return (BUS_PROBE_DEFAULT);
185 }
186
187 static int
188 tegra_rtc_attach(device_t dev)
189 {
190 int rv, rid;
191 struct tegra_rtc_softc *sc;
192
193 sc = device_get_softc(dev);
194 sc->dev = dev;
195
196 LOCK_INIT(sc);
197
198 /* Get the memory resource for the register mapping. */
199 rid = 0;
200 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
201 RF_ACTIVE);
202 if (sc->mem_res == NULL) {
203 device_printf(dev, "Cannot map registers.\n");
204 rv = ENXIO;
205 goto fail;
206 }
207
208 /* Allocate our IRQ resource. */
209 rid = 0;
210 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
211 RF_ACTIVE);
212 if (sc->irq_res == NULL) {
213 device_printf(dev, "Cannot allocate interrupt.\n");
214 rv = ENXIO;
215 goto fail;
216 }
217
218 /* OFW resources. */
219 rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
220 if (rv != 0) {
221 device_printf(dev, "Cannot get i2c clock: %d\n", rv);
222 goto fail;
223 }
224 rv = clk_enable(sc->clk);
225 if (rv != 0) {
226 device_printf(dev, "Cannot enable clock: %d\n", rv);
227 goto fail;
228 }
229
230 /* Init hardware. */
231 WR4(sc, RTC_SECONDS_ALARM0, 0);
232 WR4(sc, RTC_SECONDS_ALARM1, 0);
233 WR4(sc, RTC_INTR_STATUS, 0xFFFFFFFF);
234 WR4(sc, RTC_INTR_MASK, 0);
235
236 /* Setup interrupt */
237 rv = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
238 NULL, tegra_rtc_intr, sc, &sc->irq_h);
239 if (rv) {
240 device_printf(dev, "Cannot setup interrupt.\n");
241 goto fail;
242 }
243
244 /*
245 * Register as a time of day clock with 1-second resolution.
246 *
247 * XXXX Not yet, we don't have support for multiple RTCs
248 */
249 /* clock_register(dev, 1000000); */
250
251 return (bus_generic_attach(dev));
252
253 fail:
254 if (sc->clk != NULL)
255 clk_release(sc->clk);
256 if (sc->irq_h != NULL)
257 bus_teardown_intr(dev, sc->irq_res, sc->irq_h);
258 if (sc->irq_res != NULL)
259 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
260 if (sc->mem_res != NULL)
261 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
262 LOCK_DESTROY(sc);
263
264 return (rv);
265 }
266
267 static int
268 tegra_rtc_detach(device_t dev)
269 {
270 struct tegra_rtc_softc *sc;
271
272 sc = device_get_softc(dev);
273 if (sc->irq_h != NULL)
274 bus_teardown_intr(dev, sc->irq_res, sc->irq_h);
275 if (sc->irq_res != NULL)
276 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
277 if (sc->mem_res != NULL)
278 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
279
280 LOCK_DESTROY(sc);
281 return (bus_generic_detach(dev));
282 }
283
284 static device_method_t tegra_rtc_methods[] = {
285 /* Device interface */
286 DEVMETHOD(device_probe, tegra_rtc_probe),
287 DEVMETHOD(device_attach, tegra_rtc_attach),
288 DEVMETHOD(device_detach, tegra_rtc_detach),
289
290 /* clock interface */
291 DEVMETHOD(clock_gettime, tegra_rtc_gettime),
292 DEVMETHOD(clock_settime, tegra_rtc_settime),
293
294 DEVMETHOD_END
295 };
296
297 static devclass_t tegra_rtc_devclass;
298 static DEFINE_CLASS_0(rtc, tegra_rtc_driver, tegra_rtc_methods,
299 sizeof(struct tegra_rtc_softc));
300 DRIVER_MODULE(tegra_rtc, simplebus, tegra_rtc_driver, tegra_rtc_devclass,
301 NULL, NULL);
Cache object: 2ac2d9e388b5392afde00f869007acb4
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