1 /*-
2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 /*
31 * SDHCI driver glue for NVIDIA Tegra family
32 *
33 */
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/types.h>
37 #include <sys/bus.h>
38 #include <sys/gpio.h>
39 #include <sys/kernel.h>
40 #include <sys/lock.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
44 #include <sys/resource.h>
45 #include <sys/rman.h>
46 #include <sys/sysctl.h>
47 #include <sys/taskqueue.h>
48
49 #include <machine/bus.h>
50 #include <machine/resource.h>
51 #include <machine/intr.h>
52
53 #include <dev/extres/clk/clk.h>
54 #include <dev/extres/hwreset/hwreset.h>
55 #include <dev/gpio/gpiobusvar.h>
56 #include <dev/mmc/bridge.h>
57 #include <dev/mmc/mmcbrvar.h>
58 #include <dev/ofw/ofw_bus.h>
59 #include <dev/ofw/ofw_bus_subr.h>
60 #include <dev/sdhci/sdhci.h>
61 #include <dev/sdhci/sdhci_fdt_gpio.h>
62
63 #include "sdhci_if.h"
64
65 #include "opt_mmccam.h"
66
67 /* Tegra SDHOST controller vendor register definitions */
68 #define SDMMC_VENDOR_CLOCK_CNTRL 0x100
69 #define VENDOR_CLOCK_CNTRL_CLK_SHIFT 8
70 #define VENDOR_CLOCK_CNTRL_CLK_MASK 0xFF
71 #define SDMMC_VENDOR_SYS_SW_CNTRL 0x104
72 #define SDMMC_VENDOR_CAP_OVERRIDES 0x10C
73 #define SDMMC_VENDOR_BOOT_CNTRL 0x110
74 #define SDMMC_VENDOR_BOOT_ACK_TIMEOUT 0x114
75 #define SDMMC_VENDOR_BOOT_DAT_TIMEOUT 0x118
76 #define SDMMC_VENDOR_DEBOUNCE_COUNT 0x11C
77 #define SDMMC_VENDOR_MISC_CNTRL 0x120
78 #define VENDOR_MISC_CTRL_ENABLE_SDR104 0x8
79 #define VENDOR_MISC_CTRL_ENABLE_SDR50 0x10
80 #define VENDOR_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
81 #define VENDOR_MISC_CTRL_ENABLE_DDR50 0x200
82 #define SDMMC_MAX_CURRENT_OVERRIDE 0x124
83 #define SDMMC_MAX_CURRENT_OVERRIDE_HI 0x128
84 #define SDMMC_VENDOR_CLK_GATE_HYSTERESIS_COUNT 0x1D0
85 #define SDMMC_VENDOR_PHWRESET_VAL0 0x1D4
86 #define SDMMC_VENDOR_PHWRESET_VAL1 0x1D8
87 #define SDMMC_VENDOR_PHWRESET_VAL2 0x1DC
88 #define SDMMC_SDMEMCOMPPADCTRL_0 0x1E0
89 #define SDMMC_AUTO_CAL_CONFIG 0x1E4
90 #define SDMMC_AUTO_CAL_INTERVAL 0x1E8
91 #define SDMMC_AUTO_CAL_STATUS 0x1EC
92 #define SDMMC_SDMMC_MCCIF_FIFOCTRL 0x1F4
93 #define SDMMC_TIMEOUT_WCOAL_SDMMC 0x1F8
94
95 /* Compatible devices. */
96 static struct ofw_compat_data compat_data[] = {
97 {"nvidia,tegra124-sdhci", 1},
98 {"nvidia,tegra210-sdhci", 1},
99 {NULL, 0},
100 };
101
102 struct tegra_sdhci_softc {
103 device_t dev;
104 struct resource * mem_res;
105 struct resource * irq_res;
106 void * intr_cookie;
107 u_int quirks; /* Chip specific quirks */
108 u_int caps; /* If we override SDHCI_CAPABILITIES */
109 uint32_t max_clk; /* Max possible freq */
110 clk_t clk;
111 hwreset_t reset;
112 gpio_pin_t gpio_power;
113 struct sdhci_fdt_gpio *gpio;
114
115 int force_card_present;
116 struct sdhci_slot slot;
117
118 };
119
120 static inline uint32_t
121 RD4(struct tegra_sdhci_softc *sc, bus_size_t off)
122 {
123
124 return (bus_read_4(sc->mem_res, off));
125 }
126
127 static uint8_t
128 tegra_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
129 {
130 struct tegra_sdhci_softc *sc;
131
132 sc = device_get_softc(dev);
133 return (bus_read_1(sc->mem_res, off));
134 }
135
136 static uint16_t
137 tegra_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
138 {
139 struct tegra_sdhci_softc *sc;
140
141 sc = device_get_softc(dev);
142 return (bus_read_2(sc->mem_res, off));
143 }
144
145 static uint32_t
146 tegra_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
147 {
148 struct tegra_sdhci_softc *sc;
149 uint32_t val32;
150
151 sc = device_get_softc(dev);
152 val32 = bus_read_4(sc->mem_res, off);
153 /* Force the card-present state if necessary. */
154 if (off == SDHCI_PRESENT_STATE && sc->force_card_present)
155 val32 |= SDHCI_CARD_PRESENT;
156 return (val32);
157 }
158
159 static void
160 tegra_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
161 uint32_t *data, bus_size_t count)
162 {
163 struct tegra_sdhci_softc *sc;
164
165 sc = device_get_softc(dev);
166 bus_read_multi_4(sc->mem_res, off, data, count);
167 }
168
169 static void
170 tegra_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
171 uint8_t val)
172 {
173 struct tegra_sdhci_softc *sc;
174
175 sc = device_get_softc(dev);
176 bus_write_1(sc->mem_res, off, val);
177 }
178
179 static void
180 tegra_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
181 uint16_t val)
182 {
183 struct tegra_sdhci_softc *sc;
184
185 sc = device_get_softc(dev);
186 bus_write_2(sc->mem_res, off, val);
187 }
188
189 static void
190 tegra_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
191 uint32_t val)
192 {
193 struct tegra_sdhci_softc *sc;
194
195 sc = device_get_softc(dev);
196 bus_write_4(sc->mem_res, off, val);
197 }
198
199 static void
200 tegra_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
201 uint32_t *data, bus_size_t count)
202 {
203 struct tegra_sdhci_softc *sc;
204
205 sc = device_get_softc(dev);
206 bus_write_multi_4(sc->mem_res, off, data, count);
207 }
208
209 static void
210 tegra_sdhci_intr(void *arg)
211 {
212 struct tegra_sdhci_softc *sc = arg;
213
214 sdhci_generic_intr(&sc->slot);
215 RD4(sc, SDHCI_INT_STATUS);
216 }
217
218 static int
219 tegra_sdhci_get_ro(device_t brdev, device_t reqdev)
220 {
221 struct tegra_sdhci_softc *sc = device_get_softc(brdev);
222
223 return (sdhci_fdt_gpio_get_readonly(sc->gpio));
224 }
225
226 static bool
227 tegra_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot)
228 {
229 struct tegra_sdhci_softc *sc = device_get_softc(dev);
230
231 return (sdhci_fdt_gpio_get_present(sc->gpio));
232 }
233
234 static int
235 tegra_sdhci_probe(device_t dev)
236 {
237 struct tegra_sdhci_softc *sc;
238 phandle_t node;
239 pcell_t cid;
240 const struct ofw_compat_data *cd;
241
242 sc = device_get_softc(dev);
243 if (!ofw_bus_status_okay(dev))
244 return (ENXIO);
245
246 cd = ofw_bus_search_compatible(dev, compat_data);
247 if (cd->ocd_data == 0)
248 return (ENXIO);
249
250 node = ofw_bus_get_node(dev);
251 device_set_desc(dev, "Tegra SDHCI controller");
252
253 /* Allow dts to patch quirks, slots, and max-frequency. */
254 if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0)
255 sc->quirks = cid;
256 if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0)
257 sc->max_clk = cid;
258
259 return (BUS_PROBE_DEFAULT);
260 }
261
262 static int
263 tegra_sdhci_attach(device_t dev)
264 {
265 struct tegra_sdhci_softc *sc;
266 int rid, rv;
267 uint64_t freq;
268 phandle_t node, prop;
269
270 sc = device_get_softc(dev);
271 sc->dev = dev;
272 node = ofw_bus_get_node(dev);
273
274 rid = 0;
275 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
276 RF_ACTIVE);
277 if (!sc->mem_res) {
278 device_printf(dev, "cannot allocate memory window\n");
279 rv = ENXIO;
280 goto fail;
281 }
282
283 rid = 0;
284 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
285 RF_ACTIVE);
286 if (!sc->irq_res) {
287 device_printf(dev, "cannot allocate interrupt\n");
288 rv = ENXIO;
289 goto fail;
290 }
291
292 rv = hwreset_get_by_ofw_name(sc->dev, 0, "sdhci", &sc->reset);
293 if (rv != 0) {
294 device_printf(sc->dev, "Cannot get 'sdhci' reset\n");
295 goto fail;
296 }
297 rv = hwreset_assert(sc->reset);
298 if (rv != 0) {
299 device_printf(dev, "Cannot reset 'sdhci' reset\n");
300 goto fail;
301 }
302
303 gpio_pin_get_by_ofw_property(sc->dev, node, "power-gpios",
304 &sc->gpio_power);
305
306 if (OF_hasprop(node, "assigned-clocks")) {
307 rv = clk_set_assigned(sc->dev, node);
308 if (rv != 0) {
309 device_printf(dev, "Cannot set assigned clocks\n");
310 goto fail;
311 }
312 }
313
314 rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
315 if (rv != 0) {
316 device_printf(dev, "Cannot get clock\n");
317 goto fail;
318 }
319 rv = clk_enable(sc->clk);
320 if (rv != 0) {
321 device_printf(dev, "Cannot enable clock\n");
322 goto fail;
323 }
324 rv = clk_set_freq(sc->clk, 48000000, CLK_SET_ROUND_DOWN);
325 if (rv != 0) {
326 device_printf(dev, "Cannot set clock\n");
327 }
328 rv = clk_get_freq(sc->clk, &freq);
329 if (rv != 0) {
330 device_printf(dev, "Cannot get clock frequency\n");
331 goto fail;
332 }
333 DELAY(4000);
334 rv = hwreset_deassert(sc->reset);
335 if (rv != 0) {
336 device_printf(dev, "Cannot unreset 'sdhci' reset\n");
337 goto fail;
338 }
339 if (bootverbose)
340 device_printf(dev, " Base MMC clock: %jd\n", (uintmax_t)freq);
341
342 /* Fill slot information. */
343 sc->max_clk = (int)freq;
344 sc->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
345 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
346 SDHCI_QUIRK_MISSING_CAPS;
347
348 /* Limit real slot capabilities. */
349 sc->caps = RD4(sc, SDHCI_CAPABILITIES);
350 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) {
351 sc->caps &= ~(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA);
352 switch (prop) {
353 case 8:
354 sc->caps |= MMC_CAP_8_BIT_DATA;
355 /* FALLTHROUGH */
356 case 4:
357 sc->caps |= MMC_CAP_4_BIT_DATA;
358 break;
359 case 1:
360 break;
361 default:
362 device_printf(dev, "Bad bus-width value %u\n", prop);
363 break;
364 }
365 }
366 if (OF_hasprop(node, "non-removable"))
367 sc->force_card_present = 1;
368 /*
369 * Clear clock field, so SDHCI driver uses supplied frequency.
370 * in sc->slot.max_clk
371 */
372 sc->caps &= ~SDHCI_CLOCK_V3_BASE_MASK;
373
374 sc->slot.quirks = sc->quirks;
375 sc->slot.max_clk = sc->max_clk;
376 sc->slot.caps = sc->caps;
377
378 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
379 NULL, tegra_sdhci_intr, sc, &sc->intr_cookie)) {
380 device_printf(dev, "cannot setup interrupt handler\n");
381 rv = ENXIO;
382 goto fail;
383 }
384 rv = sdhci_init_slot(dev, &sc->slot, 0);
385 if (rv != 0) {
386 goto fail;
387 }
388
389 sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot);
390
391 bus_generic_probe(dev);
392 bus_generic_attach(dev);
393
394 sdhci_start_slot(&sc->slot);
395
396 return (0);
397
398 fail:
399 if (sc->gpio != NULL)
400 sdhci_fdt_gpio_teardown(sc->gpio);
401 if (sc->intr_cookie != NULL)
402 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
403 if (sc->gpio_power != NULL)
404 gpio_pin_release(sc->gpio_power);
405 if (sc->clk != NULL)
406 clk_release(sc->clk);
407 if (sc->reset != NULL)
408 hwreset_release(sc->reset);
409 if (sc->irq_res != NULL)
410 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
411 if (sc->mem_res != NULL)
412 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
413
414 return (rv);
415 }
416
417 static int
418 tegra_sdhci_detach(device_t dev)
419 {
420 struct tegra_sdhci_softc *sc = device_get_softc(dev);
421 struct sdhci_slot *slot = &sc->slot;
422
423 bus_generic_detach(dev);
424 sdhci_fdt_gpio_teardown(sc->gpio);
425 clk_release(sc->clk);
426 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
427 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
428 sc->irq_res);
429
430 sdhci_cleanup_slot(slot);
431 bus_release_resource(dev, SYS_RES_MEMORY,
432 rman_get_rid(sc->mem_res),
433 sc->mem_res);
434 return (0);
435 }
436
437 static device_method_t tegra_sdhci_methods[] = {
438 /* Device interface */
439 DEVMETHOD(device_probe, tegra_sdhci_probe),
440 DEVMETHOD(device_attach, tegra_sdhci_attach),
441 DEVMETHOD(device_detach, tegra_sdhci_detach),
442
443 /* Bus interface */
444 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
445 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
446
447 /* MMC bridge interface */
448 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
449 DEVMETHOD(mmcbr_request, sdhci_generic_request),
450 DEVMETHOD(mmcbr_get_ro, tegra_sdhci_get_ro),
451 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
452 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
453
454 /* SDHCI registers accessors */
455 DEVMETHOD(sdhci_read_1, tegra_sdhci_read_1),
456 DEVMETHOD(sdhci_read_2, tegra_sdhci_read_2),
457 DEVMETHOD(sdhci_read_4, tegra_sdhci_read_4),
458 DEVMETHOD(sdhci_read_multi_4, tegra_sdhci_read_multi_4),
459 DEVMETHOD(sdhci_write_1, tegra_sdhci_write_1),
460 DEVMETHOD(sdhci_write_2, tegra_sdhci_write_2),
461 DEVMETHOD(sdhci_write_4, tegra_sdhci_write_4),
462 DEVMETHOD(sdhci_write_multi_4, tegra_sdhci_write_multi_4),
463 DEVMETHOD(sdhci_get_card_present, tegra_sdhci_get_card_present),
464
465 DEVMETHOD_END
466 };
467
468 static devclass_t tegra_sdhci_devclass;
469 static DEFINE_CLASS_0(sdhci, tegra_sdhci_driver, tegra_sdhci_methods,
470 sizeof(struct tegra_sdhci_softc));
471 DRIVER_MODULE(sdhci_tegra, simplebus, tegra_sdhci_driver, tegra_sdhci_devclass,
472 NULL, NULL);
473 SDHCI_DEPEND(sdhci_tegra);
474 #ifndef MMCCAM
475 MMC_DECLARE_BRIDGE(sdhci);
476 #endif
Cache object: 378833e2116c056b707a9e8c0e620a21
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