1 /*-
2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 /*
31 * UART driver for Tegra SoCs.
32 */
33 #include "opt_platform.h"
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/bus.h>
38 #include <sys/conf.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
41 #include <sys/sysctl.h>
42 #include <machine/bus.h>
43
44 #include <dev/extres/clk/clk.h>
45 #include <dev/extres/hwreset/hwreset.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
48 #include <dev/uart/uart.h>
49 #include <dev/uart/uart_cpu.h>
50 #include <dev/uart/uart_cpu_fdt.h>
51 #include <dev/uart/uart_bus.h>
52 #include <dev/uart/uart_dev_ns8250.h>
53 #include <dev/ic/ns16550.h>
54
55 #include "uart_if.h"
56
57 /*
58 * High-level UART interface.
59 */
60 struct tegra_softc {
61 struct ns8250_softc ns8250_base;
62 clk_t clk;
63 hwreset_t reset;
64 };
65
66 /*
67 * UART class interface.
68 */
69 static int
70 tegra_uart_attach(struct uart_softc *sc)
71 {
72 int rv;
73 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
74 struct uart_bas *bas = &sc->sc_bas;
75
76 rv = ns8250_bus_attach(sc);
77 if (rv != 0)
78 return (rv);
79
80 ns8250->ier_rxbits = 0x1d;
81 ns8250->ier_mask = 0xc0;
82 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
83 ns8250->ier |= ns8250->ier_rxbits;
84 uart_setreg(bas, REG_IER, ns8250->ier);
85 uart_barrier(bas);
86 return (0);
87 }
88
89 static void
90 tegra_uart_grab(struct uart_softc *sc)
91 {
92 struct uart_bas *bas = &sc->sc_bas;
93 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
94 u_char ier;
95
96 /*
97 * turn off all interrupts to enter polling mode. Leave the
98 * saved mask alone. We'll restore whatever it was in ungrab.
99 * All pending interrupt signals are reset when IER is set to 0.
100 */
101 uart_lock(sc->sc_hwmtx);
102 ier = uart_getreg(bas, REG_IER);
103 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
104
105 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0)
106 ;
107
108 uart_setreg(bas, REG_FCR, 0);
109 uart_barrier(bas);
110 uart_unlock(sc->sc_hwmtx);
111 }
112
113 static void
114 tegra_uart_ungrab(struct uart_softc *sc)
115 {
116 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
117 struct uart_bas *bas = &sc->sc_bas;
118
119 /*
120 * Restore previous interrupt mask
121 */
122 uart_lock(sc->sc_hwmtx);
123 uart_setreg(bas, REG_FCR, ns8250->fcr);
124 uart_setreg(bas, REG_IER, ns8250->ier);
125 uart_barrier(bas);
126 uart_unlock(sc->sc_hwmtx);
127 }
128
129 static kobj_method_t tegra_methods[] = {
130 KOBJMETHOD(uart_probe, ns8250_bus_probe),
131 KOBJMETHOD(uart_attach, tegra_uart_attach),
132 KOBJMETHOD(uart_detach, ns8250_bus_detach),
133 KOBJMETHOD(uart_flush, ns8250_bus_flush),
134 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
135 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
136 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
137 KOBJMETHOD(uart_param, ns8250_bus_param),
138 KOBJMETHOD(uart_receive, ns8250_bus_receive),
139 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
140 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
141 KOBJMETHOD(uart_grab, tegra_uart_grab),
142 KOBJMETHOD(uart_ungrab, tegra_uart_ungrab),
143 KOBJMETHOD_END
144 };
145
146 static struct uart_class tegra_uart_class = {
147 "tegra class",
148 tegra_methods,
149 sizeof(struct tegra_softc),
150 .uc_ops = &uart_ns8250_ops,
151 .uc_range = 8,
152 .uc_rclk = 0,
153 };
154
155 /* Compatible devices. */
156 static struct ofw_compat_data compat_data[] = {
157 {"nvidia,tegra124-uart", (uintptr_t)&tegra_uart_class},
158 {"nvidia,tegra210-uart", (uintptr_t)&tegra_uart_class},
159 {NULL, (uintptr_t)NULL},
160 };
161
162 UART_FDT_CLASS(compat_data);
163
164 /*
165 * UART Driver interface.
166 */
167 static int
168 uart_fdt_get_shift1(phandle_t node)
169 {
170 pcell_t shift;
171
172 if ((OF_getencprop(node, "reg-shift", &shift, sizeof(shift))) <= 0)
173 shift = 2;
174 return ((int)shift);
175 }
176
177 static int
178 tegra_uart_probe(device_t dev)
179 {
180 struct tegra_softc *sc;
181 phandle_t node;
182 uint64_t freq;
183 int shift;
184 int rv;
185 const struct ofw_compat_data *cd;
186
187 sc = device_get_softc(dev);
188 if (!ofw_bus_status_okay(dev))
189 return (ENXIO);
190 cd = ofw_bus_search_compatible(dev, compat_data);
191 if (cd->ocd_data == 0)
192 return (ENXIO);
193 sc->ns8250_base.base.sc_class = (struct uart_class *)cd->ocd_data;
194 rv = hwreset_get_by_ofw_name(dev, 0, "serial", &sc->reset);
195 if (rv != 0) {
196 device_printf(dev, "Cannot get 'serial' reset\n");
197 return (ENXIO);
198 }
199 rv = hwreset_deassert(sc->reset);
200 if (rv != 0) {
201 device_printf(dev, "Cannot unreset 'serial' reset\n");
202 return (ENXIO);
203 }
204 node = ofw_bus_get_node(dev);
205 shift = uart_fdt_get_shift1(node);
206 rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
207 if (rv != 0) {
208 device_printf(dev, "Cannot get UART clock: %d\n", rv);
209 return (ENXIO);
210 }
211 rv = clk_enable(sc->clk);
212 if (rv != 0) {
213 device_printf(dev, "Cannot enable UART clock: %d\n", rv);
214 return (ENXIO);
215 }
216 rv = clk_get_freq(sc->clk, &freq);
217 if (rv != 0) {
218 device_printf(dev, "Cannot enable UART clock: %d\n", rv);
219 return (ENXIO);
220 }
221 return (uart_bus_probe(dev, shift, 0, (int)freq, 0, 0, 0));
222 }
223
224 static int
225 tegra_uart_detach(device_t dev)
226 {
227 struct tegra_softc *sc;
228
229 sc = device_get_softc(dev);
230 if (sc->clk != NULL) {
231 clk_release(sc->clk);
232 }
233
234 return (uart_bus_detach(dev));
235 }
236
237 static device_method_t tegra_uart_bus_methods[] = {
238 /* Device interface */
239 DEVMETHOD(device_probe, tegra_uart_probe),
240 DEVMETHOD(device_attach, uart_bus_attach),
241 DEVMETHOD(device_detach, tegra_uart_detach),
242 { 0, 0 }
243 };
244
245 static driver_t tegra_uart_driver = {
246 uart_driver_name,
247 tegra_uart_bus_methods,
248 sizeof(struct tegra_softc),
249 };
250
251 DRIVER_MODULE(tegra_uart, simplebus, tegra_uart_driver, uart_devclass,
252 0, 0);
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