Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/arm/nvidia/tegra_usbphy.c
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1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * USB phy driver for Tegra SoCs. 32 */ 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/malloc.h> 39 #include <sys/rman.h> 40 41 #include <machine/bus.h> 42 43 #include <dev/extres/clk/clk.h> 44 #include <dev/extres/hwreset/hwreset.h> 45 #include <dev/extres/phy/phy.h> 46 #include <dev/extres/regulator/regulator.h> 47 #include <dev/fdt/fdt_pinctrl.h> 48 #include <dev/ofw/openfirm.h> 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include "phynode_if.h" 53 54 #define CTRL_ICUSB_CTRL 0x15c 55 #define ICUSB_CTR_IC_ENB1 (1 << 3) 56 57 #define CTRL_USB_USBMODE 0x1f8 58 #define USB_USBMODE_MASK (3 << 0) 59 #define USB_USBMODE_HOST (3 << 0) 60 #define USB_USBMODE_DEVICE (2 << 0) 61 62 #define CTRL_USB_HOSTPC1_DEVLC 0x1b4 63 #define USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29) 64 #define USB_HOSTPC1_DEVLC_STS (1 << 28) 65 #define USB_HOSTPC1_DEVLC_PHCD (1 << 22) 66 67 #define IF_USB_SUSP_CTRL 0x400 68 #define FAST_WAKEUP_RESP (1 << 26) 69 #define UTMIP_SUSPL1_SET (1 << 25) 70 #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16) 71 #define USB_SUSP_SET (1 << 14) 72 #define UTMIP_PHY_ENB (1 << 12) 73 #define UTMIP_RESET (1 << 11) 74 #define USB_SUSP_POL (1 << 10) 75 #define USB_PHY_CLK_VALID_INT_ENB (1 << 9) 76 #define USB_PHY_CLK_VALID_INT_STS (1 << 8) 77 #define USB_PHY_CLK_VALID (1 << 7) 78 #define USB_CLKEN (1 << 6) 79 #define USB_SUSP_CLR (1 << 5) 80 #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4) 81 #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3) 82 #define USB_WAKE_ON_RESUME_EN (1 << 2) 83 #define USB_WAKEUP_INT_ENB (1 << 1) 84 #define USB_WAKEUP_INT_STS (1 << 0) 85 86 #define IF_USB_PHY_VBUS_SENSORS 0x404 87 #define B_SESS_END_SW_VALUE (1 << 4) 88 #define B_SESS_END_SW_EN (1 << 3) 89 90 #define UTMIP_XCVR_CFG0 0x808 91 #define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25) 92 #define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22) 93 #define UTMIP_XCVR_LSBIAS_SEL (1 << 21) 94 #define UTMIP_XCVR_DISCON_METHOD (1 << 20) 95 #define UTMIP_FORCE_PDZI_POWERUP (1 << 19) 96 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) 97 #define UTMIP_FORCE_PD2_POWERUP (1 << 17) 98 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) 99 #define UTMIP_FORCE_PD_POWERUP (1 << 15) 100 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14) 101 #define UTMIP_XCVR_TERMEN (1 << 13) 102 #define UTMIP_XCVR_HSLOOPBACK (1 << 12) 103 #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) 104 #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) 105 #define UTMIP_XCVR_FSSLEW(x) (((x) & 0x3) << 6) 106 #define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4) 107 #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) 108 109 #define UTMIP_BIAS_CFG0 0x80C 110 #define UTMIP_IDDIG_C_VAL (1 << 30) 111 #define UTMIP_IDDIG_C_SEL (1 << 29) 112 #define UTMIP_IDDIG_B_VAL (1 << 28) 113 #define UTMIP_IDDIG_B_SEL (1 << 27) 114 #define UTMIP_IDDIG_A_VAL (1 << 26) 115 #define UTMIP_IDDIG_A_SEL (1 << 25) 116 #define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24) 117 #define UTMIP_IDPD_VAL (1 << 23) 118 #define UTMIP_IDPD_SEL (1 << 22) 119 #define UTMIP_IDDIG_VAL (1 << 21) 120 #define UTMIP_IDDIG_SEL (1 << 20) 121 #define UTMIP_GPI_VAL (1 << 19) 122 #define UTMIP_GPI_SEL (1 << 18) 123 #define UTMIP_ACTIVE_TERM_OFFSET(x) (((x) & 0x7) << 15) 124 #define UTMIP_ACTIVE_PULLUP_OFFSET(x) (((x) & 0x7) << 12) 125 #define UTMIP_OTGPD (1 << 11) 126 #define UTMIP_BIASPD (1 << 10) 127 #define UTMIP_VBUS_LEVEL_LEVEL(x) (((x) & 0x3) << 8) 128 #define UTMIP_SESS_LEVEL_LEVEL(x) (((x) & 0x3) << 6) 129 #define UTMIP_HSCHIRP_LEVEL(x) (((x) & 0x3) << 4) 130 #define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2) 131 #define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0) 132 133 #define UTMIP_HSRX_CFG0 0x810 134 #define UTMIP_KEEP_PATT_ON_ACTIVE(x) (((x) & 0x3) << 30) 135 #define UTMIP_ALLOW_CONSEC_UPDN (1 << 29) 136 #define UTMIP_REALIGN_ON_NEW_PKT (1 << 28) 137 #define UTMIP_PCOUNT_UPDN_DIV(x) (((x) & 0xf) << 24) 138 #define UTMIP_SQUELCH_EOP_DLY(x) (((x) & 0x7) << 21) 139 #define UTMIP_NO_STRIPPING (1 << 20) 140 #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15) 141 #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10) 142 #define UTMIP_ELASTIC_OVERRUN_DISABLE (1 << 9) 143 #define UTMIP_ELASTIC_UNDERRUN_DISABLE (1 << 8) 144 #define UTMIP_PASS_CHIRP (1 << 7) 145 #define UTMIP_PASS_FEEDBACK (1 << 6) 146 #define UTMIP_PCOUNT_INERTIA(x) (((x) & 0x3) << 4) 147 #define UTMIP_PHASE_ADJUST(x) (((x) & 0x3) << 2) 148 #define UTMIP_THREE_SYNCBITS (1 << 1) 149 #define UTMIP_USE4SYNC_TRAN (1 << 0) 150 151 #define UTMIP_HSRX_CFG1 0x814 152 #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1F) << 1) 153 #define UTMIP_HS_ALLOW_KEEP_ALIVE (1 << 0) 154 155 #define UTMIP_TX_CFG0 0x820 156 #define UTMIP_FS_PREAMBLE_J (1 << 19) 157 #define UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE (1 << 18) 158 #define UTMIP_FS_PREAMBLE_OUTPUT_ENABLE (1 << 17) 159 #define UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR (1 << 16) 160 #define UTMIP_HS_READY_WAIT_FOR_VALID (1 << 15) 161 #define UTMIP_HS_TX_IPG_DLY(x) (((x) & 0x1f) << 10) 162 #define UTMIP_HS_DISCON_EOP_ONLY (1 << 9) 163 #define UTMIP_HS_DISCON_DISABLE (1 << 8) 164 #define UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE (1 << 7) 165 #define UTMIP_HS_PREAMBLE_OUTPUT_ENABLE (1 << 6) 166 #define UTMIP_SIE_RESUME_ON_LINESTATE (1 << 5) 167 #define UTMIP_SOF_ON_NO_STUFF (1 << 4) 168 #define UTMIP_SOF_ON_NO_ENCODE (1 << 3) 169 #define UTMIP_NO_STUFFING (1 << 2) 170 #define UTMIP_NO_ENCODING (1 << 1) 171 #define UTMIP_NO_SYNC_NO_EOP (1 << 0) 172 173 #define UTMIP_MISC_CFG0 0x824 174 #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27) 175 #define UTMIP_DPDM_OBSERVE (1 << 26) 176 #define UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON (1 << 25) 177 #define UTMIP_ALLOW_LS_ON_SOFT_DISCON (1 << 24) 178 #define UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP (1 << 23) 179 #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) 180 #define UTMIP_LS_TO_FS_SKIP_4MS (1 << 21) 181 #define UTMIP_INJECT_ERROR_TYPE(x) (((x) & 0x3) << 19) 182 #define UTMIP_FORCE_HS_CLOCK_ON (1 << 18) 183 #define UTMIP_DISABLE_HS_TERM (1 << 17) 184 #define UTMIP_FORCE_HS_TERM (1 << 16) 185 #define UTMIP_DISABLE_PULLUP_DP (1 << 15) 186 #define UTMIP_DISABLE_PULLUP_DM (1 << 14) 187 #define UTMIP_DISABLE_PULLDN_DP (1 << 13) 188 #define UTMIP_DISABLE_PULLDN_DM (1 << 12) 189 #define UTMIP_FORCE_PULLUP_DP (1 << 11) 190 #define UTMIP_FORCE_PULLUP_DM (1 << 10) 191 #define UTMIP_FORCE_PULLDN_DP (1 << 9) 192 #define UTMIP_FORCE_PULLDN_DM (1 << 8) 193 #define UTMIP_STABLE_COUNT(x) (((x) & 0x7) << 5) 194 #define UTMIP_STABLE_ALL (1 << 4) 195 #define UTMIP_NO_FREE_ON_SUSPEND (1 << 3) 196 #define UTMIP_NEVER_FREE_RUNNING_TERMS (1 << 2) 197 #define UTMIP_ALWAYS_FREE_RUNNING_TERMS (1 << 1) 198 #define UTMIP_COMB_TERMS (1 << 0) 199 200 #define UTMIP_MISC_CFG1 0x828 201 #define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) 202 203 #define UTMIP_DEBOUNCE_CFG0 0x82C 204 #define UTMIP_BIAS_DEBOUNCE_B(x) (((x) & 0xffff) << 16) 205 #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0) 206 207 #define UTMIP_BAT_CHRG_CFG0 0x830 208 #define UTMIP_CHRG_DEBOUNCE_TIMESCALE(x) (((x) & 0x1f) << 8) 209 #define UTMIP_OP_I_SRC_ENG (1 << 5) 210 #define UTMIP_ON_SRC_ENG (1 << 4) 211 #define UTMIP_OP_SRC_ENG (1 << 3) 212 #define UTMIP_ON_SINK_ENG (1 << 2) 213 #define UTMIP_OP_SINK_ENG (1 << 1) 214 #define UTMIP_PD_CHRG (1 << 0) 215 216 #define UTMIP_SPARE_CFG0 0x834 217 #define FUSE_HS_IREF_CAP_CFG (1 << 7) 218 #define FUSE_HS_SQUELCH_LEVEL (1 << 6) 219 #define FUSE_SPARE (1 << 5) 220 #define FUSE_TERM_RANGE_ADJ_SEL (1 << 4) 221 #define FUSE_SETUP_SEL (1 << 3) 222 #define HS_RX_LATE_SQUELCH (1 << 2) 223 #define HS_RX_FLUSH_ALAP (1 << 1) 224 #define HS_RX_IPG_ERROR_ENABLE (1 << 0) 225 226 #define UTMIP_XCVR_CFG1 0x838 227 #define UTMIP_XCVR_RPU_RANGE_ADJ(x) (((x) & 0x3) << 26) 228 #define UTMIP_XCVR_HS_IREF_CAP(x) (((x) & 0x3) << 24) 229 #define UTMIP_XCVR_SPARE(x) (((x) & 0x3) << 22) 230 #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18) 231 #define UTMIP_RCTRL_SW_SET (1 << 17) 232 #define UTMIP_RCTRL_SW_VAL(x) (((x) & 0x1f) << 12) 233 #define UTMIP_TCTRL_SW_SET (1 << 11) 234 #define UTMIP_TCTRL_SW_VAL(x) (((x) & 0x1f) << 6) 235 #define UTMIP_FORCE_PDDR_POWERUP (1 << 5) 236 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) 237 #define UTMIP_FORCE_PDCHRP_POWERUP (1 << 3) 238 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) 239 #define UTMIP_FORCE_PDDISC_POWERUP (1 << 1) 240 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) 241 242 #define UTMIP_BIAS_CFG1 0x83c 243 #define UTMIP_BIAS_DEBOUNCE_TIMESCALE(x) (((x) & 0x3f) << 8) 244 #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3) 245 #define UTMIP_VBUS_WAKEUP_POWERDOWN (1 << 2) 246 #define UTMIP_FORCE_PDTRK_POWERUP (1 << 1) 247 #define UTMIP_FORCE_PDTRK_POWERDOWN (1 << 0) 248 249 static int usbpby_enable_cnt; 250 251 enum usb_ifc_type { 252 USB_IFC_TYPE_UNKNOWN = 0, 253 USB_IFC_TYPE_UTMI, 254 USB_IFC_TYPE_ULPI 255 }; 256 257 enum usb_dr_mode { 258 USB_DR_MODE_UNKNOWN = 0, 259 USB_DR_MODE_DEVICE, 260 USB_DR_MODE_HOST, 261 USB_DR_MODE_OTG 262 }; 263 264 struct usbphy_softc { 265 device_t dev; 266 struct resource *mem_res; 267 struct resource *pads_res; 268 clk_t clk_reg; 269 clk_t clk_pads; 270 clk_t clk_pllu; 271 regulator_t supply_vbus; 272 hwreset_t reset_usb; 273 hwreset_t reset_pads; 274 enum usb_ifc_type ifc_type; 275 enum usb_dr_mode dr_mode; 276 bool have_utmi_regs; 277 278 /* UTMI params */ 279 int hssync_start_delay; 280 int elastic_limit; 281 int idle_wait_delay; 282 int term_range_adj; 283 int xcvr_lsfslew; 284 int xcvr_lsrslew; 285 int xcvr_hsslew; 286 int hssquelch_level; 287 int hsdiscon_level; 288 int xcvr_setup; 289 int xcvr_setup_use_fuses; 290 }; 291 292 static struct ofw_compat_data compat_data[] = { 293 {"nvidia,tegra210-usb-phy", 1}, 294 {"nvidia,tegra30-usb-phy", 1}, 295 {NULL, 0}, 296 }; 297 298 /* Phy controller class and methods. */ 299 static int usbphy_phy_enable(struct phynode *phy, bool enable); 300 static phynode_method_t usbphy_phynode_methods[] = { 301 PHYNODEMETHOD(phynode_enable, usbphy_phy_enable), 302 303 PHYNODEMETHOD_END 304 }; 305 DEFINE_CLASS_1(usbphy_phynode, usbphy_phynode_class, usbphy_phynode_methods, 306 0, phynode_class); 307 308 #define RD4(sc, offs) \ 309 bus_read_4(sc->mem_res, offs) 310 311 #define WR4(sc, offs, val) \ 312 bus_write_4(sc->mem_res, offs, val) 313 314 static int 315 reg_wait(struct usbphy_softc *sc, uint32_t reg, uint32_t mask, uint32_t val) 316 { 317 int i; 318 319 for (i = 0; i < 1000; i++) { 320 if ((RD4(sc, reg) & mask) == val) 321 return (0); 322 DELAY(10); 323 } 324 return (ETIMEDOUT); 325 } 326 327 static int 328 usbphy_utmi_phy_clk(struct usbphy_softc *sc, bool enable) 329 { 330 uint32_t val; 331 int rv; 332 333 val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC); 334 if (enable) 335 val &= ~USB_HOSTPC1_DEVLC_PHCD; 336 else 337 val |= USB_HOSTPC1_DEVLC_PHCD; 338 WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val); 339 340 rv = reg_wait(sc, IF_USB_SUSP_CTRL, USB_PHY_CLK_VALID, 341 enable ? USB_PHY_CLK_VALID: 0); 342 if (rv != 0) { 343 device_printf(sc->dev, "USB phy clock timeout.\n"); 344 return (ETIMEDOUT); 345 } 346 return (0); 347 } 348 349 static int 350 usbphy_utmi_enable(struct usbphy_softc *sc) 351 { 352 int rv; 353 uint32_t val; 354 355 /* Reset phy */ 356 val = RD4(sc, IF_USB_SUSP_CTRL); 357 val |= UTMIP_RESET; 358 WR4(sc, IF_USB_SUSP_CTRL, val); 359 360 val = RD4(sc, UTMIP_TX_CFG0); 361 val |= UTMIP_FS_PREAMBLE_J; 362 WR4(sc, UTMIP_TX_CFG0, val); 363 364 val = RD4(sc, UTMIP_HSRX_CFG0); 365 val &= ~UTMIP_IDLE_WAIT(~0); 366 val &= ~UTMIP_ELASTIC_LIMIT(~0); 367 val |= UTMIP_IDLE_WAIT(sc->idle_wait_delay); 368 val |= UTMIP_ELASTIC_LIMIT(sc->elastic_limit); 369 WR4(sc, UTMIP_HSRX_CFG0, val); 370 371 val = RD4(sc, UTMIP_HSRX_CFG1); 372 val &= ~UTMIP_HS_SYNC_START_DLY(~0); 373 val |= UTMIP_HS_SYNC_START_DLY(sc->hssync_start_delay); 374 WR4(sc, UTMIP_HSRX_CFG1, val); 375 376 val = RD4(sc, UTMIP_DEBOUNCE_CFG0); 377 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); 378 val |= UTMIP_BIAS_DEBOUNCE_A(0x7530); /* For 12MHz */ 379 WR4(sc, UTMIP_DEBOUNCE_CFG0, val); 380 381 val = RD4(sc, UTMIP_MISC_CFG0); 382 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; 383 WR4(sc, UTMIP_MISC_CFG0, val); 384 385 if (sc->dr_mode == USB_DR_MODE_DEVICE) { 386 val = RD4(sc,IF_USB_SUSP_CTRL); 387 val &= ~USB_WAKE_ON_CNNT_EN_DEV; 388 val &= ~USB_WAKE_ON_DISCON_EN_DEV; 389 WR4(sc, IF_USB_SUSP_CTRL, val); 390 391 val = RD4(sc, UTMIP_BAT_CHRG_CFG0); 392 val &= ~UTMIP_PD_CHRG; 393 WR4(sc, UTMIP_BAT_CHRG_CFG0, val); 394 } else { 395 val = RD4(sc, UTMIP_BAT_CHRG_CFG0); 396 val |= UTMIP_PD_CHRG; 397 WR4(sc, UTMIP_BAT_CHRG_CFG0, val); 398 } 399 400 usbpby_enable_cnt++; 401 if (usbpby_enable_cnt == 1) { 402 rv = hwreset_deassert(sc->reset_pads); 403 if (rv != 0) { 404 device_printf(sc->dev, 405 "Cannot unreset 'utmi-pads' reset\n"); 406 return (rv); 407 } 408 rv = clk_enable(sc->clk_pads); 409 if (rv != 0) { 410 device_printf(sc->dev, 411 "Cannot enable 'utmi-pads' clock\n"); 412 return (rv); 413 } 414 415 val = bus_read_4(sc->pads_res, UTMIP_BIAS_CFG0); 416 val &= ~UTMIP_OTGPD; 417 val &= ~UTMIP_BIASPD; 418 val &= ~UTMIP_HSSQUELCH_LEVEL(~0); 419 val &= ~UTMIP_HSDISCON_LEVEL(~0); 420 val &= ~UTMIP_HSDISCON_LEVEL_MSB(~0); 421 val |= UTMIP_HSSQUELCH_LEVEL(sc->hssquelch_level); 422 val |= UTMIP_HSDISCON_LEVEL(sc->hsdiscon_level); 423 val |= UTMIP_HSDISCON_LEVEL_MSB(sc->hsdiscon_level); 424 bus_write_4(sc->pads_res, UTMIP_BIAS_CFG0, val); 425 426 rv = clk_disable(sc->clk_pads); 427 if (rv != 0) { 428 device_printf(sc->dev, 429 "Cannot disable 'utmi-pads' clock\n"); 430 return (rv); 431 } 432 } 433 434 val = RD4(sc, UTMIP_XCVR_CFG0); 435 val &= ~UTMIP_FORCE_PD_POWERDOWN; 436 val &= ~UTMIP_FORCE_PD2_POWERDOWN ; 437 val &= ~UTMIP_FORCE_PDZI_POWERDOWN; 438 val &= ~UTMIP_XCVR_LSBIAS_SEL; 439 val &= ~UTMIP_XCVR_LSFSLEW(~0); 440 val &= ~UTMIP_XCVR_LSRSLEW(~0); 441 val &= ~UTMIP_XCVR_HSSLEW(~0); 442 val &= ~UTMIP_XCVR_HSSLEW_MSB(~0); 443 val |= UTMIP_XCVR_LSFSLEW(sc->xcvr_lsfslew); 444 val |= UTMIP_XCVR_LSRSLEW(sc->xcvr_lsrslew); 445 val |= UTMIP_XCVR_HSSLEW(sc->xcvr_hsslew); 446 val |= UTMIP_XCVR_HSSLEW_MSB(sc->xcvr_hsslew); 447 if (!sc->xcvr_setup_use_fuses) { 448 val &= ~UTMIP_XCVR_SETUP(~0); 449 val &= ~UTMIP_XCVR_SETUP_MSB(~0); 450 val |= UTMIP_XCVR_SETUP(sc->xcvr_setup); 451 val |= UTMIP_XCVR_SETUP_MSB(sc->xcvr_setup); 452 } 453 WR4(sc, UTMIP_XCVR_CFG0, val); 454 455 val = RD4(sc, UTMIP_XCVR_CFG1); 456 val &= ~UTMIP_FORCE_PDDISC_POWERDOWN; 457 val &= ~UTMIP_FORCE_PDCHRP_POWERDOWN; 458 val &= ~UTMIP_FORCE_PDDR_POWERDOWN; 459 val &= ~UTMIP_XCVR_TERM_RANGE_ADJ(~0); 460 val |= UTMIP_XCVR_TERM_RANGE_ADJ(sc->term_range_adj); 461 WR4(sc, UTMIP_XCVR_CFG1, val); 462 463 val = RD4(sc, UTMIP_BIAS_CFG1); 464 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); 465 val |= UTMIP_BIAS_PDTRK_COUNT(0x5); 466 WR4(sc, UTMIP_BIAS_CFG1, val); 467 468 val = RD4(sc, UTMIP_SPARE_CFG0); 469 if (sc->xcvr_setup_use_fuses) 470 val |= FUSE_SETUP_SEL; 471 else 472 val &= ~FUSE_SETUP_SEL; 473 WR4(sc, UTMIP_SPARE_CFG0, val); 474 475 val = RD4(sc, IF_USB_SUSP_CTRL); 476 val |= UTMIP_PHY_ENB; 477 WR4(sc, IF_USB_SUSP_CTRL, val); 478 479 val = RD4(sc, IF_USB_SUSP_CTRL); 480 val &= ~UTMIP_RESET; 481 WR4(sc, IF_USB_SUSP_CTRL, val); 482 483 usbphy_utmi_phy_clk(sc, true); 484 485 val = RD4(sc, CTRL_USB_USBMODE); 486 val &= ~USB_USBMODE_MASK; 487 if (sc->dr_mode == USB_DR_MODE_HOST) 488 val |= USB_USBMODE_HOST; 489 else 490 val |= USB_USBMODE_DEVICE; 491 WR4(sc, CTRL_USB_USBMODE, val); 492 493 val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC); 494 val &= ~USB_HOSTPC1_DEVLC_PTS(~0); 495 val |= USB_HOSTPC1_DEVLC_PTS(0); 496 WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val); 497 498 return (0); 499 } 500 501 static int 502 usbphy_utmi_disable(struct usbphy_softc *sc) 503 { 504 int rv; 505 uint32_t val; 506 507 usbphy_utmi_phy_clk(sc, false); 508 509 if (sc->dr_mode == USB_DR_MODE_DEVICE) { 510 val = RD4(sc, IF_USB_SUSP_CTRL); 511 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); 512 val |= USB_WAKE_ON_CNNT_EN_DEV; 513 val |= USB_WAKEUP_DEBOUNCE_COUNT(5); 514 WR4(sc, IF_USB_SUSP_CTRL, val); 515 } 516 517 val = RD4(sc, IF_USB_SUSP_CTRL); 518 val |= UTMIP_RESET; 519 WR4(sc, IF_USB_SUSP_CTRL, val); 520 521 val = RD4(sc, UTMIP_BAT_CHRG_CFG0); 522 val |= UTMIP_PD_CHRG; 523 WR4(sc, UTMIP_BAT_CHRG_CFG0, val); 524 525 val = RD4(sc, UTMIP_XCVR_CFG0); 526 val |= UTMIP_FORCE_PD_POWERDOWN; 527 val |= UTMIP_FORCE_PD2_POWERDOWN; 528 val |= UTMIP_FORCE_PDZI_POWERDOWN; 529 WR4(sc, UTMIP_XCVR_CFG0, val); 530 531 val = RD4(sc, UTMIP_XCVR_CFG1); 532 val |= UTMIP_FORCE_PDDISC_POWERDOWN; 533 val |= UTMIP_FORCE_PDCHRP_POWERDOWN; 534 val |= UTMIP_FORCE_PDDR_POWERDOWN; 535 WR4(sc, UTMIP_XCVR_CFG1, val); 536 537 usbpby_enable_cnt--; 538 if (usbpby_enable_cnt <= 0) { 539 rv = clk_enable(sc->clk_pads); 540 if (rv != 0) { 541 device_printf(sc->dev, 542 "Cannot enable 'utmi-pads' clock\n"); 543 return (rv); 544 } 545 val =bus_read_4(sc->pads_res, UTMIP_BIAS_CFG0); 546 val |= UTMIP_OTGPD; 547 val |= UTMIP_BIASPD; 548 bus_write_4(sc->pads_res, UTMIP_BIAS_CFG0, val); 549 550 rv = clk_disable(sc->clk_pads); 551 if (rv != 0) { 552 device_printf(sc->dev, 553 "Cannot disable 'utmi-pads' clock\n"); 554 return (rv); 555 } 556 } 557 return (0); 558 } 559 560 static int 561 usbphy_phy_enable(struct phynode *phy, bool enable) 562 { 563 device_t dev; 564 struct usbphy_softc *sc; 565 int rv = 0; 566 567 dev = phynode_get_device(phy); 568 sc = device_get_softc(dev); 569 570 if (sc->ifc_type != USB_IFC_TYPE_UTMI) { 571 device_printf(sc->dev, 572 "Only UTMI interface is supported.\n"); 573 return (ENXIO); 574 } 575 if (enable) 576 rv = usbphy_utmi_enable(sc); 577 else 578 rv = usbphy_utmi_disable(sc); 579 580 return (rv); 581 } 582 583 static enum usb_ifc_type 584 usb_get_ifc_mode(device_t dev, phandle_t node, char *name) 585 { 586 char *tmpstr; 587 int rv; 588 enum usb_ifc_type ret; 589 590 rv = OF_getprop_alloc(node, name, (void **)&tmpstr); 591 if (rv <= 0) 592 return (USB_IFC_TYPE_UNKNOWN); 593 594 ret = USB_IFC_TYPE_UNKNOWN; 595 if (strcmp(tmpstr, "utmi") == 0) 596 ret = USB_IFC_TYPE_UTMI; 597 else if (strcmp(tmpstr, "ulpi") == 0) 598 ret = USB_IFC_TYPE_ULPI; 599 else 600 device_printf(dev, "Unsupported phy type: %s\n", tmpstr); 601 OF_prop_free(tmpstr); 602 return (ret); 603 } 604 605 static enum usb_dr_mode 606 usb_get_dr_mode(device_t dev, phandle_t node, char *name) 607 { 608 char *tmpstr; 609 int rv; 610 enum usb_dr_mode ret; 611 612 rv = OF_getprop_alloc(node, name, (void **)&tmpstr); 613 if (rv <= 0) 614 return (USB_DR_MODE_UNKNOWN); 615 616 ret = USB_DR_MODE_UNKNOWN; 617 if (strcmp(tmpstr, "device") == 0) 618 ret = USB_DR_MODE_DEVICE; 619 else if (strcmp(tmpstr, "host") == 0) 620 ret = USB_DR_MODE_HOST; 621 else if (strcmp(tmpstr, "otg") == 0) 622 ret = USB_DR_MODE_OTG; 623 else 624 device_printf(dev, "Unknown dr mode: %s\n", tmpstr); 625 OF_prop_free(tmpstr); 626 return (ret); 627 } 628 629 static int 630 usbphy_utmi_read_params(struct usbphy_softc *sc, phandle_t node) 631 { 632 int rv; 633 634 rv = OF_getencprop(node, "nvidia,hssync-start-delay", 635 &sc->hssync_start_delay, sizeof (sc->hssync_start_delay)); 636 if (rv <= 0) 637 return (ENXIO); 638 639 rv = OF_getencprop(node, "nvidia,elastic-limit", 640 &sc->elastic_limit, sizeof (sc->elastic_limit)); 641 if (rv <= 0) 642 return (ENXIO); 643 644 rv = OF_getencprop(node, "nvidia,idle-wait-delay", 645 &sc->idle_wait_delay, sizeof (sc->idle_wait_delay)); 646 if (rv <= 0) 647 return (ENXIO); 648 649 rv = OF_getencprop(node, "nvidia,term-range-adj", 650 &sc->term_range_adj, sizeof (sc->term_range_adj)); 651 if (rv <= 0) 652 return (ENXIO); 653 654 rv = OF_getencprop(node, "nvidia,xcvr-lsfslew", 655 &sc->xcvr_lsfslew, sizeof (sc->xcvr_lsfslew)); 656 if (rv <= 0) 657 return (ENXIO); 658 659 rv = OF_getencprop(node, "nvidia,xcvr-lsrslew", 660 &sc->xcvr_lsrslew, sizeof (sc->xcvr_lsrslew)); 661 if (rv <= 0) 662 return (ENXIO); 663 664 rv = OF_getencprop(node, "nvidia,xcvr-hsslew", 665 &sc->xcvr_hsslew, sizeof (sc->xcvr_hsslew)); 666 if (rv <= 0) 667 return (ENXIO); 668 669 rv = OF_getencprop(node, "nvidia,hssquelch-level", 670 &sc->hssquelch_level, sizeof (sc->hssquelch_level)); 671 if (rv <= 0) 672 return (ENXIO); 673 674 rv = OF_getencprop(node, "nvidia,hsdiscon-level", 675 &sc->hsdiscon_level, sizeof (sc->hsdiscon_level)); 676 if (rv <= 0) 677 return (ENXIO); 678 679 rv = OF_getproplen(node, "nvidia,xcvr-setup-use-fuses"); 680 if (rv >= 1) { 681 sc->xcvr_setup_use_fuses = 1; 682 } else { 683 rv = OF_getencprop(node, "nvidia,xcvr-setup", 684 &sc->xcvr_setup, sizeof (sc->xcvr_setup)); 685 if (rv <= 0) 686 return (ENXIO); 687 } 688 689 return (0); 690 } 691 692 static int 693 usbphy_probe(device_t dev) 694 { 695 696 if (!ofw_bus_status_okay(dev)) 697 return (ENXIO); 698 699 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 700 return (ENXIO); 701 702 device_set_desc(dev, "Tegra USB phy"); 703 return (BUS_PROBE_DEFAULT); 704 } 705 706 static int 707 usbphy_attach(device_t dev) 708 { 709 struct usbphy_softc *sc; 710 int rid, rv; 711 phandle_t node; 712 struct phynode *phynode; 713 struct phynode_init_def phy_init; 714 715 sc = device_get_softc(dev); 716 sc->dev = dev; 717 718 rid = 0; 719 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 720 RF_ACTIVE | RF_SHAREABLE); 721 if (sc->mem_res == NULL) { 722 device_printf(dev, "Cannot allocate memory resources\n"); 723 return (ENXIO); 724 } 725 726 rid = 1; 727 sc->pads_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 728 RF_ACTIVE | RF_SHAREABLE); 729 if (sc->mem_res == NULL) { 730 device_printf(dev, "Cannot allocate memory resources\n"); 731 return (ENXIO); 732 } 733 734 node = ofw_bus_get_node(dev); 735 736 rv = hwreset_get_by_ofw_name(sc->dev, 0, "usb", &sc->reset_usb); 737 if (rv != 0) { 738 device_printf(dev, "Cannot get 'usb' reset\n"); 739 return (ENXIO); 740 } 741 rv = hwreset_get_by_ofw_name(sc->dev, 0, "utmi-pads", &sc->reset_pads); 742 if (rv != 0) { 743 device_printf(dev, "Cannot get 'utmi-pads' reset\n"); 744 return (ENXIO); 745 } 746 747 rv = clk_get_by_ofw_name(sc->dev, 0, "reg", &sc->clk_reg); 748 if (rv != 0) { 749 device_printf(sc->dev, "Cannot get 'reg' clock\n"); 750 return (ENXIO); 751 } 752 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_u", &sc->clk_pllu); 753 if (rv != 0) { 754 device_printf(sc->dev, "Cannot get 'pll_u' clock\n"); 755 return (ENXIO); 756 } 757 rv = clk_get_by_ofw_name(sc->dev, 0, "utmi-pads", &sc->clk_pads); 758 if (rv != 0) { 759 device_printf(sc->dev, "Cannot get 'utmi-pads' clock\n"); 760 return (ENXIO); 761 } 762 763 rv = hwreset_deassert(sc->reset_usb); 764 if (rv != 0) { 765 device_printf(dev, "Cannot unreset 'usb' reset\n"); 766 return (ENXIO); 767 } 768 769 rv = clk_enable(sc->clk_pllu); 770 if (rv != 0) { 771 device_printf(sc->dev, "Cannot enable 'pllu' clock\n"); 772 return (ENXIO); 773 } 774 rv = clk_enable(sc->clk_reg); 775 if (rv != 0) { 776 device_printf(sc->dev, "Cannot enable 'reg' clock\n"); 777 return (ENXIO); 778 } 779 if (OF_hasprop(node, "nvidia,has-utmi-pad-registers")) 780 sc->have_utmi_regs = true; 781 782 sc->dr_mode = usb_get_dr_mode(dev, node, "dr_mode"); 783 if (sc->dr_mode == USB_DR_MODE_UNKNOWN) 784 sc->dr_mode = USB_DR_MODE_HOST; 785 786 sc->ifc_type = usb_get_ifc_mode(dev, node, "phy_type"); 787 788 /* We supports only utmi phy mode for now .... */ 789 if (sc->ifc_type != USB_IFC_TYPE_UTMI) { 790 device_printf(dev, "Unsupported phy type\n"); 791 return (ENXIO); 792 } 793 rv = usbphy_utmi_read_params(sc, node); 794 if (rv < 0) 795 return rv; 796 797 if (OF_hasprop(node, "vbus-supply")) { 798 rv = regulator_get_by_ofw_property(sc->dev, 0, "vbus-supply", 799 &sc->supply_vbus); 800 if (rv != 0) { 801 device_printf(sc->dev, 802 "Cannot get \"vbus\" regulator\n"); 803 return (ENXIO); 804 } 805 rv = regulator_enable(sc->supply_vbus); 806 if (rv != 0) { 807 device_printf(sc->dev, 808 "Cannot enable \"vbus\" regulator\n"); 809 return (rv); 810 } 811 } 812 813 /* Create and register phy. */ 814 bzero(&phy_init, sizeof(phy_init)); 815 phy_init.id = 1; 816 phy_init.ofw_node = node; 817 phynode = phynode_create(dev, &usbphy_phynode_class, &phy_init); 818 if (phynode == NULL) { 819 device_printf(sc->dev, "Cannot create phy\n"); 820 return (ENXIO); 821 } 822 if (phynode_register(phynode) == NULL) { 823 device_printf(sc->dev, "Cannot create phy\n"); 824 return (ENXIO); 825 } 826 827 return (0); 828 } 829 830 static int 831 usbphy_detach(device_t dev) 832 { 833 834 /* This device is always present. */ 835 return (EBUSY); 836 } 837 838 static device_method_t tegra_usbphy_methods[] = { 839 /* Device interface */ 840 DEVMETHOD(device_probe, usbphy_probe), 841 DEVMETHOD(device_attach, usbphy_attach), 842 DEVMETHOD(device_detach, usbphy_detach), 843 844 DEVMETHOD_END 845 }; 846 847 static devclass_t tegra_usbphy_devclass; 848 static DEFINE_CLASS_0(usbphy, tegra_usbphy_driver, tegra_usbphy_methods, 849 sizeof(struct usbphy_softc)); 850 EARLY_DRIVER_MODULE(tegra_usbphy, simplebus, tegra_usbphy_driver, 851 tegra_usbphy_devclass, NULL, NULL, 79);
Cache object: 548c217cc244c8e1d4e9fa4d54da4e6b
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