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sys/arm/nvidia/tegra_xhci.c
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1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * XHCI driver for Tegra SoCs. 32 */ 33 #include "opt_bus.h" 34 #include "opt_platform.h" 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/clock.h> 39 #include <sys/condvar.h> 40 #include <sys/firmware.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/mutex.h> 46 #include <sys/rman.h> 47 #include <sys/systm.h> 48 49 #include <vm/vm.h> 50 #include <vm/vm_extern.h> 51 #include <vm/vm_kern.h> 52 #include <vm/pmap.h> 53 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 57 #include <dev/extres/clk/clk.h> 58 #include <dev/extres/hwreset/hwreset.h> 59 #include <dev/extres/phy/phy.h> 60 #include <dev/extres/regulator/regulator.h> 61 #include <dev/ofw/ofw_bus.h> 62 #include <dev/ofw/ofw_bus_subr.h> 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 #include <dev/usb/usb_busdma.h> 66 #include <dev/usb/usb_process.h> 67 #include <dev/usb/usb_controller.h> 68 #include <dev/usb/usb_bus.h> 69 #include <dev/usb/controller/xhci.h> 70 #include <dev/usb/controller/xhcireg.h> 71 72 #include <arm/nvidia/tegra_pmc.h> 73 74 #include "usbdevs.h" 75 76 /* FPCI address space */ 77 #define T_XUSB_CFG_0 0x000 78 #define T_XUSB_CFG_1 0x004 79 #define CFG_1_BUS_MASTER (1 << 2) 80 #define CFG_1_MEMORY_SPACE (1 << 1) 81 #define CFG_1_IO_SPACE (1 << 0) 82 83 #define T_XUSB_CFG_2 0x008 84 #define T_XUSB_CFG_3 0x00C 85 #define T_XUSB_CFG_4 0x010 86 #define CFG_4_BASE_ADDRESS(x) (((x) & 0x1FFFF) << 15) 87 88 #define T_XUSB_CFG_5 0x014 89 #define T_XUSB_CFG_ARU_MAILBOX_CMD 0x0E4 90 #define ARU_MAILBOX_CMD_INT_EN (1U << 31) 91 #define ARU_MAILBOX_CMD_DEST_XHCI (1 << 30) 92 #define ARU_MAILBOX_CMD_DEST_SMI (1 << 29) 93 #define ARU_MAILBOX_CMD_DEST_PME (1 << 28) 94 #define ARU_MAILBOX_CMD_DEST_FALC (1 << 27) 95 96 #define T_XUSB_CFG_ARU_MAILBOX_DATA_IN 0x0E8 97 #define ARU_MAILBOX_DATA_IN_DATA(x) (((x) & 0xFFFFFF) << 0) 98 #define ARU_MAILBOX_DATA_IN_TYPE(x) (((x) & 0x0000FF) << 24) 99 100 #define T_XUSB_CFG_ARU_MAILBOX_DATA_OUT 0x0EC 101 #define ARU_MAILBOX_DATA_OUT_DATA(x) (((x) >> 0) & 0xFFFFFF) 102 #define ARU_MAILBOX_DATA_OUT_TYPE(x) (((x) >> 24) & 0x0000FF) 103 104 #define T_XUSB_CFG_ARU_MAILBOX_OWNER 0x0F0 105 #define ARU_MAILBOX_OWNER_SW 2 106 #define ARU_MAILBOX_OWNER_FW 1 107 #define ARU_MAILBOX_OWNER_NONE 0 108 109 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41C /* ! UNDOCUMENTED ! */ 110 #define ARU_C11_CSBRANGE_PAGE(x) ((x) >> 9) 111 #define ARU_C11_CSBRANGE_ADDR(x) (0x800 + ((x) & 0x1FF)) 112 #define XUSB_CFG_ARU_SMI_INTR 0x428 /* ! UNDOCUMENTED ! */ 113 #define ARU_SMI_INTR_EN (1 << 3) 114 #define ARU_SMI_INTR_FW_HANG (1 << 1) 115 #define XUSB_CFG_ARU_RST 0x42C /* ! UNDOCUMENTED ! */ 116 #define ARU_RST_RESET (1 << 0) 117 118 #define XUSB_HOST_CONFIGURATION 0x180 119 #define CONFIGURATION_CLKEN_OVERRIDE (1U<< 31) 120 #define CONFIGURATION_PW_NO_DEVSEL_ERR_CYA (1 << 19) 121 #define CONFIGURATION_INITIATOR_READ_IDLE (1 << 18) 122 #define CONFIGURATION_INITIATOR_WRITE_IDLE (1 << 17) 123 #define CONFIGURATION_WDATA_LEAD_CYA (1 << 15) 124 #define CONFIGURATION_WR_INTRLV_CYA (1 << 14) 125 #define CONFIGURATION_TARGET_READ_IDLE (1 << 11) 126 #define CONFIGURATION_TARGET_WRITE_IDLE (1 << 10) 127 #define CONFIGURATION_MSI_VEC_EMPTY (1 << 9) 128 #define CONFIGURATION_UFPCI_MSIAW (1 << 7) 129 #define CONFIGURATION_UFPCI_PWPASSPW (1 << 6) 130 #define CONFIGURATION_UFPCI_PASSPW (1 << 5) 131 #define CONFIGURATION_UFPCI_PWPASSNPW (1 << 4) 132 #define CONFIGURATION_DFPCI_PWPASSNPW (1 << 3) 133 #define CONFIGURATION_DFPCI_RSPPASSPW (1 << 2) 134 #define CONFIGURATION_DFPCI_PASSPW (1 << 1) 135 #define CONFIGURATION_EN_FPCI (1 << 0) 136 137 /* IPFS address space */ 138 #define XUSB_HOST_FPCI_ERROR_MASKS 0x184 139 #define FPCI_ERROR_MASTER_ABORT (1 << 2) 140 #define FPCI_ERRORI_DATA_ERROR (1 << 1) 141 #define FPCI_ERROR_TARGET_ABORT (1 << 0) 142 143 #define XUSB_HOST_INTR_MASK 0x188 144 #define INTR_IP_INT_MASK (1 << 16) 145 #define INTR_MSI_MASK (1 << 8) 146 #define INTR_INT_MASK (1 << 0) 147 148 #define XUSB_HOST_CLKGATE_HYSTERESIS 0x1BC 149 150 /* CSB Falcon CPU */ 151 #define XUSB_FALCON_CPUCTL 0x100 152 #define CPUCTL_STOPPED (1 << 5) 153 #define CPUCTL_HALTED (1 << 4) 154 #define CPUCTL_HRESET (1 << 3) 155 #define CPUCTL_SRESET (1 << 2) 156 #define CPUCTL_STARTCPU (1 << 1) 157 #define CPUCTL_IINVAL (1 << 0) 158 159 #define XUSB_FALCON_BOOTVEC 0x104 160 #define XUSB_FALCON_DMACTL 0x10C 161 #define XUSB_FALCON_IMFILLRNG1 0x154 162 #define IMFILLRNG1_TAG_HI(x) (((x) & 0xFFF) << 16) 163 #define IMFILLRNG1_TAG_LO(x) (((x) & 0xFFF) << 0) 164 #define XUSB_FALCON_IMFILLCTL 0x158 165 166 /* CSB mempool */ 167 #define XUSB_CSB_MEMPOOL_APMAP 0x10181C 168 #define APMAP_BOOTPATH (1U << 31) 169 170 #define XUSB_CSB_MEMPOOL_ILOAD_ATTR 0x101A00 171 #define XUSB_CSB_MEMPOOL_ILOAD_BASE_LO 0x101A04 172 #define XUSB_CSB_MEMPOOL_ILOAD_BASE_HI 0x101A08 173 #define XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE 0x101A10 174 #define L2IMEMOP_SIZE_OFFSET(x) (((x) & 0x3FF) << 8) 175 #define L2IMEMOP_SIZE_SIZE(x) (((x) & 0x0FF) << 24) 176 177 #define XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG 0x101A14 178 #define L2IMEMOP_INVALIDATE_ALL (0x40 << 24) 179 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << 24) 180 181 #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT 0x101A18 182 #define L2IMEMOP_RESULT_VLD (1U << 31) 183 184 #define XUSB_CSB_IMEM_BLOCK_SIZE 256 185 186 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000 187 #define TEGRA_XHCI_SS_LOW_SPEED 12000000 188 189 /* MBOX commands. */ 190 #define MBOX_CMD_MSG_ENABLED 1 191 #define MBOX_CMD_INC_FALC_CLOCK 2 192 #define MBOX_CMD_DEC_FALC_CLOCK 3 193 #define MBOX_CMD_INC_SSPI_CLOCK 4 194 #define MBOX_CMD_DEC_SSPI_CLOCK 5 195 #define MBOX_CMD_SET_BW 6 196 #define MBOX_CMD_SET_SS_PWR_GATING 7 197 #define MBOX_CMD_SET_SS_PWR_UNGATING 8 198 #define MBOX_CMD_SAVE_DFE_CTLE_CTX 9 199 #define MBOX_CMD_AIRPLANE_MODE_ENABLED 10 200 #define MBOX_CMD_AIRPLANE_MODE_DISABLED 11 201 #define MBOX_CMD_START_HSIC_IDLE 12 202 #define MBOX_CMD_STOP_HSIC_IDLE 13 203 #define MBOX_CMD_DBC_WAKE_STACK 14 204 #define MBOX_CMD_HSIC_PRETEND_CONNECT 15 205 #define MBOX_CMD_RESET_SSPI 16 206 #define MBOX_CMD_DISABLE_SS_LFPS_DETECTION 17 207 #define MBOX_CMD_ENABLE_SS_LFPS_DETECTION 18 208 209 /* MBOX responses. */ 210 #define MBOX_CMD_ACK (0x80 + 0) 211 #define MBOX_CMD_NAK (0x80 + 1) 212 213 #define IPFS_WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res_ipfs, (_r), (_v)) 214 #define IPFS_RD4(_sc, _r) bus_read_4((_sc)->mem_res_ipfs, (_r)) 215 #define FPCI_WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res_fpci, (_r), (_v)) 216 #define FPCI_RD4(_sc, _r) bus_read_4((_sc)->mem_res_fpci, (_r)) 217 218 #define LOCK(_sc) mtx_lock(&(_sc)->mtx) 219 #define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 220 #define SLEEP(_sc, timeout) \ 221 mtx_sleep(sc, &sc->mtx, 0, "tegra_xhci", timeout); 222 #define LOCK_INIT(_sc) \ 223 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "tegra_xhci", MTX_DEF) 224 #define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx) 225 #define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED) 226 #define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED) 227 228 struct tegra_xusb_fw_hdr { 229 uint32_t boot_loadaddr_in_imem; 230 uint32_t boot_codedfi_offset; 231 uint32_t boot_codetag; 232 uint32_t boot_codesize; 233 234 uint32_t phys_memaddr; 235 uint16_t reqphys_memsize; 236 uint16_t alloc_phys_memsize; 237 238 uint32_t rodata_img_offset; 239 uint32_t rodata_section_start; 240 uint32_t rodata_section_end; 241 uint32_t main_fnaddr; 242 243 uint32_t fwimg_cksum; 244 uint32_t fwimg_created_time; 245 246 uint32_t imem_resident_start; 247 uint32_t imem_resident_end; 248 uint32_t idirect_start; 249 uint32_t idirect_end; 250 uint32_t l2_imem_start; 251 uint32_t l2_imem_end; 252 uint32_t version_id; 253 uint8_t init_ddirect; 254 uint8_t reserved[3]; 255 uint32_t phys_addr_log_buffer; 256 uint32_t total_log_entries; 257 uint32_t dequeue_ptr; 258 uint32_t dummy[2]; 259 uint32_t fwimg_len; 260 uint8_t magic[8]; 261 uint32_t ss_low_power_entry_timeout; 262 uint8_t num_hsic_port; 263 uint8_t ss_portmap; 264 uint8_t build; 265 uint8_t padding[137]; /* Pad to 256 bytes */ 266 }; 267 268 struct xhci_soc; 269 struct tegra_xhci_softc { 270 struct xhci_softc xhci_softc; 271 device_t dev; 272 struct xhci_soc *soc; 273 struct mtx mtx; 274 struct resource *mem_res_fpci; 275 struct resource *mem_res_ipfs; 276 struct resource *irq_res_mbox; 277 void *irq_hdl_mbox; 278 279 clk_t clk_xusb_host; 280 clk_t clk_xusb_gate; 281 clk_t clk_xusb_falcon_src; 282 clk_t clk_xusb_ss; 283 clk_t clk_xusb_hs_src; 284 clk_t clk_xusb_fs_src; 285 hwreset_t hwreset_xusb_host; 286 hwreset_t hwreset_xusb_ss; 287 regulator_t regulators[16]; /* Safe maximum */ 288 phy_t phys[8]; /* Safe maximum */ 289 290 struct intr_config_hook irq_hook; 291 bool xhci_inited; 292 vm_offset_t fw_vaddr; 293 vm_size_t fw_size; 294 }; 295 296 struct xhci_soc { 297 char *fw_name; 298 char **regulator_names; 299 char **phy_names; 300 }; 301 302 /* Tegra 124 config */ 303 static char *tegra124_reg_names[] = { 304 "avddio-pex-supply", 305 "dvddio-pex-supply", 306 "avdd-usb-supply", 307 "avdd-pll-utmip-supply", 308 "avdd-pll-erefe-supply", 309 "avdd-usb-ss-pll-supply", 310 "hvdd-usb-ss-supply", 311 "hvdd-usb-ss-pll-e-supply", 312 NULL 313 }; 314 315 static char *tegra124_phy_names[] = { 316 "usb2-0", 317 "usb2-1", 318 "usb2-2", 319 "usb3-0", 320 NULL 321 }; 322 323 static struct xhci_soc tegra124_soc = 324 { 325 .fw_name = "tegra124_xusb_fw", 326 .regulator_names = tegra124_reg_names, 327 .phy_names = tegra124_phy_names, 328 }; 329 330 /* Tegra 210 config */ 331 static char *tegra210_reg_names[] = { 332 "dvddio-pex-supply", 333 "hvddio-pex-supply", 334 "avdd-usb-supply", 335 "avdd-pll-utmip-supply", 336 "avdd-pll-uerefe-supply", 337 "dvdd-usb-ss-pll-supply", 338 "hvdd-usb-ss-pll-e-supply", 339 NULL 340 }; 341 342 static char *tegra210_phy_names[] = { 343 "usb2-0", 344 "usb2-1", 345 "usb2-2", 346 "usb2-3", 347 "usb3-0", 348 "usb3-1", 349 NULL 350 }; 351 352 static struct xhci_soc tegra210_soc = 353 { 354 .fw_name = "tegra210_xusb_fw", 355 .regulator_names = tegra210_reg_names, 356 .phy_names = tegra210_phy_names, 357 }; 358 359 /* Compatible devices. */ 360 static struct ofw_compat_data compat_data[] = { 361 {"nvidia,tegra124-xusb", (uintptr_t)&tegra124_soc}, 362 {"nvidia,tegra210-xusb", (uintptr_t)&tegra210_soc}, 363 {NULL, 0} 364 }; 365 366 367 static uint32_t 368 CSB_RD4(struct tegra_xhci_softc *sc, uint32_t addr) 369 { 370 371 FPCI_WR4(sc, XUSB_CFG_ARU_C11_CSBRANGE, ARU_C11_CSBRANGE_PAGE(addr)); 372 return (FPCI_RD4(sc, ARU_C11_CSBRANGE_ADDR(addr))); 373 } 374 375 static void 376 CSB_WR4(struct tegra_xhci_softc *sc, uint32_t addr, uint32_t val) 377 { 378 379 FPCI_WR4(sc, XUSB_CFG_ARU_C11_CSBRANGE, ARU_C11_CSBRANGE_PAGE(addr)); 380 FPCI_WR4(sc, ARU_C11_CSBRANGE_ADDR(addr), val); 381 } 382 383 static int 384 get_fdt_resources(struct tegra_xhci_softc *sc, phandle_t node) 385 { 386 int i, rv; 387 388 /* Regulators. */ 389 for (i = 0; sc->soc->regulator_names[i] != NULL; i++) { 390 if (i >= nitems(sc->regulators)) { 391 device_printf(sc->dev, 392 "Too many regulators present in DT.\n"); 393 return (EOVERFLOW); 394 } 395 rv = regulator_get_by_ofw_property(sc->dev, 0, 396 sc->soc->regulator_names[i], sc->regulators + i); 397 if (rv != 0) { 398 device_printf(sc->dev, 399 "Cannot get '%s' regulator\n", 400 sc->soc->regulator_names[i]); 401 return (ENXIO); 402 } 403 } 404 405 rv = hwreset_get_by_ofw_name(sc->dev, 0, "xusb_host", 406 &sc->hwreset_xusb_host); 407 if (rv != 0) { 408 device_printf(sc->dev, "Cannot get 'xusb_host' reset\n"); 409 return (ENXIO); 410 } 411 rv = hwreset_get_by_ofw_name(sc->dev, 0, "xusb_ss", 412 &sc->hwreset_xusb_ss); 413 if (rv != 0) { 414 device_printf(sc->dev, "Cannot get 'xusb_ss' reset\n"); 415 return (ENXIO); 416 } 417 418 /* Phys. */ 419 for (i = 0; sc->soc->phy_names[i] != NULL; i++) { 420 if (i >= nitems(sc->phys)) { 421 device_printf(sc->dev, 422 "Too many phys present in DT.\n"); 423 return (EOVERFLOW); 424 } 425 rv = phy_get_by_ofw_name(sc->dev, 0, sc->soc->phy_names[i], 426 sc->phys + i); 427 if (rv != 0 && rv != ENOENT) { 428 device_printf(sc->dev, "Cannot get '%s' phy.\n", 429 sc->soc->phy_names[i]); 430 return (ENXIO); 431 } 432 } 433 434 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_host", 435 &sc->clk_xusb_host); 436 if (rv != 0) { 437 device_printf(sc->dev, "Cannot get 'xusb_host' clock\n"); 438 return (ENXIO); 439 } 440 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_falcon_src", 441 &sc->clk_xusb_falcon_src); 442 if (rv != 0) { 443 device_printf(sc->dev, "Cannot get 'xusb_falcon_src' clock\n"); 444 return (ENXIO); 445 } 446 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_ss", 447 &sc->clk_xusb_ss); 448 if (rv != 0) { 449 device_printf(sc->dev, "Cannot get 'xusb_ss' clock\n"); 450 return (ENXIO); 451 } 452 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_hs_src", 453 &sc->clk_xusb_hs_src); 454 if (rv != 0) { 455 device_printf(sc->dev, "Cannot get 'xusb_hs_src' clock\n"); 456 return (ENXIO); 457 } 458 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_fs_src", 459 &sc->clk_xusb_fs_src); 460 if (rv != 0) { 461 device_printf(sc->dev, "Cannot get 'xusb_fs_src' clock\n"); 462 return (ENXIO); 463 } 464 /* Clock xusb_gate is missing in mainstream DT */ 465 rv = clk_get_by_name(sc->dev, "xusb_gate", &sc->clk_xusb_gate); 466 if (rv != 0) { 467 device_printf(sc->dev, "Cannot get 'xusb_gate' clock\n"); 468 return (ENXIO); 469 } 470 return (0); 471 } 472 473 static int 474 enable_fdt_resources(struct tegra_xhci_softc *sc) 475 { 476 int i, rv; 477 478 rv = hwreset_assert(sc->hwreset_xusb_host); 479 if (rv != 0) { 480 device_printf(sc->dev, "Cannot reset 'xusb_host' reset\n"); 481 return (rv); 482 } 483 rv = hwreset_assert(sc->hwreset_xusb_ss); 484 if (rv != 0) { 485 device_printf(sc->dev, "Cannot reset 'xusb_ss' reset\n"); 486 return (rv); 487 } 488 489 /* Regulators. */ 490 for (i = 0; i < nitems(sc->regulators); i++) { 491 if (sc->regulators[i] == NULL) 492 continue; 493 rv = regulator_enable(sc->regulators[i]); 494 if (rv != 0) { 495 device_printf(sc->dev, 496 "Cannot enable '%s' regulator\n", 497 sc->soc->regulator_names[i]); 498 return (rv); 499 } 500 } 501 502 /* Power off XUSB host and XUSB SS domains. */ 503 rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 504 if (rv != 0) { 505 device_printf(sc->dev, "Cannot powerdown 'xusba' domain\n"); 506 return (rv); 507 } 508 rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); 509 if (rv != 0) { 510 device_printf(sc->dev, "Cannot powerdown 'xusbc' domain\n"); 511 return (rv); 512 } 513 514 /* Setup XUSB ss_src clock first */ 515 clk_set_freq(sc->clk_xusb_ss, TEGRA_XHCI_SS_HIGH_SPEED, 0); 516 if (rv != 0) 517 return (rv); 518 519 /* The XUSB gate clock must be enabled before XUSBA can be powered. */ 520 rv = clk_enable(sc->clk_xusb_gate); 521 if (rv != 0) { 522 device_printf(sc->dev, 523 "Cannot enable 'xusb_gate' clock\n"); 524 return (rv); 525 } 526 527 /* Power on XUSB host and XUSB SS domains. */ 528 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC, 529 sc->clk_xusb_host, sc->hwreset_xusb_host); 530 if (rv != 0) { 531 device_printf(sc->dev, "Cannot powerup 'xusbc' domain\n"); 532 return (rv); 533 } 534 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA, 535 sc->clk_xusb_ss, sc->hwreset_xusb_ss); 536 if (rv != 0) { 537 device_printf(sc->dev, "Cannot powerup 'xusba' domain\n"); 538 return (rv); 539 } 540 541 /* Enable rest of clocks */ 542 rv = clk_enable(sc->clk_xusb_falcon_src); 543 if (rv != 0) { 544 device_printf(sc->dev, 545 "Cannot enable 'xusb_falcon_src' clock\n"); 546 return (rv); 547 } 548 rv = clk_enable(sc->clk_xusb_fs_src); 549 if (rv != 0) { 550 device_printf(sc->dev, 551 "Cannot enable 'xusb_fs_src' clock\n"); 552 return (rv); 553 } 554 rv = clk_enable(sc->clk_xusb_hs_src); 555 if (rv != 0) { 556 device_printf(sc->dev, 557 "Cannot enable 'xusb_hs_src' clock\n"); 558 return (rv); 559 } 560 561 /* Phys. */ 562 for (i = 0; i < nitems(sc->phys); i++) { 563 if (sc->phys[i] == NULL) 564 continue; 565 rv = phy_enable(sc->phys[i]); 566 if (rv != 0) { 567 device_printf(sc->dev, "Cannot enable '%s' phy\n", 568 sc->soc->phy_names[i]); 569 return (rv); 570 } 571 } 572 573 return (0); 574 } 575 576 /* Respond by ACK/NAK back to FW */ 577 static void 578 mbox_send_ack(struct tegra_xhci_softc *sc, uint32_t cmd, uint32_t data) 579 { 580 uint32_t reg; 581 582 reg = ARU_MAILBOX_DATA_IN_TYPE(cmd) | ARU_MAILBOX_DATA_IN_DATA(data); 583 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_IN, reg); 584 585 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD); 586 reg |= ARU_MAILBOX_CMD_DEST_FALC | ARU_MAILBOX_CMD_INT_EN; 587 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg); 588 } 589 590 /* Sent command to FW */ 591 static int 592 mbox_send_cmd(struct tegra_xhci_softc *sc, uint32_t cmd, uint32_t data) 593 { 594 uint32_t reg; 595 int i; 596 597 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER); 598 if (reg != ARU_MAILBOX_OWNER_NONE) { 599 device_printf(sc->dev, 600 "CPU mailbox is busy: 0x%08X\n", reg); 601 return (EBUSY); 602 } 603 /* XXX Is this right? Retry loop? Wait before send? */ 604 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER, ARU_MAILBOX_OWNER_SW); 605 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER); 606 if (reg != ARU_MAILBOX_OWNER_SW) { 607 device_printf(sc->dev, 608 "Cannot acquire CPU mailbox: 0x%08X\n", reg); 609 return (EBUSY); 610 } 611 reg = ARU_MAILBOX_DATA_IN_TYPE(cmd) | ARU_MAILBOX_DATA_IN_DATA(data); 612 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_IN, reg); 613 614 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD); 615 reg |= ARU_MAILBOX_CMD_DEST_FALC | ARU_MAILBOX_CMD_INT_EN; 616 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg); 617 618 for (i = 250; i > 0; i--) { 619 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER); 620 if (reg == ARU_MAILBOX_OWNER_NONE) 621 break; 622 DELAY(100); 623 } 624 if (i <= 0) { 625 device_printf(sc->dev, 626 "Command response timeout: 0x%08X\n", reg); 627 return (ETIMEDOUT); 628 } 629 630 return(0); 631 } 632 633 static void 634 process_msg(struct tegra_xhci_softc *sc, uint32_t req_cmd, uint32_t req_data, 635 uint32_t *resp_cmd, uint32_t *resp_data) 636 { 637 uint64_t freq; 638 int rv; 639 640 /* In most cases, data are echoed back. */ 641 *resp_data = req_data; 642 switch (req_cmd) { 643 case MBOX_CMD_INC_FALC_CLOCK: 644 case MBOX_CMD_DEC_FALC_CLOCK: 645 rv = clk_set_freq(sc->clk_xusb_falcon_src, req_data * 1000ULL, 646 0); 647 if (rv == 0) { 648 rv = clk_get_freq(sc->clk_xusb_falcon_src, &freq); 649 *resp_data = (uint32_t)(freq / 1000); 650 } 651 *resp_cmd = rv == 0 ? MBOX_CMD_ACK: MBOX_CMD_NAK; 652 break; 653 654 case MBOX_CMD_INC_SSPI_CLOCK: 655 case MBOX_CMD_DEC_SSPI_CLOCK: 656 rv = clk_set_freq(sc->clk_xusb_ss, req_data * 1000ULL, 657 0); 658 if (rv == 0) { 659 rv = clk_get_freq(sc->clk_xusb_ss, &freq); 660 *resp_data = (uint32_t)(freq / 1000); 661 } 662 *resp_cmd = rv == 0 ? MBOX_CMD_ACK: MBOX_CMD_NAK; 663 break; 664 665 case MBOX_CMD_SET_BW: 666 /* No respense is expected. */ 667 *resp_cmd = 0; 668 break; 669 670 case MBOX_CMD_SET_SS_PWR_GATING: 671 case MBOX_CMD_SET_SS_PWR_UNGATING: 672 *resp_cmd = MBOX_CMD_NAK; 673 break; 674 675 case MBOX_CMD_SAVE_DFE_CTLE_CTX: 676 /* Not implemented yet. */ 677 *resp_cmd = MBOX_CMD_ACK; 678 break; 679 680 case MBOX_CMD_START_HSIC_IDLE: 681 case MBOX_CMD_STOP_HSIC_IDLE: 682 /* Not implemented yet. */ 683 *resp_cmd = MBOX_CMD_NAK; 684 break; 685 686 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION: 687 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION: 688 /* Not implemented yet. */ 689 *resp_cmd = MBOX_CMD_NAK; 690 break; 691 692 case MBOX_CMD_AIRPLANE_MODE_ENABLED: 693 case MBOX_CMD_AIRPLANE_MODE_DISABLED: 694 case MBOX_CMD_DBC_WAKE_STACK: 695 case MBOX_CMD_HSIC_PRETEND_CONNECT: 696 case MBOX_CMD_RESET_SSPI: 697 device_printf(sc->dev, 698 "Received unused/unexpected command: %u\n", req_cmd); 699 *resp_cmd = 0; 700 break; 701 702 default: 703 device_printf(sc->dev, 704 "Received unknown command: %u\n", req_cmd); 705 } 706 } 707 708 static void 709 intr_mbox(void *arg) 710 { 711 struct tegra_xhci_softc *sc; 712 uint32_t reg, msg, resp_cmd, resp_data; 713 714 sc = (struct tegra_xhci_softc *)arg; 715 716 /* Clear interrupt first */ 717 reg = FPCI_RD4(sc, XUSB_CFG_ARU_SMI_INTR); 718 FPCI_WR4(sc, XUSB_CFG_ARU_SMI_INTR, reg); 719 if (reg & ARU_SMI_INTR_FW_HANG) { 720 device_printf(sc->dev, 721 "XUSB CPU firmware hang!!! CPUCTL: 0x%08X\n", 722 CSB_RD4(sc, XUSB_FALCON_CPUCTL)); 723 } 724 725 msg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT); 726 resp_cmd = 0; 727 process_msg(sc, ARU_MAILBOX_DATA_OUT_TYPE(msg), 728 ARU_MAILBOX_DATA_OUT_DATA(msg), &resp_cmd, &resp_data); 729 if (resp_cmd != 0) 730 mbox_send_ack(sc, resp_cmd, resp_data); 731 else 732 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER, 733 ARU_MAILBOX_OWNER_NONE); 734 735 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD); 736 reg &= ~ARU_MAILBOX_CMD_DEST_SMI; 737 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg); 738 739 } 740 741 static int 742 load_fw(struct tegra_xhci_softc *sc) 743 { 744 const struct firmware *fw; 745 const struct tegra_xusb_fw_hdr *fw_hdr; 746 vm_paddr_t fw_paddr, fw_base; 747 vm_offset_t fw_vaddr; 748 vm_size_t fw_size; 749 uint32_t code_tags, code_size; 750 struct clocktime fw_clock; 751 struct timespec fw_timespec; 752 int i; 753 754 /* Reset ARU */ 755 FPCI_WR4(sc, XUSB_CFG_ARU_RST, ARU_RST_RESET); 756 DELAY(3000); 757 758 /* Check if FALCON already runs */ 759 if (CSB_RD4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO) != 0) { 760 device_printf(sc->dev, 761 "XUSB CPU is already loaded, CPUCTL: 0x%08X\n", 762 CSB_RD4(sc, XUSB_FALCON_CPUCTL)); 763 return (0); 764 } 765 766 fw = firmware_get(sc->soc->fw_name); 767 if (fw == NULL) { 768 device_printf(sc->dev, "Cannot read xusb firmware\n"); 769 return (ENOENT); 770 } 771 772 /* Allocate uncached memory and copy firmware into. */ 773 fw_hdr = (const struct tegra_xusb_fw_hdr *)fw->data; 774 fw_size = fw_hdr->fwimg_len; 775 776 fw_vaddr = kmem_alloc_contig(fw_size, M_WAITOK, 0, -1UL, PAGE_SIZE, 0, 777 VM_MEMATTR_UNCACHEABLE); 778 fw_paddr = vtophys(fw_vaddr); 779 fw_hdr = (const struct tegra_xusb_fw_hdr *)fw_vaddr; 780 memcpy((void *)fw_vaddr, fw->data, fw_size); 781 782 firmware_put(fw, FIRMWARE_UNLOAD); 783 sc->fw_vaddr = fw_vaddr; 784 sc->fw_size = fw_size; 785 786 /* Setup firmware physical address and size. */ 787 fw_base = fw_paddr + sizeof(*fw_hdr); 788 CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_ATTR, fw_size); 789 CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO, fw_base & 0xFFFFFFFF); 790 CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI, (uint64_t)fw_base >> 32); 791 CSB_WR4(sc, XUSB_CSB_MEMPOOL_APMAP, APMAP_BOOTPATH); 792 793 /* Invalidate full L2IMEM context. */ 794 CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG, 795 L2IMEMOP_INVALIDATE_ALL); 796 797 /* Program load of L2IMEM by boot code. */ 798 code_tags = howmany(fw_hdr->boot_codetag, XUSB_CSB_IMEM_BLOCK_SIZE); 799 code_size = howmany(fw_hdr->boot_codesize, XUSB_CSB_IMEM_BLOCK_SIZE); 800 CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE, 801 L2IMEMOP_SIZE_OFFSET(code_tags) | 802 L2IMEMOP_SIZE_SIZE(code_size)); 803 804 /* Execute L2IMEM boot code fetch. */ 805 CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG, 806 L2IMEMOP_LOAD_LOCKED_RESULT); 807 808 /* Program FALCON auto-fill range and block count */ 809 CSB_WR4(sc, XUSB_FALCON_IMFILLCTL, code_size); 810 CSB_WR4(sc, XUSB_FALCON_IMFILLRNG1, 811 IMFILLRNG1_TAG_LO(code_tags) | 812 IMFILLRNG1_TAG_HI(code_tags + code_size)); 813 814 CSB_WR4(sc, XUSB_FALCON_DMACTL, 0); 815 /* Wait for CPU */ 816 for (i = 500; i > 0; i--) { 817 if (CSB_RD4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT) & 818 L2IMEMOP_RESULT_VLD) 819 break; 820 DELAY(100); 821 } 822 if (i <= 0) { 823 device_printf(sc->dev, "Timedout while wating for DMA, " 824 "state: 0x%08X\n", 825 CSB_RD4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT)); 826 return (ETIMEDOUT); 827 } 828 829 /* Boot FALCON cpu */ 830 CSB_WR4(sc, XUSB_FALCON_BOOTVEC, fw_hdr->boot_codetag); 831 CSB_WR4(sc, XUSB_FALCON_CPUCTL, CPUCTL_STARTCPU); 832 833 /* Wait for CPU */ 834 for (i = 50; i > 0; i--) { 835 if (CSB_RD4(sc, XUSB_FALCON_CPUCTL) == CPUCTL_STOPPED) 836 break; 837 DELAY(100); 838 } 839 if (i <= 0) { 840 device_printf(sc->dev, "Timedout while wating for FALCON cpu, " 841 "state: 0x%08X\n", CSB_RD4(sc, XUSB_FALCON_CPUCTL)); 842 return (ETIMEDOUT); 843 } 844 845 fw_timespec.tv_sec = fw_hdr->fwimg_created_time; 846 fw_timespec.tv_nsec = 0; 847 clock_ts_to_ct(&fw_timespec, &fw_clock); 848 device_printf(sc->dev, 849 " Falcon firmware version: %02X.%02X.%04X," 850 " (%d/%d/%d %d:%02d:%02d UTC)\n", 851 (fw_hdr->version_id >> 24) & 0xFF,(fw_hdr->version_id >> 15) & 0xFF, 852 fw_hdr->version_id & 0xFFFF, 853 fw_clock.day, fw_clock.mon, fw_clock.year, 854 fw_clock.hour, fw_clock.min, fw_clock.sec); 855 856 return (0); 857 } 858 859 static int 860 init_hw(struct tegra_xhci_softc *sc) 861 { 862 int rv; 863 uint32_t reg; 864 rman_res_t base_addr; 865 866 base_addr = rman_get_start(sc->xhci_softc.sc_io_res); 867 868 /* Enable FPCI access */ 869 reg = IPFS_RD4(sc, XUSB_HOST_CONFIGURATION); 870 reg |= CONFIGURATION_EN_FPCI; 871 IPFS_WR4(sc, XUSB_HOST_CONFIGURATION, reg); 872 IPFS_RD4(sc, XUSB_HOST_CONFIGURATION); 873 874 /* Program bar for XHCI base address */ 875 reg = FPCI_RD4(sc, T_XUSB_CFG_4); 876 reg &= ~CFG_4_BASE_ADDRESS(~0); 877 reg |= CFG_4_BASE_ADDRESS((uint32_t)base_addr >> 15); 878 FPCI_WR4(sc, T_XUSB_CFG_4, reg); 879 FPCI_WR4(sc, T_XUSB_CFG_5, (uint32_t)((uint64_t)(base_addr) >> 32)); 880 881 /* Enable bus master */ 882 reg = FPCI_RD4(sc, T_XUSB_CFG_1); 883 reg |= CFG_1_IO_SPACE; 884 reg |= CFG_1_MEMORY_SPACE; 885 reg |= CFG_1_BUS_MASTER; 886 FPCI_WR4(sc, T_XUSB_CFG_1, reg); 887 888 /* Enable Interrupts */ 889 reg = IPFS_RD4(sc, XUSB_HOST_INTR_MASK); 890 reg |= INTR_IP_INT_MASK; 891 IPFS_WR4(sc, XUSB_HOST_INTR_MASK, reg); 892 893 /* Set hysteresis */ 894 IPFS_WR4(sc, XUSB_HOST_CLKGATE_HYSTERESIS, 128); 895 896 rv = load_fw(sc); 897 if (rv != 0) 898 return rv; 899 return (0); 900 } 901 902 static int 903 tegra_xhci_probe(device_t dev) 904 { 905 906 if (!ofw_bus_status_okay(dev)) 907 return (ENXIO); 908 909 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 910 device_set_desc(dev, "Nvidia Tegra XHCI controller"); 911 return (BUS_PROBE_DEFAULT); 912 } 913 return (ENXIO); 914 } 915 916 static int 917 tegra_xhci_detach(device_t dev) 918 { 919 struct tegra_xhci_softc *sc; 920 struct xhci_softc *xsc; 921 922 sc = device_get_softc(dev); 923 xsc = &sc->xhci_softc; 924 925 /* during module unload there are lots of children leftover */ 926 device_delete_children(dev); 927 if (sc->xhci_inited) { 928 usb_callout_drain(&xsc->sc_callout); 929 xhci_halt_controller(xsc); 930 } 931 932 if (xsc->sc_irq_res && xsc->sc_intr_hdl) { 933 bus_teardown_intr(dev, xsc->sc_irq_res, xsc->sc_intr_hdl); 934 xsc->sc_intr_hdl = NULL; 935 } 936 if (xsc->sc_irq_res) { 937 bus_release_resource(dev, SYS_RES_IRQ, 938 rman_get_rid(xsc->sc_irq_res), xsc->sc_irq_res); 939 xsc->sc_irq_res = NULL; 940 } 941 if (xsc->sc_io_res != NULL) { 942 bus_release_resource(dev, SYS_RES_MEMORY, 943 rman_get_rid(xsc->sc_io_res), xsc->sc_io_res); 944 xsc->sc_io_res = NULL; 945 } 946 if (sc->xhci_inited) 947 xhci_uninit(xsc); 948 if (sc->irq_hdl_mbox != NULL) 949 bus_teardown_intr(dev, sc->irq_res_mbox, sc->irq_hdl_mbox); 950 if (sc->fw_vaddr != 0) 951 kmem_free(sc->fw_vaddr, sc->fw_size); 952 LOCK_DESTROY(sc); 953 return (0); 954 } 955 956 static int 957 tegra_xhci_attach(device_t dev) 958 { 959 struct tegra_xhci_softc *sc; 960 struct xhci_softc *xsc; 961 int rv, rid; 962 phandle_t node; 963 964 sc = device_get_softc(dev); 965 sc->dev = dev; 966 sc->soc = (struct xhci_soc *)ofw_bus_search_compatible(dev, 967 compat_data)->ocd_data; 968 node = ofw_bus_get_node(dev); 969 xsc = &sc->xhci_softc; 970 LOCK_INIT(sc); 971 972 rv = get_fdt_resources(sc, node); 973 if (rv != 0) { 974 rv = ENXIO; 975 goto error; 976 } 977 rv = enable_fdt_resources(sc); 978 if (rv != 0) { 979 rv = ENXIO; 980 goto error; 981 } 982 983 /* Allocate resources. */ 984 rid = 0; 985 xsc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 986 RF_ACTIVE); 987 if (xsc->sc_io_res == NULL) { 988 device_printf(dev, 989 "Could not allocate HCD memory resources\n"); 990 rv = ENXIO; 991 goto error; 992 } 993 rid = 1; 994 sc->mem_res_fpci = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 995 RF_ACTIVE); 996 if (sc->mem_res_fpci == NULL) { 997 device_printf(dev, 998 "Could not allocate FPCI memory resources\n"); 999 rv = ENXIO; 1000 goto error; 1001 } 1002 rid = 2; 1003 sc->mem_res_ipfs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1004 RF_ACTIVE); 1005 if (sc->mem_res_ipfs == NULL) { 1006 device_printf(dev, 1007 "Could not allocate IPFS memory resources\n"); 1008 rv = ENXIO; 1009 goto error; 1010 } 1011 1012 rid = 0; 1013 xsc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1014 RF_ACTIVE); 1015 if (xsc->sc_irq_res == NULL) { 1016 device_printf(dev, "Could not allocate HCD IRQ resources\n"); 1017 rv = ENXIO; 1018 goto error; 1019 } 1020 rid = 1; 1021 sc->irq_res_mbox = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1022 RF_ACTIVE); 1023 if (sc->irq_res_mbox == NULL) { 1024 device_printf(dev, "Could not allocate MBOX IRQ resources\n"); 1025 rv = ENXIO; 1026 goto error; 1027 } 1028 1029 rv = init_hw(sc); 1030 if (rv != 0) { 1031 device_printf(dev, "Could not initialize XUSB hardware\n"); 1032 goto error; 1033 } 1034 1035 /* Wakeup and enable firmaware */ 1036 rv = mbox_send_cmd(sc, MBOX_CMD_MSG_ENABLED, 0); 1037 if (rv != 0) { 1038 device_printf(sc->dev, "Could not enable XUSB firmware\n"); 1039 goto error; 1040 } 1041 1042 /* Fill data for XHCI driver. */ 1043 xsc->sc_bus.parent = dev; 1044 xsc->sc_bus.devices = xsc->sc_devices; 1045 xsc->sc_bus.devices_max = XHCI_MAX_DEVICES; 1046 1047 xsc->sc_io_tag = rman_get_bustag(xsc->sc_io_res); 1048 xsc->sc_io_hdl = rman_get_bushandle(xsc->sc_io_res); 1049 xsc->sc_io_size = rman_get_size(xsc->sc_io_res); 1050 strlcpy(xsc->sc_vendor, "Nvidia", sizeof(xsc->sc_vendor)); 1051 1052 /* Add USB bus device. */ 1053 xsc->sc_bus.bdev = device_add_child(sc->dev, "usbus", -1); 1054 if (xsc->sc_bus.bdev == NULL) { 1055 device_printf(sc->dev, "Could not add USB device\n"); 1056 rv = ENXIO; 1057 goto error; 1058 } 1059 device_set_ivars(xsc->sc_bus.bdev, &xsc->sc_bus); 1060 device_set_desc(xsc->sc_bus.bdev, "Nvidia USB 3.0 controller"); 1061 1062 rv = xhci_init(xsc, sc->dev, 1); 1063 if (rv != 0) { 1064 device_printf(sc->dev, "USB init failed: %d\n", rv); 1065 goto error; 1066 } 1067 sc->xhci_inited = true; 1068 rv = xhci_start_controller(xsc); 1069 if (rv != 0) { 1070 device_printf(sc->dev, 1071 "Could not start XHCI controller: %d\n", rv); 1072 goto error; 1073 } 1074 1075 rv = bus_setup_intr(dev, sc->irq_res_mbox, INTR_TYPE_MISC | INTR_MPSAFE, 1076 NULL, intr_mbox, sc, &sc->irq_hdl_mbox); 1077 if (rv != 0) { 1078 device_printf(dev, "Could not setup error IRQ: %d\n",rv); 1079 xsc->sc_intr_hdl = NULL; 1080 goto error; 1081 } 1082 1083 rv = bus_setup_intr(dev, xsc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1084 NULL, (driver_intr_t *)xhci_interrupt, xsc, &xsc->sc_intr_hdl); 1085 if (rv != 0) { 1086 device_printf(dev, "Could not setup error IRQ: %d\n",rv); 1087 xsc->sc_intr_hdl = NULL; 1088 goto error; 1089 } 1090 1091 /* Probe the bus. */ 1092 rv = device_probe_and_attach(xsc->sc_bus.bdev); 1093 if (rv != 0) { 1094 device_printf(sc->dev, "Could not initialize USB: %d\n", rv); 1095 goto error; 1096 } 1097 1098 return (0); 1099 1100 error: 1101 panic("XXXXX"); 1102 tegra_xhci_detach(dev); 1103 return (rv); 1104 } 1105 1106 static device_method_t xhci_methods[] = { 1107 /* Device interface */ 1108 DEVMETHOD(device_probe, tegra_xhci_probe), 1109 DEVMETHOD(device_attach, tegra_xhci_attach), 1110 DEVMETHOD(device_detach, tegra_xhci_detach), 1111 DEVMETHOD(device_suspend, bus_generic_suspend), 1112 DEVMETHOD(device_resume, bus_generic_resume), 1113 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1114 1115 /* Bus interface */ 1116 DEVMETHOD(bus_print_child, bus_generic_print_child), 1117 1118 DEVMETHOD_END 1119 }; 1120 1121 static devclass_t xhci_devclass; 1122 static DEFINE_CLASS_0(xhci, xhci_driver, xhci_methods, 1123 sizeof(struct tegra_xhci_softc)); 1124 DRIVER_MODULE(tegra_xhci, simplebus, xhci_driver, xhci_devclass, NULL, NULL); 1125 MODULE_DEPEND(tegra_xhci, usb, 1, 1, 1);
Cache object: 9d1d447fa2a971f2a3c667199e8ecb52
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