The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/qualcomm/qcom_scm_legacy_defs.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  *
   27  * $FreeBSD$
   28  */
   29 
   30 #ifndef __QCOM_SCM_LEGACY_DEFS_H__
   31 #define __QCOM_SCM_LEGACY_DEFS_H__
   32 
   33 /*
   34  * These definitions are specific to the 32 bit legacy SCM interface
   35  * used by the IPQ806x and IPQ401x SoCs.
   36  */
   37 
   38 /*
   39  * Mapping of the SCM service/command fields into the a0 argument
   40  * in an SMC instruction call.
   41  *
   42  * This is particular to the legacy SCM interface, and is not the
   43  * same as the non-legacy 32/64 bit FNID mapping layout.
   44  */
   45 #define QCOM_SCM_LEGACY_SMC_FNID(s, c)          (((s) << 10) | ((c) & 0x3ff))
   46 
   47 /*
   48  * There are two kinds of SCM calls in this legacy path.
   49  *
   50  * The first kind are the normal ones - up to a defined max of arguments,
   51  * a defined max of responses and some identifiers for all of it.
   52  * They can be issues in parallel on different cores, can be interrupted,
   53  * etc.
   54  *
   55  * The second kind are what are termed "atomic" SCM calls -
   56  * up to 5 argument DWORDs, up to 3 response DWORDs, done atomically,
   57  * not interruptable/parallel.
   58  *
   59  * The former use the structures below to represent the request and response
   60  * in memory.  The latter use defines and a direct SMC call with the
   61  * arguments in registers.
   62  */
   63 
   64 struct qcom_scm_legacy_smc_args {
   65         uint32_t args[8];
   66 };
   67 
   68 /*
   69  * Atomic SCM call command/response buffer definitions.
   70  */
   71 #define QCOM_SCM_LEGACY_ATOMIC_MAX_ARGCOUNT             5
   72 #define QCOM_SCM_LEGACY_CLASS_REGISTER                  (0x2 << 8)
   73 #define QCOM_SCM_LEGACY_MASK_IRQS                       (1U << 5)
   74 
   75 /*
   76  * Mapping an SCM service/command/argcount into the a0 register
   77  * for an SMC instruction call.
   78  */
   79 #define QCOM_SCM_LEGACY_ATOMIC_ID(svc, cmd, n) \
   80             ((QCOM_SCM_LEGACY_SMC_FNID((svc), cmd) << 12) | \
   81             QCOM_SCM_LEGACY_CLASS_REGISTER | \
   82             QCOM_SCM_LEGACY_MASK_IRQS | \
   83             ((n) & 0xf))
   84 
   85 /*
   86  * Legacy command/response buffer definitions.
   87  *
   88  * The legacy path contains up to the defined maximum arguments
   89  * but only a single command/response pair per call.
   90  *
   91  * A command and response buffer is laid out in memory as such:
   92  *
   93  * | command header     |
   94  * | (buffer payload)   |
   95  * | response header    |
   96  * | (response payload) |
   97  */
   98 
   99 /*
  100  * The command header.
  101  *
  102  * len - the length of the total command and response, including
  103  *       the headers.
  104  *
  105  * buf_offset - the offset inside the buffer, starting at the
  106  *       beginning of this command header, where the command buffer
  107  *       is found.  The end is the byte before the response_header_offset.
  108  *
  109  * response_header_offset - the offset inside the buffer where
  110  *       the response header is found.
  111  *
  112  * id - the QCOM_SCM_LEGACY_SMC_FNID() - service/command ids
  113  */
  114 struct qcom_scm_legacy_command_header {
  115         uint32_t len;
  116         uint32_t buf_offset;
  117         uint32_t response_header_offset;
  118         uint32_t id;
  119 };
  120 
  121 /*
  122  * The response header.
  123  *
  124  * This is found immediately after the command header and command
  125  * buffer payload.
  126  *
  127  * len - the total amount of memory available for the response.
  128  *       Linux doesn't set this; it always passes in a response
  129  *       buffer large enough to store MAX_QCOM_SCM_RETS * DWORD
  130  *       bytes.
  131  *
  132  *       It's also possible this is set by the firmware.
  133  *
  134  * buf_offset - start of response buffer, relative to the beginning
  135  *       of the command header.  This also isn't set in Linux before
  136  *       calling the SMC instruction, but it is checked afterwards
  137  *       to assemble a pointer to the response data.  The firmware
  138  *       likely sets this.
  139  *
  140  * is_complete - true if complete.  Linux loops over DMA sync to
  141  *       check if this is complete even after the SMC call returns.
  142  */
  143 struct qcom_scm_legacy_response_header {
  144         uint32_t len;
  145         uint32_t buf_offset;
  146         uint32_t is_complete;
  147 };
  148 
  149 #endif  /* __QCOM_SCM_LEGACY_DEFS_H__ */

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