The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/s3c2xx0/s3c24x0reg.h

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    1 /* $NetBSD: s3c24x0reg.h,v 1.7 2004/02/12 03:52:46 bsh Exp $ */
    2 
    3 /*-
    4  * Copyright (c) 2003  Genetec corporation  All rights reserved.
    5  * Written by Hiroyuki Bessho for Genetec corporation.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. The name of Genetec corporation may not be used to endorse
   16  *    or promote products derived from this software without specific prior
   17  *    written permission.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORP.
   23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   29  * POSSIBILITY OF SUCH DAMAGE.
   30  *
   31  * $FreeBSD: releng/10.0/sys/arm/s3c2xx0/s3c24x0reg.h 236990 2012-06-13 04:59:00Z imp $
   32  */
   33 
   34 
   35 /*
   36  * Samsung S3C2410X/2400 processor is ARM920T based integrated CPU
   37  *
   38  * Reference:
   39  *  S3C2410X User's Manual
   40  *  S3C2400 User's Manual
   41  */
   42 #ifndef _ARM_S3C2XX0_S3C24X0REG_H_
   43 #define _ARM_S3C2XX0_S3C24X0REG_H_
   44 
   45 /* common definitions for S3C2800, S3C2410 and S3C2440 */
   46 #include <arm/s3c2xx0/s3c2xx0reg.h>
   47 
   48 /*
   49  * Map the device registers into kernel space.
   50  *
   51  * As most devices use less than 1 page of memory reduce
   52  * the distance between allocations by right shifting
   53  * S3C24X0_DEV_SHIFT bits. Because the UART takes 3*0x4000
   54  * bytes the upper limit on S3C24X0_DEV_SHIFT is 4.
   55  * TODO: Fix the UART code so we can increase this value.
   56  */
   57 #define S3C24X0_DEV_START       0x48000000
   58 #define S3C24X0_DEV_STOP        0x60000000
   59 #define S3C24X0_DEV_VA_OFFSET   0xD8000000
   60 #define S3C24X0_DEV_SHIFT       4
   61 #define S3C24X0_DEV_PA_SIZE     (S3C24X0_DEV_STOP - S3C24X0_DEV_START)
   62 #define S3C24X0_DEV_VA_SIZE     (S3C24X0_DEV_PA_SIZE >> S3C24X0_DEV_SHIFT)
   63 #define S3C24X0_DEV_PA_TO_VA(x) ((x >> S3C24X0_DEV_SHIFT) - S3C24X0_DEV_START + S3C24X0_DEV_VA_OFFSET)
   64 
   65 /*
   66  * Physical address of integrated peripherals
   67  */
   68 #define S3C24X0_MEMCTL_PA_BASE  0x48000000 /* memory controller */
   69 #define S3C24X0_MEMCTL_BASE     S3C24X0_DEV_PA_TO_VA(S3C24X0_MEMCTL_PA_BASE)
   70 #define S3C24X0_USBHC_PA_BASE   0x49000000 /* USB Host controller */
   71 #define S3C24X0_USBHC_BASE      S3C24X0_DEV_PA_TO_VA(S3C24X0_USBHC_PA_BASE)
   72 #define S3C24X0_INTCTL_PA_BASE  0x4a000000 /* Interrupt controller */
   73 #define S3C24X0_INTCTL_BASE     S3C24X0_DEV_PA_TO_VA(S3C24X0_INTCTL_PA_BASE)
   74 #define S3C24X0_INTCTL_SIZE     0x20
   75 #define S3C24X0_DMAC_PA_BASE    0x4b000000
   76 #define S3C24X0_DMAC_BASE       S3C24X0_DEV_PA_TO_VA(S3C24X0_DMAC_PA_BASE)
   77 #define S3C24X0_DMAC_SIZE       0xe4
   78 #define S3C24X0_CLKMAN_PA_BASE  0x4c000000 /* clock & power management */
   79 #define S3C24X0_CLKMAN_BASE     S3C24X0_DEV_PA_TO_VA(S3C24X0_CLKMAN_PA_BASE)
   80 #define S3C24X0_LCDC_PA_BASE    0x4d000000 /* LCD controller */
   81 #define S3C24X0_LCDC_BASE       S3C24X0_DEV_PA_TO_VA(S3C24X0_LCDC_PA_BASE)
   82 #define S3C24X0_LCDC_SIZE       0x64
   83 #define S3C24X0_NANDFC_PA_BASE  0x4e000000 /* NAND Flash controller */
   84 #define S3C24X0_NANDFC_BASE     S3C24X0_DEV_PA_TO_VA(S3C24X0_NANDFC_PA_BASE)
   85 #define S3C24X0_UART0_PA_BASE   0x50000000
   86 #define S3C24X0_UART0_BASE      S3C24X0_DEV_PA_TO_VA(S3C24X0_UART0_PA_BASE)
   87 #define S3C24X0_UART_PA_BASE(n) (S3C24X0_UART0_PA_BASE+0x4000*(n))
   88 #define S3C24X0_UART_BASE(n)    (S3C24X0_UART0_BASE+0x4000*(n))
   89 #define S3C24X0_TIMER_PA_BASE   0x51000000
   90 #define S3C24X0_TIMER_BASE      S3C24X0_DEV_PA_TO_VA(S3C24X0_TIMER_PA_BASE)
   91 #define S3C24X0_USBDC_PA_BASE   0x5200140
   92 #define S3C24X0_USBDC_BASE      S3C24X0_DEV_PA_TO_VA(S3C24X0_USBDC_PA_BASE)
   93 #define S3C24X0_USBDC_SIZE      0x130
   94 #define S3C24X0_WDT_PA_BASE     0x53000000
   95 #define S3C24X0_WDT_BASE        S3C24X0_DEV_PA_TO_VA(S3C24X0_WDT_PA_BASE)
   96 #define S3C24X0_IIC_PA_BASE     0x54000000
   97 #define S3C24X0_IIC_BASE        S3C24X0_DEV_PA_TO_VA(S3C24X0_IIC_PA_BASE)
   98 #define S3C24X0_IIS_PA_BASE     0x55000000
   99 #define S3C24X0_IIS_BASE        S3C24X0_DEV_PA_TO_VA(S3C24X0_IIS_PA_BASE)
  100 #define S3C24X0_GPIO_PA_BASE    0x56000000
  101 #define S3C24X0_GPIO_BASE       S3C24X0_DEV_PA_TO_VA(S3C24X0_GPIO_PA_BASE)
  102 #define S3C24X0_RTC_PA_BASE     0x57000000
  103 #define S3C24X0_RTC_BASE        S3C24X0_DEV_PA_TO_VA(S3C24X0_RTC_PA_BASE)
  104 #define S3C24X0_RTC_SIZE        0x8C
  105 #define S3C24X0_ADC_PA_BASE     0x58000000
  106 #define S3C24X0_ADC_BASE        S3C24X0_DEV_PA_TO_VA(S3C24X0_ADC_PA_BASE)
  107 #define S3C24X0_SPI0_PA_BASE    0x59000000
  108 #define S3C24X0_SPI0_BASE       S3C24X0_DEV_PA_TO_VA(S3C24X0_SPI0_PA_BASE)
  109 #define S3C24X0_SPI1_PA_BASE    0x59000020
  110 #define S3C24X0_SPI1_BASE       S3C24X0_DEV_PA_TO_VA(S3C24X0_SPI1_PA_BASE)
  111 #define S3C24X0_SDI_PA_BASE     0x5a000000 /* SD Interface */
  112 #define S3C24X0_SDI_BASE        S3C24X0_DEV_PA_TO_VA(S3C24X0_SDI_PA_BASE)
  113 
  114 #define S3C24X0_REG_BASE        0x48000000
  115 #define S3C24X0_REG_SIZE        0x13000000
  116 
  117 /* Memory controller */
  118 #define MEMCTL_BWSCON           0x00    /* Bus width and wait status */
  119 #define  BWSCON_DW0_SHIFT       1       /* bank0 is odd */
  120 #define  BWSCON_BANK_SHIFT(n)   (4*(n)) /* for bank 1..7 */
  121 #define  BWSCON_DW_MASK         0x03
  122 #define  BWSCON_DW_8            0
  123 #define  BWSCON_DW_16           1
  124 #define  BWSCON_DW_32           2
  125 #define  BWSCON_WS              0x04    /* WAIT enable for the bank */
  126 #define  BWSCON_ST              0x08    /* SRAM use UB/LB for the bank */
  127 
  128 #define MEMCTL_BANKCON0         0x04    /* Boot ROM control */
  129 #define MEMCTL_BANKCON(n)       (0x04+4*(n)) /* BANKn control */
  130 #define  BANKCON_MT_SHIFT       15
  131 #define  BANKCON_MT_ROM         (0<<BANKCON_MT_SHIFT)
  132 #define  BANKCON_MT_DRAM        (3<<BANKCON_MT_SHIFT)
  133 #define  BANKCON_TACS_SHIFT     13      /* address set-up time to nGCS */
  134 #define  BANKCON_TCOS_SHIFT     11      /* CS set-up to nOE */
  135 #define  BANKCON_TACC_SHIFT     8       /* CS set-up to nOE */
  136 #define  BANKCON_TOCH_SHIFT     6       /* CS hold time from OE */
  137 #define  BANKCON_TCAH_SHIFT     4       /* address hold time from OE */
  138 #define  BANKCON_TACP_SHIFT     2       /* page mode access cycle */
  139 #define  BANKCON_TACP_2         (0<<BANKCON_TACP_SHIFT)
  140 #define  BANKCON_TACP_3         (1<<BANKCON_TACP_SHIFT)
  141 #define  BANKCON_TACP_4         (2<<BANKCON_TACP_SHIFT)
  142 #define  BANKCON_TACP_6         (3<<BANKCON_TACP_SHIFT)
  143 #define  BANKCON_PMC_4          (1<<0)
  144 #define  BANKCON_PMC_8          (2<<0)
  145 #define  BANKCON_PMC_16         (3<<0)
  146 #define  BANKCON_TRCD_SHIFT     2       /* RAS to CAS delay */
  147 #define  BANKCON_TRCD_2         (0<<2)
  148 #define  BANKCON_TRCD_3         (1<<2)
  149 #define  BANKCON_TRCD_4         (2<<2)
  150 #define  BANKCON_SCAN_8         (0<<0)  /* Column address number */
  151 #define  BANKCON_SCAN_9         (1<<0)
  152 #define  BANKCON_SCAN_10        (2<<0)
  153 #define MEMCTL_REFRESH          0x24    /* DRAM?SDRAM Refresh */
  154 #define  REFRESH_REFEN          (1<<23)
  155 #define  REFRESH_TREFMD         (1<<22) /* 1=self refresh */
  156 #define  REFRESH_TRP_2          (0<<20)
  157 #define  REFRESH_TRP_3          (1<<20)
  158 #define  REFRESH_TRP_4          (2<<20)
  159 #define  REFRESH_TRC_4          (0<<18)
  160 #define  REFRESH_TRC_5          (1<<18)
  161 #define  REFRESH_TRC_6          (2<<18)
  162 #define  REFRESH_TRC_7          (3<<18)
  163 #define  REFRESH_COUNTER_MASK   0x3ff
  164 #define MEMCTL_BANKSIZE         0x28    /* Flexible Bank size */
  165 #define MEMCTL_MRSRB6           0x2c    /* SDRAM Mode register */
  166 #define MEMCTL_MRSRB7           0x30
  167 #define  MRSR_CL_SHIFT          4       /* CAS Latency */
  168 
  169 #define S3C24X0_MEMCTL_SIZE     0x34
  170 
  171 /* USB Host controller */
  172 #define S3C24X0_USBHC_SIZE      0x5c
  173 
  174 /* Interrupt controller */
  175 #define INTCTL_PRIORITY         0x0c    /* IRQ Priority control */
  176 #define INTCTL_INTPND           0x10    /* Interrupt request status */
  177 #define INTCTL_INTOFFSET        0x14    /* Interrupt request source */
  178 #define INTCTL_SUBSRCPND        0x18    /* sub source pending */
  179 #define INTCTL_INTSUBMSK        0x1c    /* sub mask */
  180 
  181 /* Interrupt source */
  182 #define S3C24X0_INT_ADCTC       31      /* ADC (and TC for 2410) */
  183 #define S3C24X0_INT_RTC         30      /* RTC alarm */
  184 #define S3C24X0_INT_SPI1        29      /* SPI 1 */
  185 #define S3C24X0_INT_UART0       28      /* UART0 */
  186 #define S3C24X0_INT_IIC         27
  187 #define S3C24X0_INT_USBH        26      /* USB Host */
  188 #define S3C24X0_INT_USBD        25      /* USB Device */
  189 #define S3C24X0_INT_UART1       23      /* UART0  (2410 only) */
  190 #define S3C24X0_INT_SPI0        22      /* SPI 0 */
  191 #define S3C24X0_INT_SDI         21
  192 #define S3C24X0_INT_DMA3        20
  193 #define S3C24X0_INT_DMA2        19
  194 #define S3C24X0_INT_DMA1        18
  195 #define S3C24X0_INT_DMA0        17
  196 #define S3C24X0_INT_LCD         16
  197 
  198 #define S3C24X0_INT_UART2       15      /* UART2 int (2410) */
  199 #define S3C24X0_INT_TIMER4      14
  200 #define S3C24X0_INT_TIMER3      13
  201 #define S3C24X0_INT_TIMER2      12
  202 #define S3C24X0_INT_TIMER1      11
  203 #define S3C24X0_INT_TIMER0      10
  204 #define S3C24X0_INT_TIMER(n)    (10+(n)) /* timer interrupt [4:0] */
  205 #define S3C24X0_INT_WDT         9       /* Watch dog timer */
  206 #define S3C24X0_INT_TICK        8
  207 #define S3C24X0_INT_BFLT        7       /* Battery fault */
  208 #define S3C24X0_INT_8_23        5       /* Ext int 8..23 */
  209 #define S3C24X0_INT_4_7         4       /* Ext int 4..7 */
  210 #define S3C24X0_INT_3           3
  211 #define S3C24X0_INT_2           2
  212 #define S3C24X0_INT_1           1
  213 #define S3C24X0_INT_0           0
  214 
  215 /* 24{1,4}0 has more than 32 interrupt sources.  These are sub-sources
  216  * that are OR-ed into main interrupt sources, and controlled via
  217  * SUBSRCPND and  SUBSRCMSK registers */
  218 #define S3C24X0_SUBIRQ_MIN      32
  219 
  220 /* cascaded to INT_ADCTC */
  221 #define S3C24X0_INT_ADC         (S3C24X0_SUBIRQ_MIN+10) /* AD converter */
  222 #define S3C24X0_INT_TC          (S3C24X0_SUBIRQ_MIN+9)  /* Touch screen */
  223 /* cascaded to INT_UART2 */
  224 #define S3C24X0_INT_ERR2        (S3C24X0_SUBIRQ_MIN+8)  /* UART2 Error */
  225 #define S3C24X0_INT_TXD2        (S3C24X0_SUBIRQ_MIN+7)  /* UART2 Tx */
  226 #define S3C24X0_INT_RXD2        (S3C24X0_SUBIRQ_MIN+6)  /* UART2 Rx */
  227 /* cascaded to INT_UART1 */
  228 #define S3C24X0_INT_ERR1        (S3C24X0_SUBIRQ_MIN+5)  /* UART1 Error */
  229 #define S3C24X0_INT_TXD1        (S3C24X0_SUBIRQ_MIN+4)  /* UART1 Tx */
  230 #define S3C24X0_INT_RXD1        (S3C24X0_SUBIRQ_MIN+3)  /* UART1 Rx */
  231 /* cascaded to INT_UART0 */
  232 #define S3C24X0_INT_ERR0        (S3C24X0_SUBIRQ_MIN+2)  /* UART0 Error */
  233 #define S3C24X0_INT_TXD0        (S3C24X0_SUBIRQ_MIN+1)  /* UART0 Tx */
  234 #define S3C24X0_INT_RXD0        (S3C24X0_SUBIRQ_MIN+0)  /* UART0 Rx */
  235 
  236 /*
  237  * Support for external interrupts. We use values from 48
  238  * to allow new CPU's to allocate new subirq's.
  239  */
  240 #define S3C24X0_EXTIRQ_MIN      48
  241 #define S3C24X0_EXTIRQ_COUNT    24
  242 #define S3C24X0_EXTIRQ_MAX      (S3C24X0_EXTIRQ_MIN + S3C24X0_EXTIRQ_COUNT - 1)
  243 #define S3C24X0_INT_EXT(n)      (S3C24X0_EXTIRQ_MIN + (n))
  244 
  245 /* DMA controller */
  246 /* XXX */
  247 
  248 /* Clock & power manager */
  249 #define CLKMAN_LOCKTIME 0x00    /* PLL lock time */
  250 #define CLKMAN_MPLLCON  0x04    /* MPLL control */
  251 #define CLKMAN_UPLLCON  0x08    /* UPLL control */
  252 #define  PLLCON_MDIV_SHIFT      12
  253 #define  PLLCON_MDIV_MASK       (0xff<<PLLCON_MDIV_SHIFT)
  254 #define  PLLCON_PDIV_SHIFT      4
  255 #define  PLLCON_PDIV_MASK       (0x3f<<PLLCON_PDIV_SHIFT)
  256 #define  PLLCON_SDIV_SHIFT      0
  257 #define  PLLCON_SDIV_MASK       (0x03<<PLLCON_SDIV_SHIFT)
  258 #define CLKMAN_CLKCON   0x0c
  259 #define  CLKCON_SPI     (1<<18)
  260 #define  CLKCON_IIS     (1<<17)
  261 #define  CLKCON_IIC     (1<<16)
  262 #define  CLKCON_ADC     (1<<15)
  263 #define  CLKCON_RTC     (1<<14)
  264 #define  CLKCON_GPIO    (1<<13)
  265 #define  CLKCON_UART2   (1<<12)
  266 #define  CLKCON_UART1   (1<<11)
  267 #define  CLKCON_UART0   (1<<10) /* PCLK to UART0 */
  268 #define  CLKCON_SDI     (1<<9)
  269 #define  CLKCON_TIMER   (1<<8)  /* PCLK to TIMER */
  270 #define  CLKCON_USBD    (1<<7)  /* PCLK to USB device controller */
  271 #define  CLKCON_USBH    (1<<6)  /* PCLK to USB host controller */
  272 #define  CLKCON_LCDC    (1<<5)  /* PCLK to LCD controller */
  273 #define  CLKCON_NANDFC  (1<<4)  /* PCLK to NAND Flash controller */
  274 #define  CLKCON_IDLE    (1<<2)  /* 1=transition to IDLE mode */
  275 #define CLKMAN_CLKSLOW  0x10
  276 #define CLKMAN_CLKDIVN  0x14
  277 #define  CLKDIVN_PDIVN  (1<<0)  /* pclk=hclk/2 */
  278 
  279 #define CLKMAN_CLKSLOW  0x10    /* slow clock controll */
  280 #define  CLKSLOW_UCLK   (1<<7)  /* 1=UPLL off */
  281 #define  CLKSLOW_MPLL   (1<<5)  /* 1=PLL off */
  282 #define  CLKSLOW_SLOW   (1<<4)  /* 1: Enable SLOW mode */
  283 #define  CLKSLOW_VAL_MASK  0x0f /* divider value for slow clock */
  284 
  285 #define CLKMAN_CLKDIVN  0x14    /* Software reset control */
  286 #define  CLKDIVN_PDIVN  (1<<0)
  287 
  288 #define S3C24X0_CLKMAN_SIZE     0x18
  289 
  290 /* LCD controller */
  291 #define LCDC_LCDCON1    0x00    /* control 1 */
  292 #define  LCDCON1_ENVID          (1<<0)  /* enable video */
  293 #define  LCDCON1_BPPMODE_SHIFT  1
  294 #define  LCDCON1_BPPMODE_MASK   (0x0f<<LCDCON1_BPPMODE_SHIFT)
  295 #define  LCDCON1_BPPMODE_STN1   (0x0<<LCDCON1_BPPMODE_SHIFT)
  296 #define  LCDCON1_BPPMODE_STN2   (0x1<<LCDCON1_BPPMODE_SHIFT)
  297 #define  LCDCON1_BPPMODE_STN4   (0x2<<LCDCON1_BPPMODE_SHIFT)
  298 #define  LCDCON1_BPPMODE_STN8   (0x3<<LCDCON1_BPPMODE_SHIFT)
  299 #define  LCDCON1_BPPMODE_STN12  (0x4<<LCDCON1_BPPMODE_SHIFT)
  300 #define  LCDCON1_BPPMODE_TFT1   (0x8<<LCDCON1_BPPMODE_SHIFT)
  301 #define  LCDCON1_BPPMODE_TFT2   (0x9<<LCDCON1_BPPMODE_SHIFT)
  302 #define  LCDCON1_BPPMODE_TFT4   (0xa<<LCDCON1_BPPMODE_SHIFT)
  303 #define  LCDCON1_BPPMODE_TFT8   (0xb<<LCDCON1_BPPMODE_SHIFT)
  304 #define  LCDCON1_BPPMODE_TFT16  (0xc<<LCDCON1_BPPMODE_SHIFT)
  305 #define  LCDCON1_BPPMODE_TFT24  (0xd<<LCDCON1_BPPMODE_SHIFT)
  306 #define  LCDCON1_BPPMODE_TFTX   (0x8<<LCDCON1_BPPMODE_SHIFT)
  307 
  308 #define  LCDCON1_PNRMODE_SHIFT  5
  309 #define  LCDCON1_PNRMODE_MASK   (0x3<<LCDCON1_PNRMODE_SHIFT)
  310 #define  LCDCON1_PNRMODE_DUALSTN4    (0x0<<LCDCON1_PNRMODE_SHIFT)
  311 #define  LCDCON1_PNRMODE_SINGLESTN4  (0x1<<LCDCON1_PNRMODE_SHIFT)
  312 #define  LCDCON1_PNRMODE_SINGLESTN8  (0x2<<LCDCON1_PNRMODE_SHIFT)
  313 #define  LCDCON1_PNRMODE_TFT         (0x3<<LCDCON1_PNRMODE_SHIFT)
  314 
  315 #define  LCDCON1_MMODE          (1<<7) /* VM toggle rate */
  316 #define  LCDCON1_CLKVAL_SHIFT   8
  317 #define  LCDCON1_CLKVAL_MASK    (0x3ff<<LCDCON1_CLKVAL_SHIFT)
  318 #define  LCDCON1_LINCNT_SHIFT   18
  319 #define  LCDCON1_LINCNT_MASK    (0x3ff<<LCDCON1_LINCNT_SHIFT)
  320 
  321 #define LCDC_LCDCON2    0x04    /* control 2 */
  322 #define  LCDCON2_VPSW_SHIFT     0       /* TFT Vsync pulse width */
  323 #define  LCDCON2_VPSW_MASK      (0x3f<<LCDCON2_VPSW_SHIFT)
  324 #define  LCDCON2_VFPD_SHIFT     6       /* TFT V front porch */
  325 #define  LCDCON2_VFPD_MASK      (0xff<<LCDCON2_VFPD_SHIFT)
  326 #define  LCDCON2_LINEVAL_SHIFT  14      /* Vertical size */
  327 #define  LCDCON2_LINEVAL_MASK   (0x3ff<<LCDCON2_LINEVAL_SHIFT)
  328 #define  LCDCON2_VBPD_SHIFT     24      /* TFT V back porch */
  329 #define  LCDCON2_VBPD_MASK      (0xff<<LCDCON2_VBPD_SHIFT)
  330 
  331 #define LCDC_LCDCON3    0x08    /* control 2 */
  332 #define  LCDCON3_HFPD_SHIFT     0       /* TFT H front porch */
  333 #define  LCDCON3_HFPD_MASK      (0xff<<LCDCON3_VPFD_SHIFT)
  334 #define  LCDCON3_LINEBLANK_SHIFT  0     /* STN H blank time */
  335 #define  LCDCON3_LINEBLANK_MASK   (0xff<<LCDCON3_LINEBLANK_SHIFT)
  336 #define  LCDCON3_HOZVAL_SHIFT   8       /* Horizontal size */
  337 #define  LCDCON3_HOZVAL_MASK    (0x7ff<<LCDCON3_HOZVAL_SHIFT)
  338 #define  LCDCON3_HBPD_SHIFT     19      /* TFT H back porch */
  339 #define  LCDCON3_HBPD_MASK      (0x7f<<LCDCON3_HPBD_SHIFT)
  340 #define  LCDCON3_WDLY_SHIFT     19      /* STN vline delay */
  341 #define  LCDCON3_WDLY_MASK      (0x03<<LCDCON3_WDLY_SHIFT)
  342 #define  LCDCON3_WDLY_16        (0x00<<LCDCON3_WDLY_SHIFT)
  343 #define  LCDCON3_WDLY_32        (0x01<<LCDCON3_WDLY_SHIFT)
  344 #define  LCDCON3_WDLY_64        (0x02<<LCDCON3_WDLY_SHIFT)
  345 #define  LCDCON3_WDLY_128       (0x03<<LCDCON3_WDLY_SHIFT)
  346 
  347 #define LCDC_LCDCON4    0x0c    /* control 4 */
  348 #define  LCDCON4_HPSW_SHIFT     0       /* TFT Hsync pulse width */
  349 #define  LCDCON4_HPSW_MASK      (0xff<<LCDCON4_HPSW_SHIFT)
  350 #define  LCDCON4_WLH_SHIFT      0       /* STN VLINE high width */
  351 #define  LCDCON4_WLH_MASK       (0x03<<LCDCON4_WLH_SHIFT)
  352 #define  LCDCON4_WLH_16         (0x00<<LCDCON4_WLH_SHIFT)
  353 #define  LCDCON4_WLH_32         (0x01<<LCDCON4_WLH_SHIFT)
  354 #define  LCDCON4_WLH_64         (0x02<<LCDCON4_WLH_SHIFT)
  355 #define  LCDCON4_WLH_128        (0x03<<LCDCON4_WLH_SHIFT)
  356 
  357 #define  LCDCON4_MVAL_SHIFT     8       /* STN VM toggle rate */
  358 #define  LCDCON4_MVAL_MASK      (0xff<<LCDCON4_MVAL_SHIFT)
  359 
  360 #define LCDC_LCDCON5    0x10    /* control 5 */
  361 #define  LCDCON5_HWSWP          (1<<0)  /* half-word swap */
  362 #define  LCDCON5_BSWP           (1<<1)  /* byte swap */
  363 #define  LCDCON5_ENLEND         (1<<2)  /* TFT: enable LEND signal */
  364 #define  LCDCON5_PWREN          (1<<3)  /* enable PWREN signale */
  365 #define  LCDCON5_INVLEND        (1<<4)  /* TFT: LEND signal polarity */
  366 #define  LCDCON5_INVPWREN       (1<<5)  /* PWREN signal polarity */
  367 #define  LCDCON5_INVVDEN        (1<<6)  /* VDEN signal polarity */
  368 #define  LCDCON5_INVVD          (1<<7)  /* video data signal polarity */
  369 #define  LCDCON5_INVVFRAME      (1<<8)  /* VFRAME/VSYNC signal polarity */
  370 #define  LCDCON5_INVVLINE       (1<<9)  /* VLINE/HSYNC signal polarity */
  371 #define  LCDCON5_INVVCLK        (1<<10) /* VCLK signal polarity */
  372 #define  LCDCON5_INVVCLK_RISING LCDCON5_INVVCLK
  373 #define  LCDCON5_INVVCLK_FALLING  0
  374 #define  LCDCON5_FRM565         (1<<11) /* RGB:565 format*/
  375 #define  LCDCON5_FRM555I        0       /* RGBI:5551 format */
  376 #define  LCDCON5_BPP24BL        (1<<12) /* bit order for bpp24 */
  377 
  378 #define  LCDCON5_HSTATUS_SHIFT  17 /* TFT: horizontal status */
  379 #define  LCDCON5_HSTATUS_MASK   (0x03<<LCDCON5_HSTATUS_SHIFT)
  380 #define  LCDCON5_HSTATUS_HSYNC  (0x00<<LCDCON5_HSTATUS_SHIFT)
  381 #define  LCDCON5_HSTATUS_BACKP  (0x01<<LCDCON5_HSTATUS_SHIFT)
  382 #define  LCDCON5_HSTATUS_ACTIVE (0x02<<LCDCON5_HSTATUS_SHIFT)
  383 #define  LCDCON5_HSTATUS_FRONTP (0x03<<LCDCON5_HSTATUS_SHIFT)
  384 
  385 #define  LCDCON5_VSTATUS_SHIFT  19 /* TFT: vertical status */
  386 #define  LCDCON5_VSTATUS_MASK   (0x03<<LCDCON5_VSTATUS_SHIFT)
  387 #define  LCDCON5_VSTATUS_HSYNC  (0x00<<LCDCON5_VSTATUS_SHIFT)
  388 #define  LCDCON5_VSTATUS_BACKP  (0x01<<LCDCON5_VSTATUS_SHIFT)
  389 #define  LCDCON5_VSTATUS_ACTIVE (0x02<<LCDCON5_VSTATUS_SHIFT)
  390 #define  LCDCON5_VSTATUS_FRONTP (0x03<<LCDCON5_VSTATUS_SHIFT)
  391 
  392 #define LCDC_LCDSADDR1  0x14    /* frame buffer start address */
  393 #define LCDC_LCDSADDR2  0x18
  394 #define LCDC_LCDSADDR3  0x1c
  395 #define  LCDSADDR3_OFFSIZE_SHIFT     11
  396 #define  LCDSADDR3_PAGEWIDTH_SHIFT   0
  397 
  398 #define LCDC_REDLUT     0x20    /* STN: red lookup table */
  399 #define LCDC_GREENLUT   0x24    /* STN: green lookup table */
  400 #define LCDC_BLUELUT    0x28    /* STN: blue lookup table */
  401 #define LCDC_DITHMODE   0x4c    /* STN: dithering mode */
  402 
  403 #define LCDC_TPAL       0x50    /* TFT: temporary palette */
  404 #define  TPAL_TPALEN            (1<<24)
  405 #define  TPAL_RED_SHIFT         16
  406 #define  TPAL_GREEN_SHIFT       8
  407 #define  TPAL_BLUE_SHIFT        0
  408 
  409 #define LCDC_LCDINTPND  0x54
  410 #define LCDC_LCDSRCPND  0x58
  411 #define LCDC_LCDINTMSK  0x5c
  412 #define  LCDINT_FICNT   (1<<0)  /* FIFO trigger interrupt pending */
  413 #define  LCDINT_FRSYN   (1<<1)  /* frame sync interrupt pending */
  414 #define  LCDINT_FIWSEL  (1<<2)  /* FIFO trigger level: 1=8 words, 0=4 words*/
  415 
  416 #define LCDC_LPCSEL     0x60    /* LPC3600 mode  */
  417 #define  LPCSEL_LPC_EN          (1<<0)  /* enable LPC3600 mode */
  418 #define  LPCSEL_RES_SEL         (1<<1)  /* 1=240x320 0=320x240 */
  419 #define  LPCSEL_MODE_SEL        (1<<2)
  420 #define  LPCSEL_CPV_SEL         (1<<3)
  421 
  422 
  423 #define LCDC_PALETTE            0x0400
  424 #define LCDC_PALETTE_SIZE       0x0400
  425 
  426 /* NAND Flash controller */
  427 #define NANDFC_NFCONF   0x00    /* Configuration */
  428 /* NANDFC_NFSTAT */
  429 #define  NFSTAT_READY   (1<<0)  /* NAND flash memory ready/busy status */
  430 
  431 
  432 /* MMC/SD */
  433 #define SDI_CON         0x00
  434 #define  CON_BYTEORDER          (1<<4)
  435 #define  CON_SDIO_INTR          (1<<3)
  436 #define  CON_READWAIT_EN        (1<<2)
  437 #define  CON_CLOCK_EN           (1<<0)
  438 #define SDI_PRE         0x04
  439 #define SDI_CARG        0x08
  440 #define SDI_CCON        0x0c
  441 #define  CCON_ABORDCMD          (1<<12) /* Abort SDIO CMD12/52 */
  442 #define  CCON_WITHDATA          (1<<11) /* CMD with data */
  443 #define  CCON_LONGRSP           (1<<10) /* 136 bit response */
  444 #define  CCON_WAITRSP           (1<<9)  /* Host waits for response */
  445 #define  CCON_CMD_START         (1<<8)
  446 #define  CCON_CMDINDEX_MASK     (0x7F) /* Command number index */
  447 #define SDI_CSTA        0x10
  448 #define  CSTA_RSPCRCFAIL        (1<<12)
  449 #define  CSTA_CMDSENT           (1<<11)
  450 #define  CSTA_CMDTOUT           (1<<10)
  451 #define  CSTA_RSPFIN            (1<<9)
  452 /* All the bits to be cleared */
  453 #define  CSTA_ALL_CLEAR         (CSTA_RSPCRCFAIL | CSTA_CMDSENT | \
  454                                  CSTA_CMDTOUT | CSTA_RSPFIN)
  455 #define  CSTA_ERROR             (CSTA_RSPCRCFAIL | CSTA_CMDTOUT)
  456 #define  CSTA_CMDON             (1<<8)
  457 #define SDI_RSP0        0x14
  458 #define SDI_RSP1        0x18
  459 #define SDI_RSP2        0x1c
  460 #define SDI_RSP3        0x20
  461 #define SDI_DTIMER      0x24
  462 #define SDI_BSIZE       0x28
  463 #define SDI_DCON        0x2c
  464 #define  DCON_PRDTYPE           (1<<21)
  465 #define  DCON_TARSP             (1<<20) /* Transmit after response */
  466 #define  DCON_RACMD             (1<<19) /* Receive after command */
  467 #define  DCON_BACMD             (1<<18) /* Busy after command */
  468 #define  DCON_BLKMODE           (1<<17) /* Stream/Block mode */
  469 #define  DCON_WIDEBUS           (1<<16) /* Standard/Wide bus */
  470 #define  DCON_ENDMA             (1<<15) /* DMA Enable */
  471 /* Determine the direction of the data transfer */
  472 #define  DCON_DATA_READY        (0<<12) /* No transfer */
  473 #define  DCON_ONLYBUST          (1<<12) /* Check if busy */
  474 #define  DCON_DATA_RECEIVE      (2<<12) /* Receive data from SD */
  475 #define  DCON_DATA_TRANSMIT     (3<<12) /* Send data to SD */
  476 #define  DCON_BLKNUM_MASK       (0x7FF) /* Block number */
  477 #define SDI_DCNT        0x30
  478 #define SDI_DSTA        0x34
  479 #define SDI_FSTA        0x38
  480 #define  FSTA_TX_AVAIL          (1<<13)
  481 #define  FSTA_RX_AVAIL          (1<<12)
  482 #define  FSTA_TX_FIFO_HALF_FULL (1<<11)
  483 #define  FSTA_TX_FIFO_EMPTY     (1<<10)
  484 #define  FSTA_RX_FIFO_LAST_DATA (1<<9)
  485 #define  FSTA_RX_FIFO_FULL      (1<<8)
  486 #define  FSTA_RX_FIFO_HALF_FULL (1<<7)
  487 #define  FSTA_FIFO_COUNT_MSK    (0x7F)
  488 
  489 /* Timer */
  490 #define TIMER_TCFG0     0x00    /* Timer configuration */
  491 #define TIMER_TCFG1     0x04
  492 #define  TCFG1_MUX_SHIFT(n)     (4*(n))
  493 #define  TCFG1_MUX_MASK(n)      (0x0f << TCFG1_MUX_SHIFT(n))
  494 #define  TCFG1_MUX_DIV2         0
  495 #define  TCFG1_MUX_DIV4         1
  496 #define  TCFG1_MUX_DIV8         2
  497 #define  TCFG1_MUX_DIV16        3
  498 #define  TCFG1_MUX_EXT          4
  499 #define TIMER_TCON      0x08    /* control */
  500 #define  TCON_SHIFT(n)          (4 * ((n)==0 ? 0 : (n)+1))
  501 #define  TCON_START(n)          (1 << TCON_SHIFT(n))
  502 #define  TCON_MANUALUPDATE(n)   (1 << (TCON_SHIFT(n) + 1))
  503 #define  TCON_INVERTER(n)       (1 << (TCON_SHIFT(n) + 2))
  504 #define  __TCON_AUTORELOAD(n)   (1 << (TCON_SHIFT(n) + 3)) /* n=0..3 */
  505 #define  TCON_AUTORELOAD4       (1<<22)        /* stupid hardware design */
  506 #define  TCON_AUTORELOAD(n)     \
  507         ((n)==4 ? TCON_AUTORELOAD4 : __TCON_AUTORELOAD(n))
  508 #define  TCON_MASK(n)           (0x0f << TCON_SHIFT(n))
  509 #define TIMER_TCNTB(n)   (0x0c+0x0c*(n))        /* count buffer */
  510 #define TIMER_TCMPB(n)   (0x10+0x0c*(n))        /* compare buffer */
  511 #define __TIMER_TCNTO(n) (0x14+0x0c*(n))        /* count observation */
  512 #define TIMER_TCNTO4    0x40
  513 #define TIMER_TCNTO(n)  ((n)==4 ? TIMER_TCNTO4 : __TIMER_TCNTO(n))
  514 
  515 #define S3C24X0_TIMER_SIZE      0x44
  516 
  517 /* UART */
  518 /* diffs to s3c2800 */
  519 /* SSCOM_UMCON */
  520 #define  UMCON_AFC      (1<<4)  /* auto flow control */
  521 /* SSCOM_UMSTAT */
  522 #define  UMSTAT_DCTS    (1<<2)  /* CTS change */
  523 /* SSCOM_UMSTAT */
  524 #define  ULCON_IR       (1<<6)
  525 #define  ULCON_PARITY_SHIFT  3
  526 
  527 #define S3C24X0_UART_SIZE       0x2c
  528 
  529 /* USB device */
  530 /* XXX */
  531 
  532 /* Watch dog timer */
  533 #define WDT_WTCON       0x00    /* WDT mode */
  534 #define  WTCON_PRESCALE_SHIFT   8
  535 #define  WTCON_PRESCALE (0xff<<WTCON_PRESCALE_SHIFT)
  536 #define  WTCON_ENABLE   (1<<5)
  537 #define  WTCON_CLKSEL   (3<<3)
  538 #define  WTCON_CLKSEL_16  (0<<3)
  539 #define  WTCON_CLKSEL_32  (1<<3)
  540 #define  WTCON_CLKSEL_64  (2<<3)
  541 #define  WTCON_CLKSEL_128 (3<<3)
  542 #define  WTCON_ENINT    (1<<2)
  543 #define  WTCON_ENRST    (1<<0)
  544 
  545 #define  WTCON_WDTSTOP  0
  546         
  547 #define WDT_WTDAT       0x04    /* timer data */
  548 #define WDT_WTCNT       0x08    /* timer count */
  549 
  550 #define S3C24X0_WDT_SIZE        0x0c
  551 
  552 /* IIC */
  553 #define S3C24X0_IIC_SIZE        0x0c
  554 
  555 
  556 /* IIS */
  557 #define S3C24X0_IIS_SIZE        0x14
  558 
  559 /* GPIO */
  560 #define GPIO_PACON      0x00    /* port A configuration */
  561 #define GPIO_PADAT      0x04    /* port A data */
  562 
  563 #define GPIO_PBCON      0x10
  564 /* These are only used on port B-H on 2410 & B-H,J on 2440 */
  565 #define  PCON_INPUT     0       /* Input port */
  566 #define  PCON_OUTPUT    1       /* Output port */
  567 #define  PCON_ALTFUN    2       /* Alternate function */
  568 #define  PCON_ALTFUN2   3       /* Alternate function */
  569 #define GPIO_PBDAT      0x14
  570 /* This is different between 2440 and 2442 (pull up vs pull down): */
  571 #define GPIO_PBUP       0x18    /* 2410 & 2440 */
  572 #define GPIO_PBDOWN     0x18    /* 2442 */
  573 
  574 #define GPIO_PCCON      0x20
  575 #define GPIO_PCDAT      0x24
  576 #define GPIO_PCUP       0x28    /* 2410 & 2440 */
  577 #define GPIO_PCDOWN     0x28    /* 2442 */
  578 
  579 #define GPIO_PDCON      0x30
  580 #define GPIO_PDDAT      0x34
  581 #define GPIO_PDUP       0x38    /* 2410 & 2440 */
  582 #define GPIO_PDDOWN     0x38    /* 2442 */
  583 
  584 #define GPIO_PECON      0x40
  585 #define  PECON_INPUT(x)         (0<<((x)*2)) /* Pin is used for input */
  586 #define  PECON_OUTPUT(x)        (1<<((x)*2)) /* Pin is used for output */
  587 #define  PECON_FUNC_A(x)        (2<<((x)*2)) /* Pin is used for function 'A' */
  588 #define  PECON_FUNC_B(x)        (3<<((x)*2)) /* Pin is used for function 'B' */
  589 #define  PECON_MASK(x)          (3<<((x)*2))
  590 #define GPIO_PEDAT      0x44
  591 #define GPIO_PEUP       0x48    /* 2410 & 2440 */
  592 #define GPIO_PEDOWN     0x48    /* 2442 */
  593 #define  PEUD_ENABLE(x)         (~(1<<(x))) /* Enable the pull Up/Down */
  594 #define  PEUD_DISABLE(x)        (1<<(x)) /* Disable the pull Up/Down */
  595 
  596 #define GPIO_PFCON      0x50
  597 #define GPIO_PFDAT      0x54
  598 #define GPIO_PFUP       0x58    /* 2410 & 2440 */
  599 #define GPIO_PFDOWN     0x58    /* 2442 */
  600 
  601 #define GPIO_PGCON      0x60
  602 #define GPIO_PGDAT      0x64
  603 #define GPIO_PGUP       0x68    /* 2410 & 2440 */
  604 #define GPIO_PGDOWN     0x68    /* 2442 */
  605 
  606 #define GPIO_PHCON      0x70
  607 #define GPIO_PHDAT      0x74
  608 #define GPIO_PHUP       0x78    /* 2410 & 2440 */
  609 #define GPIO_PHDOWN     0x78    /* 2442 */
  610 
  611 #define GPIO_MISCCR     0x80    /* miscellaneous control */
  612 #define GPIO_DCLKCON    0x84    /* DCLK 0/1 */
  613 #define GPIO_EXTINT(n)  (0x88+4*(n))    /* external int control 0/1/2 */
  614 #define GPIO_EINTFLT(n) (0x94+4*(n))    /* external int filter control 0..3 */
  615 #define  EXTINTR_LOW     0x00
  616 #define  EXTINTR_HIGH    0x01
  617 #define  EXTINTR_FALLING 0x02
  618 #define  EXTINTR_RISING  0x04
  619 #define  EXTINTR_BOTH    0x06
  620 #define GPIO_EINTMASK   0xa4
  621 #define GPIO_EINTPEND   0xa8
  622 #define GPIO_GSTATUS0   0xac    /* external pin status */
  623 #define GPIO_GSTATUS1   0xb0    /* Chip ID */
  624 #define  CHIPID_S3C2410A        0x32410002
  625 #define  CHIPID_S3C2440A        0x32440001
  626 #define  CHIPID_S3C2442B        0x32440AAB
  627 #define GPIO_GSTATUS2   0xb4    /* Reset status */
  628 #define GPIO_GSTATUS3   0xb8
  629 #define GPIO_GSTATUS4   0xbc
  630 
  631 #define GPIO_SET_FUNC(v,port,func)      \
  632                 (((v) & ~(3<<(2*(port))))|((func)<<(2*(port))))
  633 
  634 /* ADC */
  635 #define ADC_ADCCON      0x00
  636 #define  ADCCON_ENABLE_START    (1<<0)
  637 #define  ADCCON_READ_START      (1<<1)
  638 #define  ADCCON_STDBM           (1<<2)
  639 #define  ADCCON_SEL_MUX_SHIFT   3
  640 #define  ADCCON_SEL_MUX_MASK    (0x7<<ADCCON_SEL_MUX_SHIFT)
  641 #define  ADCCON_PRSCVL_SHIFT    6
  642 #define  ADCCON_PRSCVL_MASK     (0xff<<ADCCON_PRSCVL_SHIFT)
  643 #define  ADCCON_PRSCEN          (1<<14)
  644 #define  ADCCON_ECFLG           (1<<15)
  645 
  646 #define ADC_ADCTSC      0x04
  647 #define  ADCTSC_XY_PST          0x03
  648 #define  ADCTSC_AUTO_PST        (1<<2)
  649 #define  ADCTSC_PULL_UP         (1<<3)
  650 #define  ADCTSC_XP_SEN          (1<<4)
  651 #define  ADCTSC_XM_SEN          (1<<5)
  652 #define  ADCTSC_YP_SEN          (1<<6)
  653 #define  ADCTSC_YM_SEN          (1<<7)
  654 #define ADC_ADCDLY      0x08
  655 #define ADC_ADCDAT0     0x0c
  656 #define ADC_ADCDAT1     0x10
  657 
  658 #define ADCDAT_DATAMASK         0x3ff
  659 
  660 /* RTC */
  661 #define RTC_RTCCON              0x40
  662 #define  RTCCON_RTCEN           (1<<0)
  663 #define  RTCCON_CLKSEL          (1<<1)
  664 #define  RTCCON_CNTSEL          (1<<2)
  665 #define  RTCCON_CLKRST          (1<<3)
  666 #define RTC_TICNT0              0x44
  667 /* TICNT1 on 2440 */
  668 #define RTC_RTCALM              0x50
  669 #define RTC_ALMSEC              0x54
  670 #define RTC_ALMMIN              0x58
  671 #define RTC_ALMHOUR             0x5C
  672 #define RTC_ALMDATE             0x60
  673 #define RTC_ALMMON              0x64
  674 #define RTC_ALMYEAR             0x68
  675 /* RTCRST on 2410 */
  676 #define RTC_BCDSEC              0x70
  677 #define RTC_BCDMIN              0x74
  678 #define RTC_BCDHOUR             0x78
  679 #define RTC_BCDDATE             0x7C
  680 #define RTC_BCDDAY              0x80
  681 #define RTC_BCDMON              0x84
  682 #define RTC_BCDYEAR             0x88
  683 
  684 
  685 /* SPI */
  686 #define S3C24X0_SPI_SIZE        0x20
  687 
  688 #define SPI_SPCON               0x00
  689 #define  SPCON_TAGD             (1<<0) /* Tx auto garbage */
  690 #define  SPCON_CPHA             (1<<1)
  691 #define  SPCON_CPOL             (1<<2)
  692 #define  SPCON_IDLELOW_RISING     (0|0)
  693 #define  SPCON_IDLELOW_FALLING    (0|SPCON_CPHA)
  694 #define  SPCON_IDLEHIGH_FALLING  (SPCON_CPOL|0)
  695 #define  SPCON_IDLEHIGH_RISING    (SPCON_CPOL|SPCON_CPHA)
  696 #define  SPCON_MSTR             (1<<3)
  697 #define  SPCON_ENSCK            (1<<4)
  698 #define  SPCON_SMOD_SHIFT       5
  699 #define  SPCON_SMOD_MASK        (0x03<<SPCON_SMOD_SHIFT)
  700 #define  SPCON_SMOD_POLL        (0x00<<SPCON_SMOD_SHIFT)
  701 #define  SPCON_SMOD_INT         (0x01<<SPCON_SMOD_SHIFT)
  702 #define  SPCON_SMOD_DMA         (0x02<<SPCON_SMOD_SHIFT)
  703 
  704 #define SPI_SPSTA               0x04 /* status register */
  705 #define  SPSTA_REDY             (1<<0) /* ready */
  706 #define  SPSTA_MULF             (1<<1) /* multi master error */
  707 #define  SPSTA_DCOL             (1<<2) /* Data collision error */
  708 
  709 #define SPI_SPPIN               0x08
  710 #define  SPPIN_KEEP             (1<<0)
  711 #define  SPPIN_ENMUL            (1<<2) /* multi master error detect */
  712 
  713 #define SPI_SPPRE               0x0c /* prescaler */
  714 #define SPI_SPTDAT              0x10 /* tx data */
  715 #define SPI_SPRDAT              0x14 /* rx data */
  716 
  717 
  718 #endif /* _ARM_S3C2XX0_S3C24X0REG_H_ */

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