The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/sa11x0/sa11x0_dmacreg.h

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    1 /*      $NetBSD: sa11x0_dmacreg.h,v 1.1 2001/07/08 23:37:53 rjs Exp $   */
    2 
    3 /*-
    4  * Copyright (c) 2001, The NetBSD Foundation, Inc.  All rights reserved.
    5  *
    6  * This code is derived from software contributed to The NetBSD Foundation
    7  * by IWAMOTO Toshihiro.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  *
   30  * $FreeBSD: releng/9.0/sys/arm/sa11x0/sa11x0_dmacreg.h 203974 2010-02-16 21:59:17Z imp $
   31  *
   32  */
   33 
   34 /* SA11[01]0 integrated DMA controller */
   35 
   36 #define SADMAC_NPORTS           40
   37 
   38 #define SADMAC_DAR0             0x00    /* DMA device address register */
   39 #define SADMAC_DCR0_SET         0x04    /* DMA control/status (set) */
   40 #define SADMAC_DCR0_CLR         0x08    /* DMA control/status (clear) */
   41 #define SADMAC_DCR0             0x0C    /* DMA control/status (read only) */
   42 #define SADMAC_DBSA0            0x10    /* DMA Buffer A start address */
   43 #define SADMAC_DBTA0            0x14    /* DMA Buffer A transfer count */
   44 #define SADMAC_DBSB0            0x18    /* DMA Buffer B start address */
   45 #define SADMAC_DBTB0            0x1C    /* DMA Buffer B transfer count */
   46 
   47 #define SADMAC_DAR1             0x20
   48 #define SADMAC_DCR1_SET         0x24
   49 #define SADMAC_DCR1_CLR         0x28
   50 #define SADMAC_DCR1             0x2C
   51 #define SADMAC_DBSA1            0x30
   52 #define SADMAC_DBTA1            0x34
   53 #define SADMAC_DBSB1            0x38
   54 #define SADMAC_DBTB1            0x3C
   55 
   56 #define SADMAC_DAR2             0x40
   57 #define SADMAC_DCR2_SET         0x44
   58 #define SADMAC_DCR2_CLR         0x48
   59 #define SADMAC_DCR2             0x4C
   60 #define SADMAC_DBSA2            0x50
   61 #define SADMAC_DBTA2            0x54
   62 #define SADMAC_DBSB2            0x58
   63 #define SADMAC_DBTB2            0x5C
   64 
   65 #define SADMAC_DAR3             0x60
   66 #define SADMAC_DCR3_SET         0x64
   67 #define SADMAC_DCR3_CLR         0x68
   68 #define SADMAC_DCR3             0x6C
   69 #define SADMAC_DBSA3            0x70
   70 #define SADMAC_DBTA3            0x74
   71 #define SADMAC_DBSB3            0x78
   72 #define SADMAC_DBTB3            0x7C
   73 
   74 #define SADMAC_DAR4             0x80
   75 #define SADMAC_DCR4_SET         0x84
   76 #define SADMAC_DCR4_CLR         0x88
   77 #define SADMAC_DCR4             0x8C
   78 #define SADMAC_DBSA4            0x90
   79 #define SADMAC_DBTA4            0x94
   80 #define SADMAC_DBSB4            0x98
   81 #define SADMAC_DBTB4            0x9C
   82 
   83 #define SADMAC_DAR5             0xA0
   84 #define SADMAC_DCR5_SET         0xA4
   85 #define SADMAC_DCR5_CLR         0xA8
   86 #define SADMAC_DCR5             0xAC
   87 #define SADMAC_DBSA5            0xB0
   88 #define SADMAC_DBTA5            0xB4
   89 #define SADMAC_DBSB5            0xB8
   90 #define SADMAC_DBTB5            0xBC

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