1 /* $NetBSD: sa11x0_reg.h,v 1.4 2002/07/19 18:26:56 ichiro Exp $ */
2
3 /*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc. All rights reserved.
5 *
6 * This code is derived from software contributed to The NetBSD Foundation
7 * by IWAMOTO Toshihiro.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the NetBSD
20 * Foundation, Inc. and its contributors.
21 * 4. Neither the name of The NetBSD Foundation nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 *
37 * $FreeBSD: src/sys/arm/sa11x0/sa11x0_reg.h,v 1.3 2006/05/23 12:14:14 cognet Exp $
38 *
39 */
40
41 #ifndef _ARM_SA11X0_REG_H_
42 #define _ARM_SA11X0_REG_H_
43
44 /* Physical register base addresses */
45 #define SAOST_BASE 0x90000000 /* OS Timer */
46 #define SARTC_BASE 0x90010000 /* Real-Time Clock */
47 #define SAPMR_BASE 0x90020000 /* Power Manager */
48 #define SARCR_BASE 0x90030000 /* Reset Controller */
49 #define SAGPIO_BASE 0x90040000 /* GPIO */
50 #define SAIPIC_BASE 0x90050000 /* Interrupt Controller */
51 #define SAIPIC_SIZE 0x24
52 #define SAPPC_BASE 0x90060000 /* Peripheral Pin Controller */
53 #define SAUDC_BASE 0x80000000 /* USB Device Controller*/
54 #define SACOM1_BASE 0x80010000 /* GPCLK/UART 1 */
55 #define SACOM1_SIZE 0x24
56 #define SACOM3_HW_BASE 0x80050000 /* UART 3 */
57 #define SAMCP_BASE 0x80060000 /* MCP Controller */
58 #define SASSP_BASE 0x80070000 /* Synchronous serial port */
59
60 #define SADMAC_BASE 0xB0000000 /* DMA Controller */
61 #define SALCD_BASE 0xB0100000 /* LCD */
62
63 /* Register base virtual addresses mapped by initarm() */
64 #define SACOM1_VBASE 0xd000d000
65
66 /* Interrupt controller registers */
67 #define SAIPIC_NPORTS 9
68 #define SAIPIC_IP 0x00 /* IRQ pending register */
69 #define SAIPIC_MR 0x04 /* Mask register */
70 #define SAIPIC_LR 0x08 /* Level register */
71 #define SAIPIC_FP 0x10 /* FIQ pending register */
72 #define SAIPIC_PR 0x20 /* Pending register */
73 #define SAIPIC_CR 0x0C /* Control register */
74
75 /* width of interrupt controller */
76 #define ICU_LEN 32
77
78 /* Reset controller registers */
79 #define SARCR_RSRR 0x0 /* Software reset register */
80 #define SARCR_RCSR 0x4 /* Reset status register */
81 #define SARCR_TUCR 0x8 /* Test Unit control reg */
82
83 #endif /* _ARM_SA11X0_REG_H_ */
84 Cache object: a427c44dcc1928bcb63d99467fcdfa0c
|