1 /* $NetBSD: sa11x0_reg.h,v 1.4 2002/07/19 18:26:56 ichiro Exp $ */
2
3 /*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc. All rights reserved.
5 *
6 * This code is derived from software contributed to The NetBSD Foundation
7 * by IWAMOTO Toshihiro.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 *
30 * $FreeBSD: releng/10.0/sys/arm/sa11x0/sa11x0_reg.h 203974 2010-02-16 21:59:17Z imp $
31 *
32 */
33
34 #ifndef _ARM_SA11X0_REG_H_
35 #define _ARM_SA11X0_REG_H_
36
37 /* Physical register base addresses */
38 #define SAOST_BASE 0x90000000 /* OS Timer */
39 #define SARTC_BASE 0x90010000 /* Real-Time Clock */
40 #define SAPMR_BASE 0x90020000 /* Power Manager */
41 #define SARCR_BASE 0x90030000 /* Reset Controller */
42 #define SAGPIO_BASE 0x90040000 /* GPIO */
43 #define SAIPIC_BASE 0x90050000 /* Interrupt Controller */
44 #define SAIPIC_SIZE 0x24
45 #define SAPPC_BASE 0x90060000 /* Peripheral Pin Controller */
46 #define SAUDC_BASE 0x80000000 /* USB Device Controller*/
47 #define SACOM1_BASE 0x80010000 /* GPCLK/UART 1 */
48 #define SACOM1_SIZE 0x24
49 #define SACOM3_HW_BASE 0x80050000 /* UART 3 */
50 #define SAMCP_BASE 0x80060000 /* MCP Controller */
51 #define SASSP_BASE 0x80070000 /* Synchronous serial port */
52
53 #define SADMAC_BASE 0xB0000000 /* DMA Controller */
54 #define SALCD_BASE 0xB0100000 /* LCD */
55
56 /* Register base virtual addresses mapped by initarm() */
57 #define SACOM1_VBASE 0xd000d000
58
59 /* Interrupt controller registers */
60 #define SAIPIC_NPORTS 9
61 #define SAIPIC_IP 0x00 /* IRQ pending register */
62 #define SAIPIC_MR 0x04 /* Mask register */
63 #define SAIPIC_LR 0x08 /* Level register */
64 #define SAIPIC_FP 0x10 /* FIQ pending register */
65 #define SAIPIC_PR 0x20 /* Pending register */
66 #define SAIPIC_CR 0x0C /* Control register */
67
68 /* width of interrupt controller */
69 #define ICU_LEN 32
70
71 /* Reset controller registers */
72 #define SARCR_RSRR 0x0 /* Software reset register */
73 #define SARCR_RCSR 0x4 /* Reset status register */
74 #define SARCR_TUCR 0x8 /* Test Unit control reg */
75
76 #endif /* _ARM_SA11X0_REG_H_ */
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