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sys/arm/ti/am335x/tda19988.c
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1 /*- 2 * Copyright (c) 2015 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 /* 30 * NXP TDA19988 HDMI encoder 31 */ 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/clock.h> 37 #include <sys/eventhandler.h> 38 #include <sys/time.h> 39 #include <sys/bus.h> 40 #include <sys/resource.h> 41 #include <sys/rman.h> 42 #include <sys/types.h> 43 #include <sys/systm.h> 44 45 #include <dev/iicbus/iicbus.h> 46 #include <dev/iicbus/iiconf.h> 47 48 #include <dev/ofw/openfirm.h> 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <dev/videomode/videomode.h> 53 #include <dev/videomode/edidvar.h> 54 55 #include "iicbus_if.h" 56 #include "hdmi_if.h" 57 58 #define MKREG(page, addr) (((page) << 8) | (addr)) 59 60 #define REGPAGE(reg) (((reg) >> 8) & 0xff) 61 #define REGADDR(reg) ((reg) & 0xff) 62 63 #define TDA_VERSION MKREG(0x00, 0x00) 64 #define TDA_MAIN_CNTRL0 MKREG(0x00, 0x01) 65 #define MAIN_CNTRL0_SR (1 << 0) 66 #define TDA_VERSION_MSB MKREG(0x00, 0x02) 67 #define TDA_SOFTRESET MKREG(0x00, 0x0a) 68 #define SOFTRESET_I2C (1 << 1) 69 #define SOFTRESET_AUDIO (1 << 0) 70 #define TDA_DDC_CTRL MKREG(0x00, 0x0b) 71 #define DDC_ENABLE 0 72 #define TDA_CCLK MKREG(0x00, 0x0c) 73 #define CCLK_ENABLE 1 74 #define TDA_INT_FLAGS_2 MKREG(0x00, 0x11) 75 #define INT_FLAGS_2_EDID_BLK_RD (1 << 1) 76 77 #define TDA_VIP_CNTRL_0 MKREG(0x00, 0x20) 78 #define TDA_VIP_CNTRL_1 MKREG(0x00, 0x21) 79 #define TDA_VIP_CNTRL_2 MKREG(0x00, 0x22) 80 #define TDA_VIP_CNTRL_3 MKREG(0x00, 0x23) 81 #define VIP_CNTRL_3_SYNC_HS (2 << 4) 82 #define VIP_CNTRL_3_V_TGL (1 << 2) 83 #define VIP_CNTRL_3_H_TGL (1 << 1) 84 85 #define TDA_VIP_CNTRL_4 MKREG(0x00, 0x24) 86 #define VIP_CNTRL_4_BLANKIT_NDE (0 << 2) 87 #define VIP_CNTRL_4_BLANKIT_HS_VS (1 << 2) 88 #define VIP_CNTRL_4_BLANKIT_NHS_VS (2 << 2) 89 #define VIP_CNTRL_4_BLANKIT_HE_VE (3 << 2) 90 #define VIP_CNTRL_4_BLC_NONE (0 << 0) 91 #define VIP_CNTRL_4_BLC_RGB444 (1 << 0) 92 #define VIP_CNTRL_4_BLC_YUV444 (2 << 0) 93 #define VIP_CNTRL_4_BLC_YUV422 (3 << 0) 94 #define TDA_VIP_CNTRL_5 MKREG(0x00, 0x25) 95 #define VIP_CNTRL_5_SP_CNT(n) (((n) & 3) << 1) 96 #define TDA_MUX_VP_VIP_OUT MKREG(0x00, 0x27) 97 #define TDA_MAT_CONTRL MKREG(0x00, 0x80) 98 #define MAT_CONTRL_MAT_BP (1 << 2) 99 #define TDA_VIDFORMAT MKREG(0x00, 0xa0) 100 #define TDA_REFPIX_MSB MKREG(0x00, 0xa1) 101 #define TDA_REFPIX_LSB MKREG(0x00, 0xa2) 102 #define TDA_REFLINE_MSB MKREG(0x00, 0xa3) 103 #define TDA_REFLINE_LSB MKREG(0x00, 0xa4) 104 #define TDA_NPIX_MSB MKREG(0x00, 0xa5) 105 #define TDA_NPIX_LSB MKREG(0x00, 0xa6) 106 #define TDA_NLINE_MSB MKREG(0x00, 0xa7) 107 #define TDA_NLINE_LSB MKREG(0x00, 0xa8) 108 #define TDA_VS_LINE_STRT_1_MSB MKREG(0x00, 0xa9) 109 #define TDA_VS_LINE_STRT_1_LSB MKREG(0x00, 0xaa) 110 #define TDA_VS_PIX_STRT_1_MSB MKREG(0x00, 0xab) 111 #define TDA_VS_PIX_STRT_1_LSB MKREG(0x00, 0xac) 112 #define TDA_VS_LINE_END_1_MSB MKREG(0x00, 0xad) 113 #define TDA_VS_LINE_END_1_LSB MKREG(0x00, 0xae) 114 #define TDA_VS_PIX_END_1_MSB MKREG(0x00, 0xaf) 115 #define TDA_VS_PIX_END_1_LSB MKREG(0x00, 0xb0) 116 #define TDA_VS_LINE_STRT_2_MSB MKREG(0x00, 0xb1) 117 #define TDA_VS_LINE_STRT_2_LSB MKREG(0x00, 0xb2) 118 #define TDA_VS_PIX_STRT_2_MSB MKREG(0x00, 0xb3) 119 #define TDA_VS_PIX_STRT_2_LSB MKREG(0x00, 0xb4) 120 #define TDA_VS_LINE_END_2_MSB MKREG(0x00, 0xb5) 121 #define TDA_VS_LINE_END_2_LSB MKREG(0x00, 0xb6) 122 #define TDA_VS_PIX_END_2_MSB MKREG(0x00, 0xb7) 123 #define TDA_VS_PIX_END_2_LSB MKREG(0x00, 0xb8) 124 #define TDA_HS_PIX_START_MSB MKREG(0x00, 0xb9) 125 #define TDA_HS_PIX_START_LSB MKREG(0x00, 0xba) 126 #define TDA_HS_PIX_STOP_MSB MKREG(0x00, 0xbb) 127 #define TDA_HS_PIX_STOP_LSB MKREG(0x00, 0xbc) 128 #define TDA_VWIN_START_1_MSB MKREG(0x00, 0xbd) 129 #define TDA_VWIN_START_1_LSB MKREG(0x00, 0xbe) 130 #define TDA_VWIN_END_1_MSB MKREG(0x00, 0xbf) 131 #define TDA_VWIN_END_1_LSB MKREG(0x00, 0xc0) 132 #define TDA_VWIN_START_2_MSB MKREG(0x00, 0xc1) 133 #define TDA_VWIN_START_2_LSB MKREG(0x00, 0xc2) 134 #define TDA_VWIN_END_2_MSB MKREG(0x00, 0xc3) 135 #define TDA_VWIN_END_2_LSB MKREG(0x00, 0xc4) 136 #define TDA_DE_START_MSB MKREG(0x00, 0xc5) 137 #define TDA_DE_START_LSB MKREG(0x00, 0xc6) 138 #define TDA_DE_STOP_MSB MKREG(0x00, 0xc7) 139 #define TDA_DE_STOP_LSB MKREG(0x00, 0xc8) 140 141 #define TDA_TBG_CNTRL_0 MKREG(0x00, 0xca) 142 #define TBG_CNTRL_0_SYNC_ONCE (1 << 7) 143 #define TBG_CNTRL_0_SYNC_MTHD (1 << 6) 144 145 #define TDA_TBG_CNTRL_1 MKREG(0x00, 0xcb) 146 #define TBG_CNTRL_1_DWIN_DIS (1 << 6) 147 #define TBG_CNTRL_1_TGL_EN (1 << 2) 148 #define TBG_CNTRL_1_V_TGL (1 << 1) 149 #define TBG_CNTRL_1_H_TGL (1 << 0) 150 151 #define TDA_HVF_CNTRL_0 MKREG(0x00, 0xe4) 152 #define HVF_CNTRL_0_PREFIL_NONE (0 << 2) 153 #define HVF_CNTRL_0_INTPOL_BYPASS (0 << 0) 154 #define TDA_HVF_CNTRL_1 MKREG(0x00, 0xe5) 155 #define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) 156 #define HVF_CNTRL_1_VQR_FULL HVF_CNTRL_1_VQR(0) 157 #define TDA_ENABLE_SPACE MKREG(0x00, 0xd6) 158 #define TDA_RPT_CNTRL MKREG(0x00, 0xf0) 159 160 #define TDA_PLL_SERIAL_1 MKREG(0x02, 0x00) 161 #define PLL_SERIAL_1_SRL_MAN_IP (1 << 6) 162 #define TDA_PLL_SERIAL_2 MKREG(0x02, 0x01) 163 #define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) 164 #define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 0x3) << 0) 165 #define TDA_PLL_SERIAL_3 MKREG(0x02, 0x02) 166 #define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) 167 #define PLL_SERIAL_3_SRL_DE (1 << 2) 168 #define PLL_SERIAL_3_SRL_CCIR (1 << 0) 169 #define TDA_SERIALIZER MKREG(0x02, 0x03) 170 #define TDA_BUFFER_OUT MKREG(0x02, 0x04) 171 #define TDA_PLL_SCG1 MKREG(0x02, 0x05) 172 #define TDA_PLL_SCG2 MKREG(0x02, 0x06) 173 #define TDA_PLL_SCGN1 MKREG(0x02, 0x07) 174 #define TDA_PLL_SCGN2 MKREG(0x02, 0x08) 175 #define TDA_PLL_SCGR1 MKREG(0x02, 0x09) 176 #define TDA_PLL_SCGR2 MKREG(0x02, 0x0a) 177 178 #define TDA_SEL_CLK MKREG(0x02, 0x11) 179 #define SEL_CLK_ENA_SC_CLK (1 << 3) 180 #define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) 181 #define SEL_CLK_SEL_CLK1 (1 << 0) 182 #define TDA_ANA_GENERAL MKREG(0x02, 0x12) 183 184 #define TDA_EDID_DATA0 MKREG(0x09, 0x00) 185 #define TDA_EDID_CTRL MKREG(0x09, 0xfa) 186 #define TDA_DDC_ADDR MKREG(0x09, 0xfb) 187 #define TDA_DDC_OFFS MKREG(0x09, 0xfc) 188 #define TDA_DDC_SEGM_ADDR MKREG(0x09, 0xfd) 189 #define TDA_DDC_SEGM MKREG(0x09, 0xfe) 190 191 #define TDA_IF_VSP MKREG(0x10, 0x20) 192 #define TDA_IF_AVI MKREG(0x10, 0x40) 193 #define TDA_IF_SPD MKREG(0x10, 0x60) 194 #define TDA_IF_AUD MKREG(0x10, 0x80) 195 #define TDA_IF_MPS MKREG(0x10, 0xa0) 196 197 #define TDA_ENC_CNTRL MKREG(0x11, 0x0d) 198 #define ENC_CNTRL_DVI_MODE (0 << 2) 199 #define ENC_CNTRL_HDMI_MODE (1 << 2) 200 #define TDA_DIP_IF_FLAGS MKREG(0x11, 0x0f) 201 #define DIP_IF_FLAGS_IF5 (1 << 5) 202 #define DIP_IF_FLAGS_IF4 (1 << 4) 203 #define DIP_IF_FLAGS_IF3 (1 << 3) 204 #define DIP_IF_FLAGS_IF2 (1 << 2) /* AVI IF on page 10h */ 205 #define DIP_IF_FLAGS_IF1 (1 << 1) 206 207 #define TDA_TX3 MKREG(0x12, 0x9a) 208 #define TDA_TX4 MKREG(0x12, 0x9b) 209 #define TX4_PD_RAM (1 << 1) 210 #define TDA_HDCP_TX33 MKREG(0x12, 0xb8) 211 #define HDCP_TX33_HDMI (1 << 1) 212 213 #define TDA_CURPAGE_ADDR 0xff 214 215 #define TDA_CEC_ENAMODS 0xff 216 #define ENAMODS_RXSENS (1 << 2) 217 #define ENAMODS_HDMI (1 << 1) 218 #define TDA_CEC_FRO_IM_CLK_CTRL 0xfb 219 #define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) 220 #define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) 221 222 /* EDID reading */ 223 #define EDID_LENGTH 0x80 224 #define MAX_READ_ATTEMPTS 100 225 226 /* EDID fields */ 227 #define EDID_MODES0 35 228 #define EDID_MODES1 36 229 #define EDID_TIMING_START 38 230 #define EDID_TIMING_END 54 231 #define EDID_TIMING_X(v) (((v) + 31) * 8) 232 #define EDID_FREQ(v) (((v) & 0x3f) + 60) 233 #define EDID_RATIO(v) (((v) >> 6) & 0x3) 234 #define EDID_RATIO_10x16 0 235 #define EDID_RATIO_3x4 1 236 #define EDID_RATIO_4x5 2 237 #define EDID_RATIO_9x16 3 238 239 #define TDA19988 0x0301 240 241 struct tda19988_softc { 242 device_t sc_dev; 243 uint32_t sc_addr; 244 uint32_t sc_cec_addr; 245 uint16_t sc_version; 246 int sc_current_page; 247 uint8_t *sc_edid; 248 uint32_t sc_edid_len; 249 }; 250 251 static int 252 tda19988_set_page(struct tda19988_softc *sc, uint8_t page) 253 { 254 uint8_t addr = TDA_CURPAGE_ADDR; 255 uint8_t cmd[2]; 256 int result; 257 struct iic_msg msg[] = { 258 { sc->sc_addr, IIC_M_WR, 2, cmd }, 259 }; 260 261 cmd[0] = addr; 262 cmd[1] = page; 263 264 result = (iicbus_transfer(sc->sc_dev, msg, 1)); 265 if (result) 266 printf("tda19988_set_page failed: %d\n", result); 267 else 268 sc->sc_current_page = page; 269 270 return (result); 271 } 272 273 static int 274 tda19988_cec_read(struct tda19988_softc *sc, uint8_t addr, uint8_t *data) 275 { 276 int result; 277 struct iic_msg msg[] = { 278 { sc->sc_cec_addr, IIC_M_WR, 1, &addr }, 279 { sc->sc_cec_addr, IIC_M_RD, 1, data }, 280 }; 281 282 result = iicbus_transfer(sc->sc_dev, msg, 2); 283 if (result) 284 printf("tda19988_cec_read failed: %d\n", result); 285 return (result); 286 } 287 288 static int 289 tda19988_cec_write(struct tda19988_softc *sc, uint8_t address, uint8_t data) 290 { 291 uint8_t cmd[2]; 292 int result; 293 struct iic_msg msg[] = { 294 { sc->sc_cec_addr, IIC_M_WR, 2, cmd }, 295 }; 296 297 cmd[0] = address; 298 cmd[1] = data; 299 300 result = iicbus_transfer(sc->sc_dev, msg, 1); 301 if (result) 302 printf("tda19988_cec_write failed: %d\n", result); 303 return (result); 304 } 305 306 static int 307 tda19988_block_read(struct tda19988_softc *sc, uint16_t addr, uint8_t *data, int len) 308 { 309 uint8_t reg; 310 int result; 311 struct iic_msg msg[] = { 312 { sc->sc_addr, IIC_M_WR, 1, ® }, 313 { sc->sc_addr, IIC_M_RD, len, data }, 314 }; 315 316 reg = REGADDR(addr); 317 318 if (sc->sc_current_page != REGPAGE(addr)) 319 tda19988_set_page(sc, REGPAGE(addr)); 320 321 result = (iicbus_transfer(sc->sc_dev, msg, 2)); 322 if (result) 323 device_printf(sc->sc_dev, "tda19988_block_read failed: %d\n", result); 324 return (result); 325 } 326 327 static int 328 tda19988_reg_read(struct tda19988_softc *sc, uint16_t addr, uint8_t *data) 329 { 330 uint8_t reg; 331 int result; 332 struct iic_msg msg[] = { 333 { sc->sc_addr, IIC_M_WR, 1, ® }, 334 { sc->sc_addr, IIC_M_RD, 1, data }, 335 }; 336 337 reg = REGADDR(addr); 338 339 if (sc->sc_current_page != REGPAGE(addr)) 340 tda19988_set_page(sc, REGPAGE(addr)); 341 342 result = (iicbus_transfer(sc->sc_dev, msg, 2)); 343 if (result) 344 device_printf(sc->sc_dev, "tda19988_reg_read failed: %d\n", result); 345 return (result); 346 } 347 348 static int 349 tda19988_reg_write(struct tda19988_softc *sc, uint16_t address, uint8_t data) 350 { 351 uint8_t cmd[2]; 352 int result; 353 struct iic_msg msg[] = { 354 { sc->sc_addr, IIC_M_WR, 2, cmd }, 355 }; 356 357 cmd[0] = REGADDR(address); 358 cmd[1] = data; 359 360 if (sc->sc_current_page != REGPAGE(address)) 361 tda19988_set_page(sc, REGPAGE(address)); 362 363 result = iicbus_transfer(sc->sc_dev, msg, 1); 364 if (result) 365 device_printf(sc->sc_dev, "tda19988_reg_write failed: %d\n", result); 366 367 return (result); 368 } 369 370 static int 371 tda19988_reg_write2(struct tda19988_softc *sc, uint16_t address, uint16_t data) 372 { 373 uint8_t cmd[3]; 374 int result; 375 struct iic_msg msg[] = { 376 { sc->sc_addr, IIC_M_WR, 3, cmd }, 377 }; 378 379 cmd[0] = REGADDR(address); 380 cmd[1] = (data >> 8); 381 cmd[2] = (data & 0xff); 382 383 if (sc->sc_current_page != REGPAGE(address)) 384 tda19988_set_page(sc, REGPAGE(address)); 385 386 result = iicbus_transfer(sc->sc_dev, msg, 1); 387 if (result) 388 device_printf(sc->sc_dev, "tda19988_reg_write2 failed: %d\n", result); 389 390 return (result); 391 } 392 393 static void 394 tda19988_reg_set(struct tda19988_softc *sc, uint16_t addr, uint8_t flags) 395 { 396 uint8_t data; 397 398 tda19988_reg_read(sc, addr, &data); 399 data |= flags; 400 tda19988_reg_write(sc, addr, data); 401 } 402 403 static void 404 tda19988_reg_clear(struct tda19988_softc *sc, uint16_t addr, uint8_t flags) 405 { 406 uint8_t data; 407 408 tda19988_reg_read(sc, addr, &data); 409 data &= ~flags; 410 tda19988_reg_write(sc, addr, data); 411 } 412 413 static int 414 tda19988_probe(device_t dev) 415 { 416 417 if (!ofw_bus_is_compatible(dev, "nxp,tda998x")) 418 return (ENXIO); 419 420 return (BUS_PROBE_DEFAULT); 421 } 422 423 static void 424 tda19988_init_encoder(struct tda19988_softc *sc, const struct videomode *mode) 425 { 426 uint16_t ref_pix, ref_line, n_pix, n_line; 427 uint16_t hs_pix_start, hs_pix_stop; 428 uint16_t vs1_pix_start, vs1_pix_stop; 429 uint16_t vs1_line_start, vs1_line_end; 430 uint16_t vs2_pix_start, vs2_pix_stop; 431 uint16_t vs2_line_start, vs2_line_end; 432 uint16_t vwin1_line_start, vwin1_line_end; 433 uint16_t vwin2_line_start, vwin2_line_end; 434 uint16_t de_start, de_stop; 435 uint8_t reg, div; 436 437 n_pix = mode->htotal; 438 n_line = mode->vtotal; 439 440 hs_pix_stop = mode->hsync_end - mode->hdisplay; 441 hs_pix_start = mode->hsync_start - mode->hdisplay; 442 443 de_stop = mode->htotal; 444 de_start = mode->htotal - mode->hdisplay; 445 ref_pix = hs_pix_start + 3; 446 447 if (mode->flags & VID_HSKEW) 448 ref_pix += mode->hskew; 449 450 if ((mode->flags & VID_INTERLACE) == 0) { 451 ref_line = 1 + mode->vsync_start - mode->vdisplay; 452 vwin1_line_start = mode->vtotal - mode->vdisplay - 1; 453 vwin1_line_end = vwin1_line_start + mode->vdisplay; 454 455 vs1_pix_start = vs1_pix_stop = hs_pix_start; 456 vs1_line_start = mode->vsync_start - mode->vdisplay; 457 vs1_line_end = vs1_line_start + mode->vsync_end - mode->vsync_start; 458 459 vwin2_line_start = vwin2_line_end = 0; 460 vs2_pix_start = vs2_pix_stop = 0; 461 vs2_line_start = vs2_line_end = 0; 462 } else { 463 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; 464 vwin1_line_start = (mode->vtotal - mode->vdisplay)/2; 465 vwin1_line_end = vwin1_line_start + mode->vdisplay/2; 466 467 vs1_pix_start = vs1_pix_stop = hs_pix_start; 468 vs1_line_start = (mode->vsync_start - mode->vdisplay)/2; 469 vs1_line_end = vs1_line_start + (mode->vsync_end - mode->vsync_start)/2; 470 471 vwin2_line_start = vwin1_line_start + mode->vtotal/2; 472 vwin2_line_end = vwin2_line_start + mode->vdisplay/2; 473 474 vs2_pix_start = vs2_pix_stop = hs_pix_start + mode->htotal/2; 475 vs2_line_start = vs1_line_start + mode->vtotal/2 ; 476 vs2_line_end = vs2_line_start + (mode->vsync_end - mode->vsync_start)/2; 477 } 478 479 div = 148500 / mode->dot_clock; 480 if (div != 0) { 481 div--; 482 if (div > 3) 483 div = 3; 484 } 485 486 /* set HDMI HDCP mode off */ 487 tda19988_reg_set(sc, TDA_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 488 tda19988_reg_clear(sc, TDA_HDCP_TX33, HDCP_TX33_HDMI); 489 tda19988_reg_write(sc, TDA_ENC_CNTRL, ENC_CNTRL_DVI_MODE); 490 491 /* no pre-filter or interpolator */ 492 tda19988_reg_write(sc, TDA_HVF_CNTRL_0, 493 HVF_CNTRL_0_INTPOL_BYPASS | HVF_CNTRL_0_PREFIL_NONE); 494 tda19988_reg_write(sc, TDA_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); 495 tda19988_reg_write(sc, TDA_VIP_CNTRL_4, 496 VIP_CNTRL_4_BLANKIT_NDE | VIP_CNTRL_4_BLC_NONE); 497 498 tda19988_reg_clear(sc, TDA_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR); 499 tda19988_reg_clear(sc, TDA_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IP); 500 tda19988_reg_clear(sc, TDA_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); 501 tda19988_reg_write(sc, TDA_SERIALIZER, 0); 502 tda19988_reg_write(sc, TDA_HVF_CNTRL_1, HVF_CNTRL_1_VQR_FULL); 503 504 tda19988_reg_write(sc, TDA_RPT_CNTRL, 0); 505 tda19988_reg_write(sc, TDA_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | 506 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 507 508 tda19988_reg_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | 509 PLL_SERIAL_2_SRL_PR(0)); 510 511 tda19988_reg_set(sc, TDA_MAT_CONTRL, MAT_CONTRL_MAT_BP); 512 513 tda19988_reg_write(sc, TDA_ANA_GENERAL, 0x09); 514 515 tda19988_reg_clear(sc, TDA_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); 516 517 /* 518 * Sync on rising HSYNC/VSYNC 519 */ 520 reg = VIP_CNTRL_3_SYNC_HS; 521 if (mode->flags & VID_NHSYNC) 522 reg |= VIP_CNTRL_3_H_TGL; 523 if (mode->flags & VID_NVSYNC) 524 reg |= VIP_CNTRL_3_V_TGL; 525 tda19988_reg_write(sc, TDA_VIP_CNTRL_3, reg); 526 527 reg = TBG_CNTRL_1_TGL_EN; 528 if (mode->flags & VID_NHSYNC) 529 reg |= TBG_CNTRL_1_H_TGL; 530 if (mode->flags & VID_NVSYNC) 531 reg |= TBG_CNTRL_1_V_TGL; 532 tda19988_reg_write(sc, TDA_TBG_CNTRL_1, reg); 533 534 /* Program timing */ 535 tda19988_reg_write(sc, TDA_VIDFORMAT, 0x00); 536 537 tda19988_reg_write2(sc, TDA_REFPIX_MSB, ref_pix); 538 tda19988_reg_write2(sc, TDA_REFLINE_MSB, ref_line); 539 tda19988_reg_write2(sc, TDA_NPIX_MSB, n_pix); 540 tda19988_reg_write2(sc, TDA_NLINE_MSB, n_line); 541 542 tda19988_reg_write2(sc, TDA_VS_LINE_STRT_1_MSB, vs1_line_start); 543 tda19988_reg_write2(sc, TDA_VS_PIX_STRT_1_MSB, vs1_pix_start); 544 tda19988_reg_write2(sc, TDA_VS_LINE_END_1_MSB, vs1_line_end); 545 tda19988_reg_write2(sc, TDA_VS_PIX_END_1_MSB, vs1_pix_stop); 546 tda19988_reg_write2(sc, TDA_VS_LINE_STRT_2_MSB, vs2_line_start); 547 tda19988_reg_write2(sc, TDA_VS_PIX_STRT_2_MSB, vs2_pix_start); 548 tda19988_reg_write2(sc, TDA_VS_LINE_END_2_MSB, vs2_line_end); 549 tda19988_reg_write2(sc, TDA_VS_PIX_END_2_MSB, vs2_pix_stop); 550 tda19988_reg_write2(sc, TDA_HS_PIX_START_MSB, hs_pix_start); 551 tda19988_reg_write2(sc, TDA_HS_PIX_STOP_MSB, hs_pix_stop); 552 tda19988_reg_write2(sc, TDA_VWIN_START_1_MSB, vwin1_line_start); 553 tda19988_reg_write2(sc, TDA_VWIN_END_1_MSB, vwin1_line_end); 554 tda19988_reg_write2(sc, TDA_VWIN_START_2_MSB, vwin2_line_start); 555 tda19988_reg_write2(sc, TDA_VWIN_END_2_MSB, vwin2_line_end); 556 tda19988_reg_write2(sc, TDA_DE_START_MSB, de_start); 557 tda19988_reg_write2(sc, TDA_DE_STOP_MSB, de_stop); 558 559 if (sc->sc_version == TDA19988) 560 tda19988_reg_write(sc, TDA_ENABLE_SPACE, 0x00); 561 562 /* must be last register set */ 563 tda19988_reg_clear(sc, TDA_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); 564 } 565 566 static int 567 tda19988_read_edid_block(struct tda19988_softc *sc, uint8_t *buf, int block) 568 { 569 int attempt, err; 570 uint8_t data; 571 572 err = 0; 573 574 tda19988_reg_set(sc, TDA_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 575 576 /* Block 0 */ 577 tda19988_reg_write(sc, TDA_DDC_ADDR, 0xa0); 578 tda19988_reg_write(sc, TDA_DDC_OFFS, (block % 2) ? 128 : 0); 579 tda19988_reg_write(sc, TDA_DDC_SEGM_ADDR, 0x60); 580 tda19988_reg_write(sc, TDA_DDC_SEGM, block / 2); 581 582 tda19988_reg_write(sc, TDA_EDID_CTRL, 1); 583 tda19988_reg_write(sc, TDA_EDID_CTRL, 0); 584 585 data = 0; 586 for (attempt = 0; attempt < MAX_READ_ATTEMPTS; attempt++) { 587 tda19988_reg_read(sc, TDA_INT_FLAGS_2, &data); 588 if (data & INT_FLAGS_2_EDID_BLK_RD) 589 break; 590 pause("EDID", 1); 591 } 592 593 if (attempt == MAX_READ_ATTEMPTS) { 594 err = -1; 595 goto done; 596 } 597 598 if (tda19988_block_read(sc, TDA_EDID_DATA0, buf, EDID_LENGTH) != 0) { 599 err = -1; 600 goto done; 601 } 602 603 done: 604 tda19988_reg_clear(sc, TDA_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 605 606 return (err); 607 } 608 609 static int 610 tda19988_read_edid(struct tda19988_softc *sc) 611 { 612 int err; 613 int blocks, i; 614 uint8_t *buf; 615 616 err = 0; 617 if (sc->sc_version == TDA19988) 618 tda19988_reg_clear(sc, TDA_TX4, TX4_PD_RAM); 619 620 err = tda19988_read_edid_block(sc, sc->sc_edid, 0); 621 if (err) 622 goto done; 623 624 blocks = sc->sc_edid[0x7e]; 625 if (blocks > 0) { 626 sc->sc_edid = realloc(sc->sc_edid, 627 EDID_LENGTH*(blocks+1), M_DEVBUF, M_WAITOK); 628 sc->sc_edid_len = EDID_LENGTH*(blocks+1); 629 for (i = 0; i < blocks; i++) { 630 /* TODO: check validity */ 631 buf = sc->sc_edid + EDID_LENGTH*(i+1); 632 err = tda19988_read_edid_block(sc, buf, i); 633 if (err) 634 goto done; 635 } 636 } 637 638 EVENTHANDLER_INVOKE(hdmi_event, sc->sc_dev, HDMI_EVENT_CONNECTED); 639 done: 640 if (sc->sc_version == TDA19988) 641 tda19988_reg_set(sc, TDA_TX4, TX4_PD_RAM); 642 643 return (err); 644 } 645 646 static void 647 tda19988_start(struct tda19988_softc *sc) 648 { 649 device_t dev; 650 uint8_t data; 651 uint16_t version; 652 653 dev = sc->sc_dev; 654 655 tda19988_cec_write(sc, TDA_CEC_ENAMODS, ENAMODS_RXSENS | ENAMODS_HDMI); 656 DELAY(1000); 657 tda19988_cec_read(sc, 0xfe, &data); 658 659 /* Reset core */ 660 tda19988_reg_set(sc, TDA_SOFTRESET, 3); 661 DELAY(100); 662 tda19988_reg_clear(sc, TDA_SOFTRESET, 3); 663 DELAY(100); 664 665 /* reset transmitter: */ 666 tda19988_reg_set(sc, TDA_MAIN_CNTRL0, MAIN_CNTRL0_SR); 667 tda19988_reg_clear(sc, TDA_MAIN_CNTRL0, MAIN_CNTRL0_SR); 668 669 /* PLL registers common configuration */ 670 tda19988_reg_write(sc, TDA_PLL_SERIAL_1, 0x00); 671 tda19988_reg_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); 672 tda19988_reg_write(sc, TDA_PLL_SERIAL_3, 0x00); 673 tda19988_reg_write(sc, TDA_SERIALIZER, 0x00); 674 tda19988_reg_write(sc, TDA_BUFFER_OUT, 0x00); 675 tda19988_reg_write(sc, TDA_PLL_SCG1, 0x00); 676 tda19988_reg_write(sc, TDA_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 677 tda19988_reg_write(sc, TDA_PLL_SCGN1, 0xfa); 678 tda19988_reg_write(sc, TDA_PLL_SCGN2, 0x00); 679 tda19988_reg_write(sc, TDA_PLL_SCGR1, 0x5b); 680 tda19988_reg_write(sc, TDA_PLL_SCGR2, 0x00); 681 tda19988_reg_write(sc, TDA_PLL_SCG2, 0x10); 682 683 /* Write the default value MUX register */ 684 tda19988_reg_write(sc, TDA_MUX_VP_VIP_OUT, 0x24); 685 686 version = 0; 687 tda19988_reg_read(sc, TDA_VERSION, &data); 688 version |= data; 689 tda19988_reg_read(sc, TDA_VERSION_MSB, &data); 690 version |= (data << 8); 691 692 /* Clear feature bits */ 693 sc->sc_version = version & ~0x30; 694 switch (sc->sc_version) { 695 case TDA19988: 696 device_printf(dev, "TDA19988\n"); 697 break; 698 default: 699 device_printf(dev, "Unknown device: %04x\n", sc->sc_version); 700 return; 701 } 702 703 tda19988_reg_write(sc, TDA_DDC_CTRL, DDC_ENABLE); 704 tda19988_reg_write(sc, TDA_TX3, 39); 705 706 tda19988_cec_write(sc, TDA_CEC_FRO_IM_CLK_CTRL, 707 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); 708 709 if (tda19988_read_edid(sc) < 0) { 710 device_printf(dev, "failed to read EDID\n"); 711 return; 712 } 713 714 /* Default values for RGB 4:4:4 mapping */ 715 tda19988_reg_write(sc, TDA_VIP_CNTRL_0, 0x23); 716 tda19988_reg_write(sc, TDA_VIP_CNTRL_1, 0x01); 717 tda19988_reg_write(sc, TDA_VIP_CNTRL_2, 0x45); 718 } 719 720 static int 721 tda19988_attach(device_t dev) 722 { 723 struct tda19988_softc *sc; 724 phandle_t node; 725 726 sc = device_get_softc(dev); 727 728 sc->sc_dev = dev; 729 sc->sc_addr = iicbus_get_addr(dev); 730 sc->sc_cec_addr = (0x34 << 1); /* hardcoded */ 731 sc->sc_edid = malloc(EDID_LENGTH, M_DEVBUF, M_WAITOK | M_ZERO); 732 sc->sc_edid_len = EDID_LENGTH; 733 734 device_set_desc(dev, "NXP TDA19988 HDMI transmitter"); 735 736 node = ofw_bus_get_node(dev); 737 OF_device_register_xref(OF_xref_from_node(node), dev); 738 739 tda19988_start(sc); 740 741 return (0); 742 } 743 744 static int 745 tda19988_detach(device_t dev) 746 { 747 748 /* XXX: Do not let unload drive */ 749 return (EBUSY); 750 } 751 752 static int 753 tda19988_get_edid(device_t dev, uint8_t **edid, uint32_t *edid_len) 754 { 755 struct tda19988_softc *sc; 756 757 sc = device_get_softc(dev); 758 759 if (sc->sc_edid) { 760 *edid = sc->sc_edid; 761 *edid_len = sc->sc_edid_len; 762 } else 763 return (ENXIO); 764 765 return (0); 766 } 767 768 static int 769 tda19988_set_videomode(device_t dev, const struct videomode *mode) 770 { 771 struct tda19988_softc *sc; 772 773 sc = device_get_softc(dev); 774 775 tda19988_init_encoder(sc, mode); 776 777 return (0); 778 } 779 780 static device_method_t tda_methods[] = { 781 DEVMETHOD(device_probe, tda19988_probe), 782 DEVMETHOD(device_attach, tda19988_attach), 783 DEVMETHOD(device_detach, tda19988_detach), 784 785 /* HDMI methods */ 786 DEVMETHOD(hdmi_get_edid, tda19988_get_edid), 787 DEVMETHOD(hdmi_set_videomode, tda19988_set_videomode), 788 {0, 0}, 789 }; 790 791 static driver_t tda_driver = { 792 "tda", 793 tda_methods, 794 sizeof(struct tda19988_softc), 795 }; 796 797 DRIVER_MODULE(tda, iicbus, tda_driver, 0, 0); 798 MODULE_VERSION(tda, 1); 799 MODULE_DEPEND(tda, iicbus, 1, 1, 1);
Cache object: 07dd412c8534a1da9d3384814615c1ec
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