1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2017 Emmanuel Vadot <manu@freebsd.org>
5 *
6 * Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31
32 #ifndef _TI_DPLL_CLOCK_H_
33 #define _TI_DPLL_CLOCK_H_
34
35 #include <dev/extres/clk/clk.h>
36
37 /* Registers are described in AM335x TRM chapter 8.1.12.2.* */
38
39 /* Register offsets */
40 #define CM_CLKSEL_DPLL_PERIPH 0x49C
41
42 /* CM_IDLEST_DPLL_xxx */
43 #define ST_MN_BYPASS_MASK 0x0100
44 #define ST_MN_BYPASS_SHIFT 8
45 #define ST_DPLL_CLK_MASK 0x0001
46
47 /* CM_CLKMODE_DPLL_DPLL_EN feature flag */
48 #define LOW_POWER_STOP_MODE_FLAG 0x01
49 #define MN_BYPASS_MODE_FLAG 0x02
50 #define IDLE_BYPASS_LOW_POWER_MODE_FLAG 0x04
51 #define IDLE_BYPASS_FAST_RELOCK_MODE_FLAG 0x08
52 #define LOCK_MODE_FLAG 0x10
53
54 /* CM_CLKMODE_DPLL_xxx */
55 #define DPLL_EN_LOW_POWER_STOP_MODE 0x01
56 #define DPLL_EN_MN_BYPASS_MODE 0x04
57 #define DPLL_EN_IDLE_BYPASS_LOW_POWER_MODE 0x05
58 #define DPLL_EN_IDLE_BYPASS_FAST_RELOCK_MODE 0x06
59 #define DPLL_EN_LOCK_MODE 0x07
60
61 #define TI_CLK_FACTOR_ZERO_BASED 0x0002
62 #define TI_CLK_FACTOR_FIXED 0x0008
63 #define TI_CLK_FACTOR_MIN_VALUE 0x0020
64 #define TI_CLK_FACTOR_MAX_VALUE 0x0040
65
66 /* Based on aw_clk_factor sys/arm/allwinner/clkng/aw_clk.h */
67 struct ti_clk_factor {
68 uint32_t shift; /* Shift bits for the factor */
69 uint32_t mask; /* Mask to get the factor */
70 uint32_t width; /* Number of bits for the factor */
71 uint32_t value; /* Fixed value */
72
73 uint32_t min_value;
74 uint32_t max_value;
75
76 uint32_t flags; /* Flags */
77 };
78
79 struct ti_clk_dpll_def {
80 struct clknode_init_def clkdef;
81
82 uint32_t ti_clkmode_offset; /* control */
83 uint8_t ti_clkmode_flags;
84
85 uint32_t ti_idlest_offset;
86
87 uint32_t ti_clksel_offset; /* mult-div1 */
88 struct ti_clk_factor ti_clksel_mult;
89 struct ti_clk_factor ti_clksel_div;
90
91 uint32_t ti_autoidle_offset;
92 };
93
94 int ti_clknode_dpll_register(struct clkdom *clkdom, struct ti_clk_dpll_def *clkdef);
95
96 #endif /* _TI_DPLL_CLOCK_H_ */
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