FreeBSD/Linux Kernel Cross Reference
sys/arm/ti/ti_adc.c
1 /*-
2 * Copyright 2014 Luiz Otavio O Souza <loos@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include "opt_evdev.h"
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35
36 #include <sys/conf.h>
37 #include <sys/kernel.h>
38 #include <sys/limits.h>
39 #include <sys/lock.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/condvar.h>
43 #include <sys/resource.h>
44 #include <sys/rman.h>
45 #include <sys/sysctl.h>
46 #include <sys/selinfo.h>
47 #include <sys/poll.h>
48 #include <sys/uio.h>
49
50 #include <machine/bus.h>
51
52 #include <dev/ofw/openfirm.h>
53 #include <dev/ofw/ofw_bus.h>
54 #include <dev/ofw/ofw_bus_subr.h>
55
56 #ifdef EVDEV_SUPPORT
57 #include <dev/evdev/input.h>
58 #include <dev/evdev/evdev.h>
59 #endif
60
61 #include <arm/ti/ti_sysc.h>
62 #include <arm/ti/ti_adcreg.h>
63 #include <arm/ti/ti_adcvar.h>
64
65 #undef DEBUG_TSC
66
67 #define DEFAULT_CHARGE_DELAY 0x400
68 #define STEPDLY_OPEN 0x98
69
70 #define ORDER_XP 0
71 #define ORDER_XN 1
72 #define ORDER_YP 2
73 #define ORDER_YN 3
74
75 /* Define our 8 steps, one for each input channel. */
76 static struct ti_adc_input ti_adc_inputs[TI_ADC_NPINS] = {
77 { .stepconfig = ADC_STEPCFG(1), .stepdelay = ADC_STEPDLY(1) },
78 { .stepconfig = ADC_STEPCFG(2), .stepdelay = ADC_STEPDLY(2) },
79 { .stepconfig = ADC_STEPCFG(3), .stepdelay = ADC_STEPDLY(3) },
80 { .stepconfig = ADC_STEPCFG(4), .stepdelay = ADC_STEPDLY(4) },
81 { .stepconfig = ADC_STEPCFG(5), .stepdelay = ADC_STEPDLY(5) },
82 { .stepconfig = ADC_STEPCFG(6), .stepdelay = ADC_STEPDLY(6) },
83 { .stepconfig = ADC_STEPCFG(7), .stepdelay = ADC_STEPDLY(7) },
84 { .stepconfig = ADC_STEPCFG(8), .stepdelay = ADC_STEPDLY(8) },
85 };
86
87 static int ti_adc_samples[5] = { 0, 2, 4, 8, 16 };
88
89 static int ti_adc_detach(device_t dev);
90
91 #ifdef EVDEV_SUPPORT
92 static void
93 ti_adc_ev_report(struct ti_adc_softc *sc)
94 {
95
96 evdev_push_event(sc->sc_evdev, EV_ABS, ABS_X, sc->sc_x);
97 evdev_push_event(sc->sc_evdev, EV_ABS, ABS_Y, sc->sc_y);
98 evdev_push_event(sc->sc_evdev, EV_KEY, BTN_TOUCH, sc->sc_pen_down);
99 evdev_sync(sc->sc_evdev);
100 }
101 #endif /* EVDEV */
102
103 static void
104 ti_adc_enable(struct ti_adc_softc *sc)
105 {
106 uint32_t reg;
107
108 TI_ADC_LOCK_ASSERT(sc);
109
110 if (sc->sc_last_state == 1)
111 return;
112
113 /* Enable the FIFO0 threshold and the end of sequence interrupt. */
114 ADC_WRITE4(sc, ADC_IRQENABLE_SET,
115 ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ);
116
117 reg = ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID;
118 if (sc->sc_tsc_wires > 0) {
119 reg |= ADC_CTRL_TSC_ENABLE;
120 switch (sc->sc_tsc_wires) {
121 case 4:
122 reg |= ADC_CTRL_TSC_4WIRE;
123 break;
124 case 5:
125 reg |= ADC_CTRL_TSC_5WIRE;
126 break;
127 case 8:
128 reg |= ADC_CTRL_TSC_8WIRE;
129 break;
130 default:
131 break;
132 }
133 }
134 reg |= ADC_CTRL_ENABLE;
135 /* Enable the ADC. Run thru enabled steps, start the conversions. */
136 ADC_WRITE4(sc, ADC_CTRL, reg);
137
138 sc->sc_last_state = 1;
139 }
140
141 static void
142 ti_adc_disable(struct ti_adc_softc *sc)
143 {
144 int count;
145
146 TI_ADC_LOCK_ASSERT(sc);
147
148 if (sc->sc_last_state == 0)
149 return;
150
151 /* Disable all the enabled steps. */
152 ADC_WRITE4(sc, ADC_STEPENABLE, 0);
153
154 /* Disable the ADC. */
155 ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) & ~ADC_CTRL_ENABLE);
156
157 /* Disable the FIFO0 threshold and the end of sequence interrupt. */
158 ADC_WRITE4(sc, ADC_IRQENABLE_CLR,
159 ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ);
160
161 /* ACK any pending interrupt. */
162 ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS));
163
164 /* Drain the FIFO data. */
165 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
166 while (count > 0) {
167 (void)ADC_READ4(sc, ADC_FIFO0DATA);
168 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
169 }
170
171 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
172 while (count > 0) {
173 (void)ADC_READ4(sc, ADC_FIFO1DATA);
174 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
175 }
176
177 sc->sc_last_state = 0;
178 }
179
180 static int
181 ti_adc_setup(struct ti_adc_softc *sc)
182 {
183 int ain, i;
184 uint32_t enabled;
185
186 TI_ADC_LOCK_ASSERT(sc);
187
188 /* Check for enabled inputs. */
189 enabled = sc->sc_tsc_enabled;
190 for (i = 0; i < sc->sc_adc_nchannels; i++) {
191 ain = sc->sc_adc_channels[i];
192 if (ti_adc_inputs[ain].enable)
193 enabled |= (1U << (ain + 1));
194 }
195
196 /* Set the ADC global status. */
197 if (enabled != 0) {
198 ti_adc_enable(sc);
199 /* Update the enabled steps. */
200 if (enabled != ADC_READ4(sc, ADC_STEPENABLE))
201 ADC_WRITE4(sc, ADC_STEPENABLE, enabled);
202 } else
203 ti_adc_disable(sc);
204
205 return (0);
206 }
207
208 static void
209 ti_adc_input_setup(struct ti_adc_softc *sc, int32_t ain)
210 {
211 struct ti_adc_input *input;
212 uint32_t reg, val;
213
214 TI_ADC_LOCK_ASSERT(sc);
215
216 input = &ti_adc_inputs[ain];
217 reg = input->stepconfig;
218 val = ADC_READ4(sc, reg);
219
220 /* Set single ended operation. */
221 val &= ~ADC_STEP_DIFF_CNTRL;
222
223 /* Set the negative voltage reference. */
224 val &= ~ADC_STEP_RFM_MSK;
225
226 /* Set the positive voltage reference. */
227 val &= ~ADC_STEP_RFP_MSK;
228
229 /* Set the samples average. */
230 val &= ~ADC_STEP_AVG_MSK;
231 val |= input->samples << ADC_STEP_AVG_SHIFT;
232
233 /* Select the desired input. */
234 val &= ~ADC_STEP_INP_MSK;
235 val |= ain << ADC_STEP_INP_SHIFT;
236
237 /* Set the ADC to one-shot mode. */
238 val &= ~ADC_STEP_MODE_MSK;
239
240 ADC_WRITE4(sc, reg, val);
241 }
242
243 static void
244 ti_adc_reset(struct ti_adc_softc *sc)
245 {
246 int ain, i;
247
248 TI_ADC_LOCK_ASSERT(sc);
249
250 /* Disable all the inputs. */
251 for (i = 0; i < sc->sc_adc_nchannels; i++) {
252 ain = sc->sc_adc_channels[i];
253 ti_adc_inputs[ain].enable = 0;
254 }
255 }
256
257 static int
258 ti_adc_clockdiv_proc(SYSCTL_HANDLER_ARGS)
259 {
260 int error, reg;
261 struct ti_adc_softc *sc;
262
263 sc = (struct ti_adc_softc *)arg1;
264
265 TI_ADC_LOCK(sc);
266 reg = (int)ADC_READ4(sc, ADC_CLKDIV) + 1;
267 TI_ADC_UNLOCK(sc);
268
269 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
270 if (error != 0 || req->newptr == NULL)
271 return (error);
272
273 /*
274 * The actual written value is the prescaler setting - 1.
275 * Enforce a minimum value of 10 (i.e. 9) which limits the maximum
276 * ADC clock to ~2.4Mhz (CLK_M_OSC / 10).
277 */
278 reg--;
279 if (reg < 9)
280 reg = 9;
281 if (reg > USHRT_MAX)
282 reg = USHRT_MAX;
283
284 TI_ADC_LOCK(sc);
285 /* Disable the ADC. */
286 ti_adc_disable(sc);
287 /* Update the ADC prescaler setting. */
288 ADC_WRITE4(sc, ADC_CLKDIV, reg);
289 /* Enable the ADC again. */
290 ti_adc_setup(sc);
291 TI_ADC_UNLOCK(sc);
292
293 return (0);
294 }
295
296 static int
297 ti_adc_enable_proc(SYSCTL_HANDLER_ARGS)
298 {
299 int error;
300 int32_t enable;
301 struct ti_adc_softc *sc;
302 struct ti_adc_input *input;
303
304 input = (struct ti_adc_input *)arg1;
305 sc = input->sc;
306
307 enable = input->enable;
308 error = sysctl_handle_int(oidp, &enable, sizeof(enable),
309 req);
310 if (error != 0 || req->newptr == NULL)
311 return (error);
312
313 if (enable)
314 enable = 1;
315
316 TI_ADC_LOCK(sc);
317 /* Setup the ADC as needed. */
318 if (input->enable != enable) {
319 input->enable = enable;
320 ti_adc_setup(sc);
321 if (input->enable == 0)
322 input->value = 0;
323 }
324 TI_ADC_UNLOCK(sc);
325
326 return (0);
327 }
328
329 static int
330 ti_adc_open_delay_proc(SYSCTL_HANDLER_ARGS)
331 {
332 int error, reg;
333 struct ti_adc_softc *sc;
334 struct ti_adc_input *input;
335
336 input = (struct ti_adc_input *)arg1;
337 sc = input->sc;
338
339 TI_ADC_LOCK(sc);
340 reg = (int)ADC_READ4(sc, input->stepdelay) & ADC_STEP_OPEN_DELAY;
341 TI_ADC_UNLOCK(sc);
342
343 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
344 if (error != 0 || req->newptr == NULL)
345 return (error);
346
347 if (reg < 0)
348 reg = 0;
349
350 TI_ADC_LOCK(sc);
351 ADC_WRITE4(sc, input->stepdelay, reg & ADC_STEP_OPEN_DELAY);
352 TI_ADC_UNLOCK(sc);
353
354 return (0);
355 }
356
357 static int
358 ti_adc_samples_avg_proc(SYSCTL_HANDLER_ARGS)
359 {
360 int error, samples, i;
361 struct ti_adc_softc *sc;
362 struct ti_adc_input *input;
363
364 input = (struct ti_adc_input *)arg1;
365 sc = input->sc;
366
367 if (input->samples > nitems(ti_adc_samples))
368 input->samples = nitems(ti_adc_samples);
369 samples = ti_adc_samples[input->samples];
370
371 error = sysctl_handle_int(oidp, &samples, 0, req);
372 if (error != 0 || req->newptr == NULL)
373 return (error);
374
375 TI_ADC_LOCK(sc);
376 if (samples != ti_adc_samples[input->samples]) {
377 input->samples = 0;
378 for (i = 0; i < nitems(ti_adc_samples); i++)
379 if (samples >= ti_adc_samples[i])
380 input->samples = i;
381 ti_adc_input_setup(sc, input->input);
382 }
383 TI_ADC_UNLOCK(sc);
384
385 return (error);
386 }
387
388 static void
389 ti_adc_read_data(struct ti_adc_softc *sc)
390 {
391 int count, ain;
392 struct ti_adc_input *input;
393 uint32_t data;
394
395 TI_ADC_LOCK_ASSERT(sc);
396
397 /* Read the available data. */
398 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
399 while (count > 0) {
400 data = ADC_READ4(sc, ADC_FIFO0DATA);
401 ain = (data & ADC_FIFO_STEP_ID_MSK) >> ADC_FIFO_STEP_ID_SHIFT;
402 input = &ti_adc_inputs[ain];
403 if (input->enable == 0)
404 input->value = 0;
405 else
406 input->value = (int32_t)(data & ADC_FIFO_DATA_MSK);
407 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
408 }
409 }
410
411 static int
412 cmp_values(const void *a, const void *b)
413 {
414 const uint32_t *v1, *v2;
415 v1 = a;
416 v2 = b;
417 if (*v1 < *v2)
418 return -1;
419 if (*v1 > *v2)
420 return 1;
421
422 return (0);
423 }
424
425 static void
426 ti_adc_tsc_read_data(struct ti_adc_softc *sc)
427 {
428 int count;
429 uint32_t data[16];
430 uint32_t x, y;
431 int i, start, end;
432
433 TI_ADC_LOCK_ASSERT(sc);
434
435 /* Read the available data. */
436 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
437 if (count == 0)
438 return;
439
440 i = 0;
441 while (count > 0) {
442 data[i++] = ADC_READ4(sc, ADC_FIFO1DATA) & ADC_FIFO_DATA_MSK;
443 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
444 }
445
446 if (sc->sc_coord_readouts > 3) {
447 start = 1;
448 end = sc->sc_coord_readouts - 1;
449 qsort(data, sc->sc_coord_readouts,
450 sizeof(data[0]), &cmp_values);
451 qsort(&data[sc->sc_coord_readouts + 2],
452 sc->sc_coord_readouts,
453 sizeof(data[0]), &cmp_values);
454 }
455 else {
456 start = 0;
457 end = sc->sc_coord_readouts;
458 }
459
460 x = y = 0;
461 for (i = start; i < end; i++)
462 y += data[i];
463 y /= (end - start);
464
465 for (i = sc->sc_coord_readouts + 2 + start; i < sc->sc_coord_readouts + 2 + end; i++)
466 x += data[i];
467 x /= (end - start);
468
469 #ifdef DEBUG_TSC
470 device_printf(sc->sc_dev, "touchscreen x: %d, y: %d\n", x, y);
471 #endif
472
473 #ifdef EVDEV_SUPPORT
474 if ((sc->sc_x != x) || (sc->sc_y != y)) {
475 sc->sc_x = x;
476 sc->sc_y = y;
477 ti_adc_ev_report(sc);
478 }
479 #endif
480 }
481
482 static void
483 ti_adc_intr_locked(struct ti_adc_softc *sc, uint32_t status)
484 {
485 /* Read the available data. */
486 if (status & ADC_IRQ_FIFO0_THRES)
487 ti_adc_read_data(sc);
488 }
489
490 static void
491 ti_adc_tsc_intr_locked(struct ti_adc_softc *sc, uint32_t status)
492 {
493 /* Read the available data. */
494 if (status & ADC_IRQ_FIFO1_THRES)
495 ti_adc_tsc_read_data(sc);
496
497 }
498
499 static void
500 ti_adc_intr(void *arg)
501 {
502 struct ti_adc_softc *sc;
503 uint32_t status, rawstatus;
504
505 sc = (struct ti_adc_softc *)arg;
506
507 TI_ADC_LOCK(sc);
508
509 rawstatus = ADC_READ4(sc, ADC_IRQSTATUS_RAW);
510 status = ADC_READ4(sc, ADC_IRQSTATUS);
511
512 if (rawstatus & ADC_IRQ_HW_PEN_ASYNC) {
513 sc->sc_pen_down = 1;
514 status |= ADC_IRQ_HW_PEN_ASYNC;
515 ADC_WRITE4(sc, ADC_IRQENABLE_CLR,
516 ADC_IRQ_HW_PEN_ASYNC);
517 #ifdef EVDEV_SUPPORT
518 ti_adc_ev_report(sc);
519 #endif
520 }
521
522 if (rawstatus & ADC_IRQ_PEN_UP) {
523 sc->sc_pen_down = 0;
524 status |= ADC_IRQ_PEN_UP;
525 #ifdef EVDEV_SUPPORT
526 ti_adc_ev_report(sc);
527 #endif
528 }
529
530 if (status & ADC_IRQ_FIFO0_THRES)
531 ti_adc_intr_locked(sc, status);
532
533 if (status & ADC_IRQ_FIFO1_THRES)
534 ti_adc_tsc_intr_locked(sc, status);
535
536 if (status) {
537 /* ACK the interrupt. */
538 ADC_WRITE4(sc, ADC_IRQSTATUS, status);
539 }
540
541 /* Start the next conversion ? */
542 if (status & ADC_IRQ_END_OF_SEQ)
543 ti_adc_setup(sc);
544
545 TI_ADC_UNLOCK(sc);
546 }
547
548 static void
549 ti_adc_sysctl_init(struct ti_adc_softc *sc)
550 {
551 char pinbuf[3];
552 struct sysctl_ctx_list *ctx;
553 struct sysctl_oid *tree_node, *inp_node, *inpN_node;
554 struct sysctl_oid_list *tree, *inp_tree, *inpN_tree;
555 int ain, i;
556
557 /*
558 * Add per-pin sysctl tree/handlers.
559 */
560 ctx = device_get_sysctl_ctx(sc->sc_dev);
561 tree_node = device_get_sysctl_tree(sc->sc_dev);
562 tree = SYSCTL_CHILDREN(tree_node);
563 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clockdiv",
564 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, sc, 0,
565 ti_adc_clockdiv_proc, "IU", "ADC clock prescaler");
566 inp_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "ain",
567 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ADC inputs");
568 inp_tree = SYSCTL_CHILDREN(inp_node);
569
570 for (i = 0; i < sc->sc_adc_nchannels; i++) {
571 ain = sc->sc_adc_channels[i];
572
573 snprintf(pinbuf, sizeof(pinbuf), "%d", ain);
574 inpN_node = SYSCTL_ADD_NODE(ctx, inp_tree, OID_AUTO, pinbuf,
575 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ADC input");
576 inpN_tree = SYSCTL_CHILDREN(inpN_node);
577
578 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "enable",
579 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
580 &ti_adc_inputs[ain], 0,
581 ti_adc_enable_proc, "IU", "Enable ADC input");
582 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "open_delay",
583 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
584 &ti_adc_inputs[ain], 0,
585 ti_adc_open_delay_proc, "IU", "ADC open delay");
586 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "samples_avg",
587 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
588 &ti_adc_inputs[ain], 0,
589 ti_adc_samples_avg_proc, "IU", "ADC samples average");
590 SYSCTL_ADD_INT(ctx, inpN_tree, OID_AUTO, "input",
591 CTLFLAG_RD, &ti_adc_inputs[ain].value, 0,
592 "Converted raw value for the ADC input");
593 }
594 }
595
596 static void
597 ti_adc_inputs_init(struct ti_adc_softc *sc)
598 {
599 int ain, i;
600 struct ti_adc_input *input;
601
602 TI_ADC_LOCK(sc);
603 for (i = 0; i < sc->sc_adc_nchannels; i++) {
604 ain = sc->sc_adc_channels[i];
605 input = &ti_adc_inputs[ain];
606 input->sc = sc;
607 input->input = ain;
608 input->value = 0;
609 input->enable = 0;
610 input->samples = 0;
611 ti_adc_input_setup(sc, ain);
612 }
613 TI_ADC_UNLOCK(sc);
614 }
615
616 static void
617 ti_adc_tsc_init(struct ti_adc_softc *sc)
618 {
619 int i, start_step, end_step;
620 uint32_t stepconfig, val;
621
622 TI_ADC_LOCK(sc);
623
624 /* X coordinates */
625 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) |
626 ADC_STEP_MODE_HW_ONESHOT | sc->sc_xp_bit;
627 if (sc->sc_tsc_wires == 4)
628 stepconfig |= ADC_STEP_INP(sc->sc_yp_inp) | sc->sc_xn_bit;
629 else if (sc->sc_tsc_wires == 5)
630 stepconfig |= ADC_STEP_INP(4) |
631 sc->sc_xn_bit | sc->sc_yn_bit | sc->sc_yp_bit;
632 else if (sc->sc_tsc_wires == 8)
633 stepconfig |= ADC_STEP_INP(sc->sc_yp_inp) | sc->sc_xn_bit;
634
635 start_step = ADC_STEPS - sc->sc_coord_readouts + 1;
636 end_step = start_step + sc->sc_coord_readouts - 1;
637 for (i = start_step; i <= end_step; i++) {
638 ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig);
639 ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN);
640 }
641
642 /* Y coordinates */
643 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) |
644 ADC_STEP_MODE_HW_ONESHOT | sc->sc_yn_bit |
645 ADC_STEP_INM(8);
646 if (sc->sc_tsc_wires == 4)
647 stepconfig |= ADC_STEP_INP(sc->sc_xp_inp) | sc->sc_yp_bit;
648 else if (sc->sc_tsc_wires == 5)
649 stepconfig |= ADC_STEP_INP(4) |
650 sc->sc_xp_bit | sc->sc_xn_bit | sc->sc_yp_bit;
651 else if (sc->sc_tsc_wires == 8)
652 stepconfig |= ADC_STEP_INP(sc->sc_xp_inp) | sc->sc_yp_bit;
653
654 start_step = ADC_STEPS - (sc->sc_coord_readouts*2 + 2) + 1;
655 end_step = start_step + sc->sc_coord_readouts - 1;
656 for (i = start_step; i <= end_step; i++) {
657 ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig);
658 ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN);
659 }
660
661 /* Charge config */
662 val = ADC_READ4(sc, ADC_IDLECONFIG);
663 ADC_WRITE4(sc, ADC_TC_CHARGE_STEPCONFIG, val);
664 ADC_WRITE4(sc, ADC_TC_CHARGE_DELAY, sc->sc_charge_delay);
665
666 /* 2 steps for Z */
667 start_step = ADC_STEPS - (sc->sc_coord_readouts + 2) + 1;
668 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) |
669 ADC_STEP_MODE_HW_ONESHOT | sc->sc_yp_bit |
670 sc->sc_xn_bit | ADC_STEP_INP(sc->sc_xp_inp) |
671 ADC_STEP_INM(8);
672 ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig);
673 ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN);
674 start_step++;
675 stepconfig |= ADC_STEP_INP(sc->sc_yn_inp);
676 ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig);
677 ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN);
678
679 ADC_WRITE4(sc, ADC_FIFO1THRESHOLD, (sc->sc_coord_readouts*2 + 2) - 1);
680
681 sc->sc_tsc_enabled = 1;
682 start_step = ADC_STEPS - (sc->sc_coord_readouts*2 + 2) + 1;
683 end_step = ADC_STEPS;
684 for (i = start_step; i <= end_step; i++) {
685 sc->sc_tsc_enabled |= (1 << i);
686 }
687
688 TI_ADC_UNLOCK(sc);
689 }
690
691 static void
692 ti_adc_idlestep_init(struct ti_adc_softc *sc)
693 {
694 uint32_t val;
695
696 val = ADC_STEP_YNN_SW | ADC_STEP_INM(8) | ADC_STEP_INP(8) | ADC_STEP_YPN_SW;
697
698 ADC_WRITE4(sc, ADC_IDLECONFIG, val);
699 }
700
701 static int
702 ti_adc_config_wires(struct ti_adc_softc *sc, int *wire_configs, int nwire_configs)
703 {
704 int i;
705 int wire, ai;
706
707 for (i = 0; i < nwire_configs; i++) {
708 wire = wire_configs[i] & 0xf;
709 ai = (wire_configs[i] >> 4) & 0xf;
710 switch (wire) {
711 case ORDER_XP:
712 sc->sc_xp_bit = ADC_STEP_XPP_SW;
713 sc->sc_xp_inp = ai;
714 break;
715 case ORDER_XN:
716 sc->sc_xn_bit = ADC_STEP_XNN_SW;
717 sc->sc_xn_inp = ai;
718 break;
719 case ORDER_YP:
720 sc->sc_yp_bit = ADC_STEP_YPP_SW;
721 sc->sc_yp_inp = ai;
722 break;
723 case ORDER_YN:
724 sc->sc_yn_bit = ADC_STEP_YNN_SW;
725 sc->sc_yn_inp = ai;
726 break;
727 default:
728 device_printf(sc->sc_dev, "Invalid wire config\n");
729 return (-1);
730 }
731 }
732 return (0);
733 }
734
735 static int
736 ti_adc_probe(device_t dev)
737 {
738
739 if (!ofw_bus_is_compatible(dev, "ti,am3359-tscadc"))
740 return (ENXIO);
741 device_set_desc(dev, "TI ADC controller");
742
743 return (BUS_PROBE_DEFAULT);
744 }
745
746 static int
747 ti_adc_attach(device_t dev)
748 {
749 int err, rid, i;
750 struct ti_adc_softc *sc;
751 uint32_t rev, reg;
752 phandle_t node, child;
753 pcell_t cell;
754 int *channels;
755 int nwire_configs;
756 int *wire_configs;
757
758 sc = device_get_softc(dev);
759 sc->sc_dev = dev;
760
761 node = ofw_bus_get_node(dev);
762
763 sc->sc_tsc_wires = 0;
764 sc->sc_coord_readouts = 1;
765 sc->sc_x_plate_resistance = 0;
766 sc->sc_charge_delay = DEFAULT_CHARGE_DELAY;
767 /* Read "tsc" node properties */
768 child = ofw_bus_find_child(node, "tsc");
769 if (child != 0 && OF_hasprop(child, "ti,wires")) {
770 if ((OF_getencprop(child, "ti,wires", &cell, sizeof(cell))) > 0)
771 sc->sc_tsc_wires = cell;
772 if ((OF_getencprop(child, "ti,coordinate-readouts", &cell,
773 sizeof(cell))) > 0)
774 sc->sc_coord_readouts = cell;
775 if ((OF_getencprop(child, "ti,x-plate-resistance", &cell,
776 sizeof(cell))) > 0)
777 sc->sc_x_plate_resistance = cell;
778 if ((OF_getencprop(child, "ti,charge-delay", &cell,
779 sizeof(cell))) > 0)
780 sc->sc_charge_delay = cell;
781 nwire_configs = OF_getencprop_alloc_multi(child,
782 "ti,wire-config", sizeof(*wire_configs),
783 (void **)&wire_configs);
784 if (nwire_configs != sc->sc_tsc_wires) {
785 device_printf(sc->sc_dev,
786 "invalid number of ti,wire-config: %d (should be %d)\n",
787 nwire_configs, sc->sc_tsc_wires);
788 OF_prop_free(wire_configs);
789 return (EINVAL);
790 }
791 err = ti_adc_config_wires(sc, wire_configs, nwire_configs);
792 OF_prop_free(wire_configs);
793 if (err)
794 return (EINVAL);
795 }
796
797 /* Read "adc" node properties */
798 child = ofw_bus_find_child(node, "adc");
799 if (child != 0) {
800 sc->sc_adc_nchannels = OF_getencprop_alloc_multi(child,
801 "ti,adc-channels", sizeof(*channels), (void **)&channels);
802 if (sc->sc_adc_nchannels > 0) {
803 for (i = 0; i < sc->sc_adc_nchannels; i++)
804 sc->sc_adc_channels[i] = channels[i];
805 OF_prop_free(channels);
806 }
807 }
808
809 /* Sanity check FDT data */
810 if (sc->sc_tsc_wires + sc->sc_adc_nchannels > TI_ADC_NPINS) {
811 device_printf(dev, "total number of channels (%d) is larger than %d\n",
812 sc->sc_tsc_wires + sc->sc_adc_nchannels, TI_ADC_NPINS);
813 return (ENXIO);
814 }
815
816 rid = 0;
817 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
818 RF_ACTIVE);
819 if (!sc->sc_mem_res) {
820 device_printf(dev, "cannot allocate memory window\n");
821 return (ENXIO);
822 }
823
824 /* Activate the ADC_TSC module. */
825 err = ti_sysc_clock_enable(device_get_parent(dev));
826 if (err)
827 return (err);
828
829 rid = 0;
830 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
831 RF_ACTIVE);
832 if (!sc->sc_irq_res) {
833 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
834 device_printf(dev, "cannot allocate interrupt\n");
835 return (ENXIO);
836 }
837
838 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
839 NULL, ti_adc_intr, sc, &sc->sc_intrhand) != 0) {
840 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
841 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
842 device_printf(dev, "Unable to setup the irq handler.\n");
843 return (ENXIO);
844 }
845
846 /* Check the ADC revision. */
847 rev = ADC_READ4(sc, ti_sysc_get_rev_address_offset_host(device_get_parent(dev)));
848 device_printf(dev,
849 "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n",
850 (rev & ADC_REV_SCHEME_MSK) >> ADC_REV_SCHEME_SHIFT,
851 (rev & ADC_REV_FUNC_MSK) >> ADC_REV_FUNC_SHIFT,
852 (rev & ADC_REV_RTL_MSK) >> ADC_REV_RTL_SHIFT,
853 (rev & ADC_REV_MAJOR_MSK) >> ADC_REV_MAJOR_SHIFT,
854 rev & ADC_REV_MINOR_MSK,
855 (rev & ADC_REV_CUSTOM_MSK) >> ADC_REV_CUSTOM_SHIFT);
856
857 reg = ADC_READ4(sc, ADC_CTRL);
858 ADC_WRITE4(sc, ADC_CTRL, reg | ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID);
859
860 /*
861 * Set the ADC prescaler to 2400 if touchscreen is not enabled
862 * and to 24 if it is. This sets the ADC clock to ~10Khz and
863 * ~1Mhz respectively (CLK_M_OSC / prescaler).
864 */
865 if (sc->sc_tsc_wires)
866 ADC_WRITE4(sc, ADC_CLKDIV, 24 - 1);
867 else
868 ADC_WRITE4(sc, ADC_CLKDIV, 2400 - 1);
869
870 TI_ADC_LOCK_INIT(sc);
871
872 ti_adc_idlestep_init(sc);
873 ti_adc_inputs_init(sc);
874 ti_adc_sysctl_init(sc);
875 ti_adc_tsc_init(sc);
876
877 TI_ADC_LOCK(sc);
878 ti_adc_setup(sc);
879 TI_ADC_UNLOCK(sc);
880
881 #ifdef EVDEV_SUPPORT
882 if (sc->sc_tsc_wires > 0) {
883 sc->sc_evdev = evdev_alloc();
884 evdev_set_name(sc->sc_evdev, device_get_desc(dev));
885 evdev_set_phys(sc->sc_evdev, device_get_nameunit(dev));
886 evdev_set_id(sc->sc_evdev, BUS_VIRTUAL, 0, 0, 0);
887 evdev_support_prop(sc->sc_evdev, INPUT_PROP_DIRECT);
888 evdev_support_event(sc->sc_evdev, EV_SYN);
889 evdev_support_event(sc->sc_evdev, EV_ABS);
890 evdev_support_event(sc->sc_evdev, EV_KEY);
891
892 evdev_support_abs(sc->sc_evdev, ABS_X, 0,
893 ADC_MAX_VALUE, 0, 0, 0);
894 evdev_support_abs(sc->sc_evdev, ABS_Y, 0,
895 ADC_MAX_VALUE, 0, 0, 0);
896
897 evdev_support_key(sc->sc_evdev, BTN_TOUCH);
898
899 err = evdev_register(sc->sc_evdev);
900 if (err) {
901 device_printf(dev,
902 "failed to register evdev: error=%d\n", err);
903 ti_adc_detach(dev);
904 return (err);
905 }
906
907 sc->sc_pen_down = 0;
908 sc->sc_x = -1;
909 sc->sc_y = -1;
910 }
911 #endif /* EVDEV */
912
913 return (0);
914 }
915
916 static int
917 ti_adc_detach(device_t dev)
918 {
919 struct ti_adc_softc *sc;
920
921 sc = device_get_softc(dev);
922
923 /* Turn off the ADC. */
924 TI_ADC_LOCK(sc);
925 ti_adc_reset(sc);
926 ti_adc_setup(sc);
927
928 #ifdef EVDEV_SUPPORT
929 evdev_free(sc->sc_evdev);
930 #endif
931
932 TI_ADC_UNLOCK(sc);
933
934 TI_ADC_LOCK_DESTROY(sc);
935
936 if (sc->sc_intrhand)
937 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
938 if (sc->sc_irq_res)
939 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
940 if (sc->sc_mem_res)
941 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
942
943 return (bus_generic_detach(dev));
944 }
945
946 static device_method_t ti_adc_methods[] = {
947 DEVMETHOD(device_probe, ti_adc_probe),
948 DEVMETHOD(device_attach, ti_adc_attach),
949 DEVMETHOD(device_detach, ti_adc_detach),
950
951 DEVMETHOD_END
952 };
953
954 static driver_t ti_adc_driver = {
955 "ti_adc",
956 ti_adc_methods,
957 sizeof(struct ti_adc_softc),
958 };
959
960 DRIVER_MODULE(ti_adc, simplebus, ti_adc_driver, 0, 0);
961 MODULE_VERSION(ti_adc, 1);
962 MODULE_DEPEND(ti_adc, simplebus, 1, 1, 1);
963 MODULE_DEPEND(ti_adc, ti_sysc, 1, 1, 1);
964 #ifdef EVDEV_SUPPORT
965 MODULE_DEPEND(ti_adc, evdev, 1, 1, 1);
966 #endif
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