FreeBSD/Linux Kernel Cross Reference
sys/arm/ti/ti_edma3.c
1 /*-
2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
3 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of authors nor the names of its contributors may be
15 * used to endorse or promote products derived from this software without
16 * specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD: releng/10.1/sys/arm/ti/ti_edma3.c 266152 2014-05-15 16:11:06Z ian $");
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/mbuf.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/socket.h>
43 #include <sys/sysctl.h>
44
45 #include <sys/sockio.h>
46 #include <sys/bus.h>
47 #include <machine/bus.h>
48 #include <sys/rman.h>
49 #include <machine/resource.h>
50
51 #include <dev/fdt/fdt_common.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
54
55 #include <arm/ti/ti_scm.h>
56 #include <arm/ti/ti_prcm.h>
57
58 #include <arm/ti/ti_edma3.h>
59
60 #define TI_EDMA3_NUM_TCS 3
61 #define TI_EDMA3_NUM_IRQS 3
62 #define TI_EDMA3_NUM_DMA_CHS 64
63 #define TI_EDMA3_NUM_QDMA_CHS 8
64
65 #define TI_EDMA3CC_PID 0x000
66 #define TI_EDMA3CC_DCHMAP(p) (0x100 + ((p)*4))
67 #define TI_EDMA3CC_DMAQNUM(n) (0x240 + ((n)*4))
68 #define TI_EDMA3CC_QDMAQNUM 0x260
69 #define TI_EDMA3CC_EMCR 0x308
70 #define TI_EDMA3CC_EMCRH 0x30C
71 #define TI_EDMA3CC_QEMCR 0x314
72 #define TI_EDMA3CC_CCERR 0x318
73 #define TI_EDMA3CC_CCERRCLR 0x31C
74 #define TI_EDMA3CC_DRAE(p) (0x340 + ((p)*8))
75 #define TI_EDMA3CC_DRAEH(p) (0x344 + ((p)*8))
76 #define TI_EDMA3CC_QRAE(p) (0x380 + ((p)*4))
77 #define TI_EDMA3CC_S_ESR(p) (0x2010 + ((p)*0x200))
78 #define TI_EDMA3CC_S_ESRH(p) (0x2014 + ((p)*0x200))
79 #define TI_EDMA3CC_S_SECR(p) (0x2040 + ((p)*0x200))
80 #define TI_EDMA3CC_S_SECRH(p) (0x2044 + ((p)*0x200))
81 #define TI_EDMA3CC_S_EESR(p) (0x2030 + ((p)*0x200))
82 #define TI_EDMA3CC_S_EESRH(p) (0x2034 + ((p)*0x200))
83 #define TI_EDMA3CC_S_IESR(p) (0x2060 + ((p)*0x200))
84 #define TI_EDMA3CC_S_IESRH(p) (0x2064 + ((p)*0x200))
85 #define TI_EDMA3CC_S_IPR(p) (0x2068 + ((p)*0x200))
86 #define TI_EDMA3CC_S_IPRH(p) (0x206C + ((p)*0x200))
87 #define TI_EDMA3CC_S_QEESR(p) (0x208C + ((p)*0x200))
88
89 #define TI_EDMA3CC_PARAM_OFFSET 0x4000
90 #define TI_EDMA3CC_OPT(p) (TI_EDMA3CC_PARAM_OFFSET + 0x0 + ((p)*0x20))
91
92 #define TI_EDMA3CC_DMAQNUM_SET(c,q) ((0x7 & (q)) << (((c) % 8) * 4))
93 #define TI_EDMA3CC_DMAQNUM_CLR(c) (~(0x7 << (((c) % 8) * 4)))
94 #define TI_EDMA3CC_QDMAQNUM_SET(c,q) ((0x7 & (q)) << ((c) * 4))
95 #define TI_EDMA3CC_QDMAQNUM_CLR(c) (~(0x7 << ((c) * 4)))
96
97 #define TI_EDMA3CC_OPT_TCC_CLR (~(0x3F000))
98 #define TI_EDMA3CC_OPT_TCC_SET(p) (((0x3F000 >> 12) & (p)) << 12)
99
100 struct ti_edma3_softc {
101 device_t sc_dev;
102 struct resource * mem_res[TI_EDMA3_NUM_TCS+1];
103 struct resource * irq_res[TI_EDMA3_NUM_IRQS];
104 void *ih_cookie[TI_EDMA3_NUM_IRQS];
105 };
106
107 static struct ti_edma3_softc *ti_edma3_sc = NULL;
108
109 static struct resource_spec ti_edma3_mem_spec[] = {
110 { SYS_RES_MEMORY, 0, RF_ACTIVE },
111 { SYS_RES_MEMORY, 1, RF_ACTIVE },
112 { SYS_RES_MEMORY, 2, RF_ACTIVE },
113 { SYS_RES_MEMORY, 3, RF_ACTIVE },
114 { -1, 0, 0 }
115 };
116 static struct resource_spec ti_edma3_irq_spec[] = {
117 { SYS_RES_IRQ, 0, RF_ACTIVE },
118 { SYS_RES_IRQ, 1, RF_ACTIVE },
119 { SYS_RES_IRQ, 2, RF_ACTIVE },
120 { -1, 0, 0 }
121 };
122
123 /* Read/Write macros */
124 #define ti_edma3_cc_rd_4(reg) bus_read_4(ti_edma3_sc->mem_res[0], reg)
125 #define ti_edma3_cc_wr_4(reg, val) bus_write_4(ti_edma3_sc->mem_res[0], reg, val)
126 #define ti_edma3_tc_rd_4(c, reg) bus_read_4(ti_edma3_sc->mem_res[c+1], reg)
127 #define ti_edma3_tc_wr_4(c, reg, val) bus_write_4(ti_edma3_sc->mem_res[c+1], reg, val)
128
129 static void ti_edma3_intr_comp(void *arg);
130 static void ti_edma3_intr_mperr(void *arg);
131 static void ti_edma3_intr_err(void *arg);
132
133 static struct {
134 driver_intr_t *handler;
135 char * description;
136 } ti_edma3_intrs[TI_EDMA3_NUM_IRQS] = {
137 { ti_edma3_intr_comp, "EDMA Completion Interrupt" },
138 { ti_edma3_intr_mperr, "EDMA Memory Protection Error Interrupt" },
139 { ti_edma3_intr_err, "EDMA Error Interrupt" },
140 };
141
142 static int
143 ti_edma3_probe(device_t dev)
144 {
145
146 if (!ofw_bus_status_okay(dev))
147 return (ENXIO);
148
149 if (!ofw_bus_is_compatible(dev, "ti,edma3"))
150 return (ENXIO);
151
152 device_set_desc(dev, "TI EDMA Controller");
153 return (0);
154 }
155
156 static int
157 ti_edma3_attach(device_t dev)
158 {
159 struct ti_edma3_softc *sc = device_get_softc(dev);
160 uint32_t reg;
161 int err;
162 int i;
163
164 if (ti_edma3_sc)
165 return (ENXIO);
166
167 ti_edma3_sc = sc;
168 sc->sc_dev = dev;
169
170 /* Request the memory resources */
171 err = bus_alloc_resources(dev, ti_edma3_mem_spec, sc->mem_res);
172 if (err) {
173 device_printf(dev, "Error: could not allocate mem resources\n");
174 return (ENXIO);
175 }
176
177 /* Request the IRQ resources */
178 err = bus_alloc_resources(dev, ti_edma3_irq_spec, sc->irq_res);
179 if (err) {
180 device_printf(dev, "Error: could not allocate irq resources\n");
181 return (ENXIO);
182 }
183
184 /* Enable Channel Controller */
185 ti_prcm_clk_enable(EDMA_TPCC_CLK);
186
187 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_PID);
188
189 device_printf(dev, "EDMA revision %08x\n", reg);
190
191
192 /* Attach interrupt handlers */
193 for (i = 0; i < TI_EDMA3_NUM_IRQS; ++i) {
194 err = bus_setup_intr(dev, sc->irq_res[i], INTR_TYPE_MISC |
195 INTR_MPSAFE, NULL, *ti_edma3_intrs[i].handler,
196 sc, &sc->ih_cookie[i]);
197 if (err) {
198 device_printf(dev, "could not setup %s\n",
199 ti_edma3_intrs[i].description);
200 return (err);
201 }
202 }
203
204 return (0);
205 }
206
207 static device_method_t ti_edma3_methods[] = {
208 DEVMETHOD(device_probe, ti_edma3_probe),
209 DEVMETHOD(device_attach, ti_edma3_attach),
210 {0, 0},
211 };
212
213 static driver_t ti_edma3_driver = {
214 "ti_edma3",
215 ti_edma3_methods,
216 sizeof(struct ti_edma3_softc),
217 };
218 static devclass_t ti_edma3_devclass;
219
220 DRIVER_MODULE(ti_edma3, simplebus, ti_edma3_driver, ti_edma3_devclass, 0, 0);
221 MODULE_DEPEND(ti_edma3, ti_prcm, 1, 1, 1);
222
223 static void
224 ti_edma3_intr_comp(void *arg)
225 {
226 printf("%s: unimplemented\n", __func__);
227 }
228
229 static void
230 ti_edma3_intr_mperr(void *arg)
231 {
232 printf("%s: unimplemented\n", __func__);
233 }
234
235 static void
236 ti_edma3_intr_err(void *arg)
237 {
238 printf("%s: unimplemented\n", __func__);
239 }
240
241 void
242 ti_edma3_init(unsigned int eqn)
243 {
244 uint32_t reg;
245 int i;
246
247 /* on AM335x Event queue 0 is always mapped to Transfer Controller 0,
248 * event queue 1 to TC2, etc. So we are asking PRCM to power on specific
249 * TC based on what event queue we need to initialize */
250 ti_prcm_clk_enable(EDMA_TPTC0_CLK + eqn);
251
252 /* Clear Event Missed Regs */
253 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCR, 0xFFFFFFFF);
254 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCRH, 0xFFFFFFFF);
255 ti_edma3_cc_wr_4(TI_EDMA3CC_QEMCR, 0xFFFFFFFF);
256
257 /* Clear Error Reg */
258 ti_edma3_cc_wr_4(TI_EDMA3CC_CCERRCLR, 0xFFFFFFFF);
259
260 /* Enable DMA channels 0-63 */
261 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), 0xFFFFFFFF);
262 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), 0xFFFFFFFF);
263
264 for (i = 0; i < 64; i++) {
265 ti_edma3_cc_wr_4(TI_EDMA3CC_DCHMAP(i), i<<5);
266 }
267
268 /* Initialize the DMA Queue Number Registers */
269 for (i = 0; i < TI_EDMA3_NUM_DMA_CHS; i++) {
270 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(i>>3));
271 reg &= TI_EDMA3CC_DMAQNUM_CLR(i);
272 reg |= TI_EDMA3CC_DMAQNUM_SET(i, eqn);
273 ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(i>>3), reg);
274 }
275
276 /* Enable the QDMA Region access for all channels */
277 ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), (1 << TI_EDMA3_NUM_QDMA_CHS) - 1);
278
279 /*Initialize QDMA Queue Number Registers */
280 for (i = 0; i < TI_EDMA3_NUM_QDMA_CHS; i++) {
281 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM);
282 reg &= TI_EDMA3CC_QDMAQNUM_CLR(i);
283 reg |= TI_EDMA3CC_QDMAQNUM_SET(i, eqn);
284 ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg);
285 }
286 }
287
288 #ifdef notyet
289 int
290 ti_edma3_enable_event_intr(unsigned int ch)
291 {
292 uint32_t reg;
293
294 if (ch >= TI_EDMA3_NUM_DMA_CHS)
295 return (EINVAL);
296
297 if (ch < 32) {
298 ti_edma3_cc_wr_4(TI_EDMA3CC_S_IESR(0), 1 << ch);
299 } else {
300 ti_edma3_cc_wr_4(TI_EDMA3CC_S_IESRH(0), 1 << (ch - 32));
301 }
302 return 0;
303 }
304 #endif
305
306 int
307 ti_edma3_request_dma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn)
308 {
309 uint32_t reg;
310
311 if (ch >= TI_EDMA3_NUM_DMA_CHS)
312 return (EINVAL);
313
314 /* Enable the DMA channel in the DRAE/DRAEH registers */
315 if (ch < 32) {
316 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAE(0));
317 reg |= (0x01 << ch);
318 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), reg);
319 } else {
320 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAEH(0));
321 reg |= (0x01 << (ch - 32));
322 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), reg);
323 }
324
325 /* Associate DMA Channel to Event Queue */
326 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(ch >> 3));
327 reg &= TI_EDMA3CC_DMAQNUM_CLR(ch);
328 reg |= TI_EDMA3CC_DMAQNUM_SET((ch), eqn);
329 ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(ch >> 3), reg);
330
331 /* Set TCC in corresponding PaRAM Entry */
332 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch));
333 reg &= TI_EDMA3CC_OPT_TCC_CLR;
334 reg |= TI_EDMA3CC_OPT_TCC_SET(ch);
335 ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg);
336
337 return 0;
338 }
339
340 int
341 ti_edma3_request_qdma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn)
342 {
343 uint32_t reg;
344
345 if (ch >= TI_EDMA3_NUM_DMA_CHS)
346 return (EINVAL);
347
348 /* Enable the QDMA channel in the QRAE registers */
349 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QRAE(0));
350 reg |= (0x01 << ch);
351 ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), reg);
352
353 /* Associate QDMA Channel to Event Queue */
354 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM);
355 reg |= TI_EDMA3CC_QDMAQNUM_SET(ch, eqn);
356 ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg);
357
358 /* Set TCC in corresponding PaRAM Entry */
359 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch));
360 reg &= TI_EDMA3CC_OPT_TCC_CLR;
361 reg |= TI_EDMA3CC_OPT_TCC_SET(ch);
362 ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg);
363
364 return 0;
365 }
366
367 int
368 ti_edma3_enable_transfer_manual(unsigned int ch)
369 {
370 if (ch >= TI_EDMA3_NUM_DMA_CHS)
371 return (EINVAL);
372
373 /* set corresponding bit in ESR/ESRH to set a event */
374 if (ch < 32) {
375 ti_edma3_cc_wr_4(TI_EDMA3CC_S_ESR(0), 1 << ch);
376 } else {
377 ti_edma3_cc_wr_4(TI_EDMA3CC_S_ESRH(0), 1 << (ch - 32));
378 }
379
380 return 0;
381 }
382
383 int
384 ti_edma3_enable_transfer_qdma(unsigned int ch)
385 {
386 if (ch >= TI_EDMA3_NUM_QDMA_CHS)
387 return (EINVAL);
388
389 /* set corresponding bit in QEESR to enable QDMA event */
390 ti_edma3_cc_wr_4(TI_EDMA3CC_S_QEESR(0), (1 << ch));
391
392 return 0;
393 }
394
395 int
396 ti_edma3_enable_transfer_event(unsigned int ch)
397 {
398 if (ch >= TI_EDMA3_NUM_DMA_CHS)
399 return (EINVAL);
400
401 /* Clear SECR(H) & EMCR(H) to clean any previous NULL request
402 * and set corresponding bit in EESR to enable DMA event */
403 if(ch < 32) {
404 ti_edma3_cc_wr_4(TI_EDMA3CC_S_SECR(0), (1 << ch));
405 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCR, (1 << ch));
406 ti_edma3_cc_wr_4(TI_EDMA3CC_S_EESR(0), (1 << ch));
407 } else {
408 ti_edma3_cc_wr_4(TI_EDMA3CC_S_SECRH(0), 1 << (ch - 32));
409 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCRH, 1 << (ch - 32));
410 ti_edma3_cc_wr_4(TI_EDMA3CC_S_EESRH(0), 1 << (ch - 32));
411 }
412
413 return 0;
414 }
415
416 void
417 ti_edma3_param_write(unsigned int ch, struct ti_edma3cc_param_set *prs)
418 {
419 bus_write_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch),
420 (uint32_t *) prs, 8);
421 }
422
423 void
424 ti_edma3_param_read(unsigned int ch, struct ti_edma3cc_param_set *prs)
425 {
426 bus_read_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch),
427 (uint32_t *) prs, 8);
428 }
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