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sys/arm/ti/ti_gpio.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 5 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /** 31 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code 32 * here uses 0-5. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include "opt_platform.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/proc.h> 47 #include <sys/rman.h> 48 #include <sys/lock.h> 49 #include <sys/mutex.h> 50 #include <sys/gpio.h> 51 #include <sys/interrupt.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 #include <machine/resource.h> 56 57 #include <arm/ti/ti_cpuid.h> 58 #include <arm/ti/ti_gpio.h> 59 #include <arm/ti/ti_scm.h> 60 #include <arm/ti/ti_sysc.h> 61 62 #include <dev/gpio/gpiobusvar.h> 63 #include <dev/ofw/openfirm.h> 64 #include <dev/ofw/ofw_bus.h> 65 #include <dev/ofw/ofw_bus_subr.h> 66 67 #include "gpio_if.h" 68 #include "ti_gpio_if.h" 69 #include "pic_if.h" 70 71 #if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X) 72 #error "Unknown SoC" 73 #endif 74 75 /* Register definitions */ 76 #define TI_GPIO_REVISION 0x0000 77 #define TI_GPIO_SYSCONFIG 0x0010 78 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024 79 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028 80 #define TI_GPIO_IRQSTATUS_0 0x002C /* writing a 0 has no effect */ 81 #define TI_GPIO_IRQSTATUS_1 0x0030 /* writing a 0 has no effect */ 82 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 /* writing a 0 has no effect */ 83 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 /* writing a 0 has no effect */ 84 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C /* writing a 0 has no effect */ 85 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 /* writing a 0 has no effect */ 86 #define TI_GPIO_IRQWAKEN_0 0x0044 87 #define TI_GPIO_IRQWAKEN_1 0x0048 88 #define TI_GPIO_SYSSTATUS 0x0114 89 #define TI_GPIO_IRQSTATUS1 0x0118 90 #define TI_GPIO_IRQENABLE1 0x011C 91 #define TI_GPIO_WAKEUPENABLE 0x0120 92 #define TI_GPIO_IRQSTATUS2 0x0128 93 #define TI_GPIO_IRQENABLE2 0x012C 94 #define TI_GPIO_CTRL 0x0130 95 #define TI_GPIO_OE 0x0134 96 #define TI_GPIO_DATAIN 0x0138 97 #define TI_GPIO_DATAOUT 0x013C 98 #define TI_GPIO_LEVELDETECT0 0x0140 /* RW register */ 99 #define TI_GPIO_LEVELDETECT1 0x0144 /* RW register */ 100 #define TI_GPIO_RISINGDETECT 0x0148 /* RW register */ 101 #define TI_GPIO_FALLINGDETECT 0x014C /* RW register */ 102 #define TI_GPIO_DEBOUNCENABLE 0x0150 103 #define TI_GPIO_DEBOUNCINGTIME 0x0154 104 #define TI_GPIO_CLEARWKUPENA 0x0180 105 #define TI_GPIO_SETWKUENA 0x0184 106 #define TI_GPIO_CLEARDATAOUT 0x0190 107 #define TI_GPIO_SETDATAOUT 0x0194 108 109 /* Other SoC Specific definitions */ 110 #define OMAP4_FIRST_GPIO_BANK 1 111 #define OMAP4_INTR_PER_BANK 1 112 #define OMAP4_GPIO_REV 0x50600801 113 #define AM335X_FIRST_GPIO_BANK 0 114 #define AM335X_INTR_PER_BANK 2 115 #define AM335X_GPIO_REV 0x50600801 116 #define PINS_PER_BANK 32 117 #define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK)) 118 119 #define OMAP4_GPIO1_REV 0x00000 120 #define OMAP4_GPIO2_REV 0x55000 121 #define OMAP4_GPIO3_REV 0x57000 122 #define OMAP4_GPIO4_REV 0x59000 123 #define OMAP4_GPIO5_REV 0x5b000 124 #define OMAP4_GPIO6_REV 0x5d000 125 126 #define AM335X_GPIO0_REV 0x07000 127 #define AM335X_GPIO1_REV 0x4C000 128 #define AM335X_GPIO2_REV 0xAC000 129 #define AM335X_GPIO3_REV 0xAE000 130 131 static int ti_gpio_intr(void *arg); 132 static int ti_gpio_detach(device_t); 133 134 static int ti_gpio_pic_attach(struct ti_gpio_softc *sc); 135 static int ti_gpio_pic_detach(struct ti_gpio_softc *sc); 136 137 static uint32_t 138 ti_gpio_rev(void) 139 { 140 switch(ti_chip()) { 141 #ifdef SOC_OMAP4 142 case CHIP_OMAP_4: 143 return (OMAP4_GPIO_REV); 144 #endif 145 #ifdef SOC_TI_AM335X 146 case CHIP_AM335X: 147 return (AM335X_GPIO_REV); 148 #endif 149 } 150 return (0); 151 } 152 153 /** 154 * Macros for driver mutex locking 155 */ 156 #define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 157 #define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 158 #define TI_GPIO_LOCK_INIT(_sc) \ 159 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 160 "ti_gpio", MTX_SPIN) 161 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 162 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 163 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 164 165 /** 166 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers 167 * @sc: GPIO device context 168 * @bank: The bank to read from 169 * @off: The offset of a register from the GPIO register address range 170 * 171 * 172 * RETURNS: 173 * 32-bit value read from the register. 174 */ 175 static inline uint32_t 176 ti_gpio_read_4(struct ti_gpio_softc *sc, bus_size_t off) 177 { 178 return (bus_read_4(sc->sc_mem_res, off)); 179 } 180 181 /** 182 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers 183 * @sc: GPIO device context 184 * @bank: The bank to write to 185 * @off: The offset of a register from the GPIO register address range 186 * @val: The value to write into the register 187 * 188 * RETURNS: 189 * nothing 190 */ 191 static inline void 192 ti_gpio_write_4(struct ti_gpio_softc *sc, bus_size_t off, 193 uint32_t val) 194 { 195 bus_write_4(sc->sc_mem_res, off, val); 196 } 197 198 static inline void 199 ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask) 200 { 201 202 /* We clear both set of registers. */ 203 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask); 204 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask); 205 } 206 207 static inline void 208 ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask) 209 { 210 211 /* 212 * On OMAP4 we unmask only the MPU interrupt and on AM335x we 213 * also activate only the first interrupt. 214 */ 215 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask); 216 } 217 218 static inline void 219 ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask) 220 { 221 222 /* 223 * Acknowledge the interrupt on both registers even if we use only 224 * the first one. 225 */ 226 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask); 227 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask); 228 } 229 230 static inline uint32_t 231 ti_gpio_intr_status(struct ti_gpio_softc *sc) 232 { 233 uint32_t reg; 234 235 /* Get the status from both registers. */ 236 reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0); 237 reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1); 238 239 return (reg); 240 } 241 242 static device_t 243 ti_gpio_get_bus(device_t dev) 244 { 245 struct ti_gpio_softc *sc; 246 247 sc = device_get_softc(dev); 248 249 return (sc->sc_busdev); 250 } 251 252 /** 253 * ti_gpio_pin_max - Returns the maximum number of GPIO pins 254 * @dev: gpio device handle 255 * @maxpin: pointer to a value that upon return will contain the maximum number 256 * of pins in the device. 257 * 258 * 259 * LOCKING: 260 * No locking required, returns static data. 261 * 262 * RETURNS: 263 * Returns 0 on success otherwise an error code 264 */ 265 static int 266 ti_gpio_pin_max(device_t dev, int *maxpin) 267 { 268 269 *maxpin = PINS_PER_BANK - 1; 270 271 return (0); 272 } 273 274 static int 275 ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin) 276 { 277 278 if (pin >= sc->sc_maxpin || sc->sc_mem_res == NULL) 279 return (EINVAL); 280 281 return (0); 282 } 283 284 /** 285 * ti_gpio_pin_getcaps - Gets the capabilities of a given pin 286 * @dev: gpio device handle 287 * @pin: the number of the pin 288 * @caps: pointer to a value that upon return will contain the capabilities 289 * 290 * Currently all pins have the same capability, notably: 291 * - GPIO_PIN_INPUT 292 * - GPIO_PIN_OUTPUT 293 * - GPIO_PIN_PULLUP 294 * - GPIO_PIN_PULLDOWN 295 * - GPIO_INTR_LEVEL_LOW 296 * - GPIO_INTR_LEVEL_HIGH 297 * - GPIO_INTR_EDGE_RISING 298 * - GPIO_INTR_EDGE_FALLING 299 * - GPIO_INTR_EDGE_BOTH 300 * 301 * LOCKING: 302 * No locking required, returns static data. 303 * 304 * RETURNS: 305 * Returns 0 on success otherwise an error code 306 */ 307 static int 308 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 309 { 310 struct ti_gpio_softc *sc; 311 312 sc = device_get_softc(dev); 313 if (ti_gpio_valid_pin(sc, pin) != 0) 314 return (EINVAL); 315 316 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP | 317 GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | 318 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | 319 GPIO_INTR_EDGE_BOTH); 320 321 return (0); 322 } 323 324 /** 325 * ti_gpio_pin_getflags - Gets the current flags of a given pin 326 * @dev: gpio device handle 327 * @pin: the number of the pin 328 * @flags: upon return will contain the current flags of the pin 329 * 330 * Reads the current flags of a given pin, here we actually read the H/W 331 * registers to determine the flags, rather than storing the value in the 332 * setflags call. 333 * 334 * LOCKING: 335 * Internally locks the context 336 * 337 * RETURNS: 338 * Returns 0 on success otherwise an error code 339 */ 340 static int 341 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 342 { 343 struct ti_gpio_softc *sc; 344 345 sc = device_get_softc(dev); 346 if (ti_gpio_valid_pin(sc, pin) != 0) 347 return (EINVAL); 348 349 /* Get the current pin state */ 350 TI_GPIO_LOCK(sc); 351 TI_GPIO_GET_FLAGS(dev, pin, flags); 352 TI_GPIO_UNLOCK(sc); 353 354 return (0); 355 } 356 357 /** 358 * ti_gpio_pin_getname - Gets the name of a given pin 359 * @dev: gpio device handle 360 * @pin: the number of the pin 361 * @name: buffer to put the name in 362 * 363 * The driver simply calls the pins gpio_n, where 'n' is obviously the number 364 * of the pin. 365 * 366 * LOCKING: 367 * No locking required, returns static data. 368 * 369 * RETURNS: 370 * Returns 0 on success otherwise an error code 371 */ 372 static int 373 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 374 { 375 struct ti_gpio_softc *sc; 376 377 sc = device_get_softc(dev); 378 if (ti_gpio_valid_pin(sc, pin) != 0) 379 return (EINVAL); 380 381 /* Set a very simple name */ 382 snprintf(name, GPIOMAXNAME, "gpio_%u", pin); 383 name[GPIOMAXNAME - 1] = '\0'; 384 385 return (0); 386 } 387 388 /** 389 * ti_gpio_pin_setflags - Sets the flags for a given pin 390 * @dev: gpio device handle 391 * @pin: the number of the pin 392 * @flags: the flags to set 393 * 394 * The flags of the pin correspond to things like input/output mode, pull-ups, 395 * pull-downs, etc. This driver doesn't support all flags, only the following: 396 * - GPIO_PIN_INPUT 397 * - GPIO_PIN_OUTPUT 398 * - GPIO_PIN_PULLUP 399 * - GPIO_PIN_PULLDOWN 400 * 401 * LOCKING: 402 * Internally locks the context 403 * 404 * RETURNS: 405 * Returns 0 on success otherwise an error code 406 */ 407 static int 408 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 409 { 410 struct ti_gpio_softc *sc; 411 uint32_t oe; 412 413 sc = device_get_softc(dev); 414 if (ti_gpio_valid_pin(sc, pin) != 0) 415 return (EINVAL); 416 417 /* Set the GPIO mode and state */ 418 TI_GPIO_LOCK(sc); 419 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) { 420 TI_GPIO_UNLOCK(sc); 421 return (EINVAL); 422 } 423 424 /* If configuring as an output set the "output enable" bit */ 425 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 426 if (flags & GPIO_PIN_INPUT) 427 oe |= TI_GPIO_MASK(pin); 428 else 429 oe &= ~TI_GPIO_MASK(pin); 430 ti_gpio_write_4(sc, TI_GPIO_OE, oe); 431 TI_GPIO_UNLOCK(sc); 432 433 return (0); 434 } 435 436 /** 437 * ti_gpio_pin_set - Sets the current level on a GPIO pin 438 * @dev: gpio device handle 439 * @pin: the number of the pin 440 * @value: non-zero value will drive the pin high, otherwise the pin is 441 * driven low. 442 * 443 * 444 * LOCKING: 445 * Internally locks the context 446 * 447 * RETURNS: 448 * Returns 0 on success otherwise a error code 449 */ 450 static int 451 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 452 { 453 struct ti_gpio_softc *sc; 454 uint32_t reg; 455 456 sc = device_get_softc(dev); 457 if (ti_gpio_valid_pin(sc, pin) != 0) 458 return (EINVAL); 459 460 TI_GPIO_LOCK(sc); 461 if (value == GPIO_PIN_LOW) 462 reg = TI_GPIO_CLEARDATAOUT; 463 else 464 reg = TI_GPIO_SETDATAOUT; 465 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 466 TI_GPIO_UNLOCK(sc); 467 468 return (0); 469 } 470 471 /** 472 * ti_gpio_pin_get - Gets the current level on a GPIO pin 473 * @dev: gpio device handle 474 * @pin: the number of the pin 475 * @value: pointer to a value that upond return will contain the pin value 476 * 477 * The pin must be configured as an input pin beforehand, otherwise this 478 * function will fail. 479 * 480 * LOCKING: 481 * Internally locks the context 482 * 483 * RETURNS: 484 * Returns 0 on success otherwise a error code 485 */ 486 static int 487 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 488 { 489 struct ti_gpio_softc *sc; 490 uint32_t oe, reg, val; 491 492 sc = device_get_softc(dev); 493 if (ti_gpio_valid_pin(sc, pin) != 0) 494 return (EINVAL); 495 496 /* 497 * Return data from output latch when set as output and from the 498 * input register otherwise. 499 */ 500 TI_GPIO_LOCK(sc); 501 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 502 if (oe & TI_GPIO_MASK(pin)) 503 reg = TI_GPIO_DATAIN; 504 else 505 reg = TI_GPIO_DATAOUT; 506 val = ti_gpio_read_4(sc, reg); 507 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0; 508 TI_GPIO_UNLOCK(sc); 509 510 return (0); 511 } 512 513 /** 514 * ti_gpio_pin_toggle - Toggles a given GPIO pin 515 * @dev: gpio device handle 516 * @pin: the number of the pin 517 * 518 * 519 * LOCKING: 520 * Internally locks the context 521 * 522 * RETURNS: 523 * Returns 0 on success otherwise a error code 524 */ 525 static int 526 ti_gpio_pin_toggle(device_t dev, uint32_t pin) 527 { 528 struct ti_gpio_softc *sc; 529 uint32_t reg, val; 530 531 sc = device_get_softc(dev); 532 if (ti_gpio_valid_pin(sc, pin) != 0) 533 return (EINVAL); 534 535 /* Toggle the pin */ 536 TI_GPIO_LOCK(sc); 537 val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT); 538 if (val & TI_GPIO_MASK(pin)) 539 reg = TI_GPIO_CLEARDATAOUT; 540 else 541 reg = TI_GPIO_SETDATAOUT; 542 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 543 TI_GPIO_UNLOCK(sc); 544 545 return (0); 546 } 547 548 static int 549 ti_gpio_bank_init(device_t dev) 550 { 551 int pin, err; 552 struct ti_gpio_softc *sc; 553 uint32_t flags, reg_oe, reg_set, rev; 554 uint64_t rev_address; 555 556 sc = device_get_softc(dev); 557 558 /* Enable the interface and functional clocks for the module. */ 559 rev_address = ti_sysc_get_rev_address(device_get_parent(dev)); 560 /* AM335x 561 * sc->sc_bank used in am335x/am335x_gpio.c and omap4/omap4_gpio.c */ 562 switch(ti_chip()) { 563 #ifdef SOC_OMAP4 564 case CHIP_OMAP_4: 565 switch (rev_address) { 566 case OMAP4_GPIO1_REV: 567 sc->sc_bank = 0; 568 break; 569 case OMAP4_GPIO2_REV: 570 sc->sc_bank = 1; 571 break; 572 case OMAP4_GPIO3_REV: 573 sc->sc_bank = 2; 574 break; 575 case OMAP4_GPIO4_REV: 576 sc->sc_bank = 3; 577 break; 578 case OMAP4_GPIO5_REV: 579 sc->sc_bank = 4; 580 break; 581 case OMAP4_GPIO6_REV: 582 sc->sc_bank = 5; 583 break; 584 } 585 #endif 586 #ifdef SOC_TI_AM335X 587 case CHIP_AM335X: 588 switch (rev_address) { 589 case AM335X_GPIO0_REV: 590 sc->sc_bank = 0; 591 break; 592 case AM335X_GPIO1_REV: 593 sc->sc_bank = 1; 594 break; 595 case AM335X_GPIO2_REV: 596 sc->sc_bank = 2; 597 break; 598 case AM335X_GPIO3_REV: 599 sc->sc_bank = 3; 600 break; 601 } 602 #endif 603 } 604 err = ti_sysc_clock_enable(device_get_parent(dev)); 605 if (err) { 606 device_printf(dev, "Failed to enable clock\n"); 607 return (EINVAL); 608 } 609 610 /* 611 * Read the revision number of the module. TI don't publish the 612 * actual revision numbers, so instead the values have been 613 * determined by experimentation. 614 */ 615 rev = ti_gpio_read_4(sc, 616 ti_sysc_get_rev_address_offset_host(device_get_parent(dev))); 617 618 /* Check the revision. */ 619 if (rev != ti_gpio_rev()) { 620 device_printf(dev, "Warning: could not determine the revision " 621 "of GPIO module (revision:0x%08x)\n", rev); 622 return (EINVAL); 623 } 624 625 /* Disable interrupts for all pins. */ 626 ti_gpio_intr_clr(sc, 0xffffffff); 627 628 /* Init OE register based on pads configuration. */ 629 reg_oe = 0xffffffff; 630 reg_set = 0; 631 for (pin = 0; pin < PINS_PER_BANK; pin++) { 632 TI_GPIO_GET_FLAGS(dev, pin, &flags); 633 if (flags & GPIO_PIN_OUTPUT) { 634 reg_oe &= ~(1UL << pin); 635 if (flags & GPIO_PIN_PULLUP) 636 reg_set |= (1UL << pin); 637 } 638 } 639 ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe); 640 if (reg_set) 641 ti_gpio_write_4(sc, TI_GPIO_SETDATAOUT, reg_set); 642 643 return (0); 644 } 645 646 /** 647 * ti_gpio_attach - attach function for the driver 648 * @dev: gpio device handle 649 * 650 * Allocates and sets up the driver context for all GPIO banks. This function 651 * expects the memory ranges and IRQs to already be allocated to the driver. 652 * 653 * LOCKING: 654 * None 655 * 656 * RETURNS: 657 * Always returns 0 658 */ 659 static int 660 ti_gpio_attach(device_t dev) 661 { 662 struct ti_gpio_softc *sc; 663 int err; 664 665 sc = device_get_softc(dev); 666 sc->sc_dev = dev; 667 TI_GPIO_LOCK_INIT(sc); 668 ti_gpio_pin_max(dev, &sc->sc_maxpin); 669 sc->sc_maxpin++; 670 671 sc->sc_mem_rid = 0; 672 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 673 &sc->sc_mem_rid, RF_ACTIVE); 674 if (!sc->sc_mem_res) { 675 device_printf(dev, "Error: could not allocate mem resources\n"); 676 ti_gpio_detach(dev); 677 return (ENXIO); 678 } 679 680 sc->sc_irq_rid = 0; 681 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 682 &sc->sc_irq_rid, RF_ACTIVE); 683 if (!sc->sc_irq_res) { 684 device_printf(dev, "Error: could not allocate irq resources\n"); 685 ti_gpio_detach(dev); 686 return (ENXIO); 687 } 688 689 /* 690 * Register our interrupt filter for each of the IRQ resources. 691 */ 692 if (bus_setup_intr(dev, sc->sc_irq_res, 693 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc, 694 &sc->sc_irq_hdl) != 0) { 695 device_printf(dev, 696 "WARNING: unable to register interrupt filter\n"); 697 ti_gpio_detach(dev); 698 return (ENXIO); 699 } 700 701 if (ti_gpio_pic_attach(sc) != 0) { 702 device_printf(dev, "WARNING: unable to attach PIC\n"); 703 ti_gpio_detach(dev); 704 return (ENXIO); 705 } 706 707 /* We need to go through each block and ensure the clocks are running and 708 * the module is enabled. It might be better to do this only when the 709 * pins are configured which would result in less power used if the GPIO 710 * pins weren't used ... 711 */ 712 if (sc->sc_mem_res != NULL) { 713 /* Initialize the GPIO module. */ 714 err = ti_gpio_bank_init(dev); 715 if (err != 0) { 716 ti_gpio_detach(dev); 717 return (err); 718 } 719 } 720 721 sc->sc_busdev = gpiobus_attach_bus(dev); 722 if (sc->sc_busdev == NULL) { 723 ti_gpio_detach(dev); 724 return (ENXIO); 725 } 726 727 return (0); 728 } 729 730 /** 731 * ti_gpio_detach - detach function for the driver 732 * @dev: scm device handle 733 * 734 * Allocates and sets up the driver context, this simply entails creating a 735 * bus mappings for the SCM register set. 736 * 737 * LOCKING: 738 * None 739 * 740 * RETURNS: 741 * Always returns 0 742 */ 743 static int 744 ti_gpio_detach(device_t dev) 745 { 746 struct ti_gpio_softc *sc = device_get_softc(dev); 747 748 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 749 750 /* Disable all interrupts */ 751 if (sc->sc_mem_res != NULL) 752 ti_gpio_intr_clr(sc, 0xffffffff); 753 if (sc->sc_busdev != NULL) 754 gpiobus_detach_bus(dev); 755 if (sc->sc_isrcs != NULL) 756 ti_gpio_pic_detach(sc); 757 /* Release the memory and IRQ resources. */ 758 if (sc->sc_irq_hdl) { 759 bus_teardown_intr(dev, sc->sc_irq_res, 760 sc->sc_irq_hdl); 761 } 762 if (sc->sc_irq_res) 763 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 764 sc->sc_irq_res); 765 if (sc->sc_mem_res) 766 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, 767 sc->sc_mem_res); 768 TI_GPIO_LOCK_DESTROY(sc); 769 770 return (0); 771 } 772 773 static inline void 774 ti_gpio_rwreg_modify(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask, 775 bool set_bits) 776 { 777 uint32_t value; 778 779 value = ti_gpio_read_4(sc, reg); 780 ti_gpio_write_4(sc, reg, set_bits ? value | mask : value & ~mask); 781 } 782 783 static inline void 784 ti_gpio_isrc_mask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 785 { 786 787 /* Writing a 0 has no effect. */ 788 ti_gpio_intr_clr(sc, tgi->tgi_mask); 789 } 790 791 static inline void 792 ti_gpio_isrc_unmask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 793 { 794 795 /* Writing a 0 has no effect. */ 796 ti_gpio_intr_set(sc, tgi->tgi_mask); 797 } 798 799 static inline void 800 ti_gpio_isrc_eoi(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 801 { 802 803 /* Writing a 0 has no effect. */ 804 ti_gpio_intr_ack(sc, tgi->tgi_mask); 805 } 806 807 static inline bool 808 ti_gpio_isrc_is_level(struct ti_gpio_irqsrc *tgi) 809 { 810 811 return (tgi->tgi_mode == GPIO_INTR_LEVEL_LOW || 812 tgi->tgi_mode == GPIO_INTR_LEVEL_HIGH); 813 } 814 815 static int 816 ti_gpio_intr(void *arg) 817 { 818 u_int irq; 819 uint32_t reg; 820 struct ti_gpio_softc *sc; 821 struct trapframe *tf; 822 struct ti_gpio_irqsrc *tgi; 823 824 sc = (struct ti_gpio_softc *)arg; 825 tf = curthread->td_intr_frame; 826 827 reg = ti_gpio_intr_status(sc); 828 for (irq = 0; irq < sc->sc_maxpin; irq++) { 829 tgi = &sc->sc_isrcs[irq]; 830 if ((reg & tgi->tgi_mask) == 0) 831 continue; 832 if (!ti_gpio_isrc_is_level(tgi)) 833 ti_gpio_isrc_eoi(sc, tgi); 834 if (intr_isrc_dispatch(&tgi->tgi_isrc, tf) != 0) { 835 ti_gpio_isrc_mask(sc, tgi); 836 if (ti_gpio_isrc_is_level(tgi)) 837 ti_gpio_isrc_eoi(sc, tgi); 838 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 839 irq); 840 } 841 } 842 return (FILTER_HANDLED); 843 } 844 845 static int 846 ti_gpio_pic_attach(struct ti_gpio_softc *sc) 847 { 848 int error; 849 uint32_t irq; 850 const char *name; 851 852 sc->sc_isrcs = malloc(sizeof(*sc->sc_isrcs) * sc->sc_maxpin, M_DEVBUF, 853 M_WAITOK | M_ZERO); 854 855 name = device_get_nameunit(sc->sc_dev); 856 for (irq = 0; irq < sc->sc_maxpin; irq++) { 857 sc->sc_isrcs[irq].tgi_irq = irq; 858 sc->sc_isrcs[irq].tgi_mask = TI_GPIO_MASK(irq); 859 sc->sc_isrcs[irq].tgi_mode = GPIO_INTR_CONFORM; 860 861 error = intr_isrc_register(&sc->sc_isrcs[irq].tgi_isrc, 862 sc->sc_dev, 0, "%s,%u", name, irq); 863 if (error != 0) 864 return (error); /* XXX deregister ISRCs */ 865 } 866 if (intr_pic_register(sc->sc_dev, 867 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL) 868 return (ENXIO); 869 870 return (0); 871 } 872 873 static int 874 ti_gpio_pic_detach(struct ti_gpio_softc *sc) 875 { 876 877 /* 878 * There has not been established any procedure yet 879 * how to detach PIC from living system correctly. 880 */ 881 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__); 882 return (EBUSY); 883 } 884 885 static void 886 ti_gpio_pic_config_intr(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi, 887 uint32_t mode) 888 { 889 890 TI_GPIO_LOCK(sc); 891 ti_gpio_rwreg_modify(sc, TI_GPIO_RISINGDETECT, tgi->tgi_mask, 892 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH); 893 ti_gpio_rwreg_modify(sc, TI_GPIO_FALLINGDETECT, tgi->tgi_mask, 894 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH); 895 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT1, tgi->tgi_mask, 896 mode == GPIO_INTR_LEVEL_HIGH); 897 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT0, tgi->tgi_mask, 898 mode == GPIO_INTR_LEVEL_LOW); 899 tgi->tgi_mode = mode; 900 TI_GPIO_UNLOCK(sc); 901 } 902 903 static void 904 ti_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 905 { 906 struct ti_gpio_softc *sc = device_get_softc(dev); 907 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 908 909 ti_gpio_isrc_mask(sc, tgi); 910 } 911 912 static void 913 ti_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 914 { 915 struct ti_gpio_softc *sc = device_get_softc(dev); 916 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 917 918 arm_irq_memory_barrier(tgi->tgi_irq); 919 ti_gpio_isrc_unmask(sc, tgi); 920 } 921 922 static int 923 ti_gpio_pic_map_fdt(struct ti_gpio_softc *sc, struct intr_map_data_fdt *daf, 924 u_int *irqp, uint32_t *modep) 925 { 926 uint32_t mode; 927 928 /* 929 * The first cell is the interrupt number. 930 * The second cell is used to specify flags: 931 * bits[3:0] trigger type and level flags: 932 * 1 = low-to-high edge triggered. 933 * 2 = high-to-low edge triggered. 934 * 4 = active high level-sensitive. 935 * 8 = active low level-sensitive. 936 */ 937 if (daf->ncells != 2 || daf->cells[0] >= sc->sc_maxpin) 938 return (EINVAL); 939 940 /* Only reasonable modes are supported. */ 941 if (daf->cells[1] == 1) 942 mode = GPIO_INTR_EDGE_RISING; 943 else if (daf->cells[1] == 2) 944 mode = GPIO_INTR_EDGE_FALLING; 945 else if (daf->cells[1] == 3) 946 mode = GPIO_INTR_EDGE_BOTH; 947 else if (daf->cells[1] == 4) 948 mode = GPIO_INTR_LEVEL_HIGH; 949 else if (daf->cells[1] == 8) 950 mode = GPIO_INTR_LEVEL_LOW; 951 else 952 return (EINVAL); 953 954 *irqp = daf->cells[0]; 955 if (modep != NULL) 956 *modep = mode; 957 return (0); 958 } 959 960 static int 961 ti_gpio_pic_map_gpio(struct ti_gpio_softc *sc, struct intr_map_data_gpio *dag, 962 u_int *irqp, uint32_t *modep) 963 { 964 uint32_t mode; 965 966 if (dag->gpio_pin_num >= sc->sc_maxpin) 967 return (EINVAL); 968 969 mode = dag->gpio_intr_mode; 970 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH && 971 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING && 972 mode != GPIO_INTR_EDGE_BOTH) 973 return (EINVAL); 974 975 *irqp = dag->gpio_pin_num; 976 if (modep != NULL) 977 *modep = mode; 978 return (0); 979 } 980 981 static int 982 ti_gpio_pic_map(struct ti_gpio_softc *sc, struct intr_map_data *data, 983 u_int *irqp, uint32_t *modep) 984 { 985 986 switch (data->type) { 987 case INTR_MAP_DATA_FDT: 988 return (ti_gpio_pic_map_fdt(sc, 989 (struct intr_map_data_fdt *)data, irqp, modep)); 990 case INTR_MAP_DATA_GPIO: 991 return (ti_gpio_pic_map_gpio(sc, 992 (struct intr_map_data_gpio *)data, irqp, modep)); 993 default: 994 return (ENOTSUP); 995 } 996 } 997 998 static int 999 ti_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 1000 struct intr_irqsrc **isrcp) 1001 { 1002 int error; 1003 u_int irq; 1004 struct ti_gpio_softc *sc = device_get_softc(dev); 1005 1006 error = ti_gpio_pic_map(sc, data, &irq, NULL); 1007 if (error == 0) 1008 *isrcp = &sc->sc_isrcs[irq].tgi_isrc; 1009 return (error); 1010 } 1011 1012 static void 1013 ti_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 1014 { 1015 struct ti_gpio_softc *sc = device_get_softc(dev); 1016 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1017 1018 if (ti_gpio_isrc_is_level(tgi)) 1019 ti_gpio_isrc_eoi(sc, tgi); 1020 } 1021 1022 static void 1023 ti_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 1024 { 1025 1026 ti_gpio_pic_enable_intr(dev, isrc); 1027 } 1028 1029 static void 1030 ti_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 1031 { 1032 struct ti_gpio_softc *sc = device_get_softc(dev); 1033 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1034 1035 ti_gpio_isrc_mask(sc, tgi); 1036 if (ti_gpio_isrc_is_level(tgi)) 1037 ti_gpio_isrc_eoi(sc, tgi); 1038 } 1039 1040 static int 1041 ti_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 1042 struct resource *res, struct intr_map_data *data) 1043 { 1044 u_int irq; 1045 uint32_t mode; 1046 struct ti_gpio_softc *sc; 1047 struct ti_gpio_irqsrc *tgi; 1048 1049 if (data == NULL) 1050 return (ENOTSUP); 1051 1052 sc = device_get_softc(dev); 1053 tgi = (struct ti_gpio_irqsrc *)isrc; 1054 1055 /* Get and check config for an interrupt. */ 1056 if (ti_gpio_pic_map(sc, data, &irq, &mode) != 0 || tgi->tgi_irq != irq) 1057 return (EINVAL); 1058 1059 /* 1060 * If this is a setup for another handler, 1061 * only check that its configuration match. 1062 */ 1063 if (isrc->isrc_handlers != 0) 1064 return (tgi->tgi_mode == mode ? 0 : EINVAL); 1065 1066 ti_gpio_pic_config_intr(sc, tgi, mode); 1067 return (0); 1068 } 1069 1070 static int 1071 ti_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 1072 struct resource *res, struct intr_map_data *data) 1073 { 1074 struct ti_gpio_softc *sc = device_get_softc(dev); 1075 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1076 1077 if (isrc->isrc_handlers == 0) 1078 ti_gpio_pic_config_intr(sc, tgi, GPIO_INTR_CONFORM); 1079 return (0); 1080 } 1081 1082 static phandle_t 1083 ti_gpio_get_node(device_t bus, device_t dev) 1084 { 1085 1086 /* We only have one child, the GPIO bus, which needs our own node. */ 1087 return (ofw_bus_get_node(bus)); 1088 } 1089 1090 static device_method_t ti_gpio_methods[] = { 1091 DEVMETHOD(device_attach, ti_gpio_attach), 1092 DEVMETHOD(device_detach, ti_gpio_detach), 1093 1094 /* GPIO protocol */ 1095 DEVMETHOD(gpio_get_bus, ti_gpio_get_bus), 1096 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max), 1097 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname), 1098 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags), 1099 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps), 1100 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags), 1101 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get), 1102 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set), 1103 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle), 1104 1105 /* Interrupt controller interface */ 1106 DEVMETHOD(pic_disable_intr, ti_gpio_pic_disable_intr), 1107 DEVMETHOD(pic_enable_intr, ti_gpio_pic_enable_intr), 1108 DEVMETHOD(pic_map_intr, ti_gpio_pic_map_intr), 1109 DEVMETHOD(pic_setup_intr, ti_gpio_pic_setup_intr), 1110 DEVMETHOD(pic_teardown_intr, ti_gpio_pic_teardown_intr), 1111 DEVMETHOD(pic_post_filter, ti_gpio_pic_post_filter), 1112 DEVMETHOD(pic_post_ithread, ti_gpio_pic_post_ithread), 1113 DEVMETHOD(pic_pre_ithread, ti_gpio_pic_pre_ithread), 1114 1115 /* ofw_bus interface */ 1116 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node), 1117 1118 {0, 0}, 1119 }; 1120 1121 driver_t ti_gpio_driver = { 1122 "gpio", 1123 ti_gpio_methods, 1124 sizeof(struct ti_gpio_softc), 1125 };
Cache object: 25aa50c84bc2d4ee2a58a8fdb78f3483
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