FreeBSD/Linux Kernel Cross Reference
sys/arm/ti/ti_wdt.c
1 /*-
2 * Copyright (c) 2014 Rui Paulo <rpaulo@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
25 */
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/conf.h>
33 #include <sys/eventhandler.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/malloc.h>
37 #include <sys/rman.h>
38 #include <sys/event.h>
39 #include <sys/selinfo.h>
40 #include <sys/watchdog.h>
41 #include <machine/bus.h>
42 #include <machine/cpu.h>
43 #include <machine/frame.h>
44 #include <machine/intr.h>
45
46 #include <dev/ofw/openfirm.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
49
50 #include <machine/bus.h>
51
52 #include <arm/ti/ti_wdt.h>
53
54 #ifdef DEBUG
55 #define DPRINTF(fmt, ...) do { \
56 printf("%s: ", __func__); \
57 printf(fmt, __VA_ARGS__); \
58 } while (0)
59 #else
60 #define DPRINTF(fmt, ...)
61 #endif
62
63 static device_probe_t ti_wdt_probe;
64 static device_attach_t ti_wdt_attach;
65 static device_detach_t ti_wdt_detach;
66 static void ti_wdt_intr(void *);
67 static void ti_wdt_event(void *, unsigned int, int *);
68
69 struct ti_wdt_softc {
70 struct resource *sc_mem_res;
71 struct resource *sc_irq_res;
72 void *sc_intr;
73 bus_space_tag_t sc_bt;
74 bus_space_handle_t sc_bh;
75 eventhandler_tag sc_ev_tag;
76 };
77
78 static device_method_t ti_wdt_methods[] = {
79 DEVMETHOD(device_probe, ti_wdt_probe),
80 DEVMETHOD(device_attach, ti_wdt_attach),
81 DEVMETHOD(device_detach, ti_wdt_detach),
82
83 DEVMETHOD_END
84 };
85
86 static driver_t ti_wdt_driver = {
87 "ti_wdt",
88 ti_wdt_methods,
89 sizeof(struct ti_wdt_softc)
90 };
91
92 DRIVER_MODULE(ti_wdt, simplebus, ti_wdt_driver, 0, 0);
93 MODULE_DEPEND(ti_wdt, ti_sysc, 1, 1, 1);
94
95 static __inline uint32_t
96 ti_wdt_reg_read(struct ti_wdt_softc *sc, uint32_t reg)
97 {
98
99 return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
100 }
101
102 static __inline void
103 ti_wdt_reg_write(struct ti_wdt_softc *sc, uint32_t reg, uint32_t val)
104 {
105
106 bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
107 }
108
109 /*
110 * Wait for the write to a specific synchronised register to complete.
111 */
112 static __inline void
113 ti_wdt_reg_wait(struct ti_wdt_softc *sc, uint32_t bit)
114 {
115
116 while (ti_wdt_reg_read(sc, TI_WDT_WWPS) & bit)
117 DELAY(10);
118 }
119
120 static __inline void
121 ti_wdt_disable(struct ti_wdt_softc *sc)
122 {
123
124 DPRINTF("disabling watchdog %p\n", sc);
125 ti_wdt_reg_write(sc, TI_WDT_WSPR, 0xAAAA);
126 ti_wdt_reg_wait(sc, TI_W_PEND_WSPR);
127 ti_wdt_reg_write(sc, TI_WDT_WSPR, 0x5555);
128 ti_wdt_reg_wait(sc, TI_W_PEND_WSPR);
129 }
130
131 static __inline void
132 ti_wdt_enable(struct ti_wdt_softc *sc)
133 {
134
135 DPRINTF("enabling watchdog %p\n", sc);
136 ti_wdt_reg_write(sc, TI_WDT_WSPR, 0xBBBB);
137 ti_wdt_reg_wait(sc, TI_W_PEND_WSPR);
138 ti_wdt_reg_write(sc, TI_WDT_WSPR, 0x4444);
139 ti_wdt_reg_wait(sc, TI_W_PEND_WSPR);
140 }
141
142 static int
143 ti_wdt_probe(device_t dev)
144 {
145
146 if (!ofw_bus_status_okay(dev))
147 return (ENXIO);
148 if (ofw_bus_is_compatible(dev, "ti,omap3-wdt")) {
149 device_set_desc(dev, "TI Watchdog Timer");
150 return (BUS_PROBE_DEFAULT);
151 }
152
153 return (ENXIO);
154 }
155
156 static int
157 ti_wdt_attach(device_t dev)
158 {
159 struct ti_wdt_softc *sc;
160 int rid;
161
162 sc = device_get_softc(dev);
163 rid = 0;
164 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
165 RF_ACTIVE);
166 if (sc->sc_mem_res == NULL) {
167 device_printf(dev, "could not allocate memory resource\n");
168 return (ENXIO);
169 }
170 sc->sc_bt = rman_get_bustag(sc->sc_mem_res);
171 sc->sc_bh = rman_get_bushandle(sc->sc_mem_res);
172 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
173 if (sc->sc_irq_res == NULL) {
174 device_printf(dev, "could not allocate interrupt resource\n");
175 ti_wdt_detach(dev);
176 return (ENXIO);
177 }
178 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE | INTR_TYPE_MISC,
179 NULL, ti_wdt_intr, sc, &sc->sc_intr) != 0) {
180 device_printf(dev,
181 "unable to setup the interrupt handler\n");
182 ti_wdt_detach(dev);
183 return (ENXIO);
184 }
185 /* Reset, enable interrupts and stop the watchdog. */
186 ti_wdt_reg_write(sc, TI_WDT_WDSC,
187 ti_wdt_reg_read(sc, TI_WDT_WDSC) | TI_WDSC_SR);
188 while (ti_wdt_reg_read(sc, TI_WDT_WDSC) & TI_WDSC_SR)
189 DELAY(10);
190 ti_wdt_reg_write(sc, TI_WDT_WIRQENSET, TI_IRQ_EN_OVF | TI_IRQ_EN_DLY);
191 ti_wdt_disable(sc);
192 if (bootverbose)
193 device_printf(dev, "revision: 0x%x\n",
194 ti_wdt_reg_read(sc, TI_WDT_WIDR));
195 sc->sc_ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ti_wdt_event, sc,
196 0);
197
198 return (0);
199 }
200
201 static int
202 ti_wdt_detach(device_t dev)
203 {
204 struct ti_wdt_softc *sc;
205
206 sc = device_get_softc(dev);
207 if (sc->sc_ev_tag)
208 EVENTHANDLER_DEREGISTER(watchdog_list, sc->sc_ev_tag);
209 if (sc->sc_intr)
210 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr);
211 if (sc->sc_irq_res)
212 bus_release_resource(dev, SYS_RES_IRQ,
213 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
214 if (sc->sc_mem_res)
215 bus_release_resource(dev, SYS_RES_MEMORY,
216 rman_get_rid(sc->sc_mem_res), sc->sc_mem_res);
217
218 return (0);
219 }
220
221 static void
222 ti_wdt_intr(void *arg)
223 {
224 struct ti_wdt_softc *sc;
225
226 sc = arg;
227 DPRINTF("interrupt %p", sc);
228 ti_wdt_reg_write(sc, TI_WDT_WIRQSTAT, TI_IRQ_EV_OVF | TI_IRQ_EV_DLY);
229 /* TODO: handle interrupt */
230 }
231
232 static void
233 ti_wdt_event(void *arg, unsigned int cmd, int *error)
234 {
235 struct ti_wdt_softc *sc;
236 uint8_t s;
237 uint32_t wldr;
238 uint32_t ptv;
239
240 sc = arg;
241 ti_wdt_disable(sc);
242 if (cmd == WD_TO_NEVER) {
243 *error = 0;
244 return;
245 }
246 DPRINTF("cmd 0x%x\n", cmd);
247 cmd &= WD_INTERVAL;
248 if (cmd < WD_TO_1SEC) {
249 *error = EINVAL;
250 return;
251 }
252 s = 1 << (cmd - WD_TO_1SEC);
253 DPRINTF("seconds %u\n", s);
254 /*
255 * Leave the pre-scaler with its default values:
256 * PTV = 0 == 2**0 == 1
257 * PRE = 1 (enabled)
258 *
259 * Compute the load register value assuming a 32kHz clock.
260 * See OVF_Rate in the WDT section of the AM335x TRM.
261 */
262 ptv = 0;
263 wldr = 0xffffffff - (s * (32768 / (1 << ptv))) + 1;
264 DPRINTF("wldr 0x%x\n", wldr);
265 ti_wdt_reg_write(sc, TI_WDT_WLDR, wldr);
266 /*
267 * Trigger a timer reload.
268 */
269 ti_wdt_reg_write(sc, TI_WDT_WTGR,
270 ti_wdt_reg_read(sc, TI_WDT_WTGR) + 1);
271 ti_wdt_reg_wait(sc, TI_W_PEND_WTGR);
272 ti_wdt_enable(sc);
273 *error = 0;
274 }
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