The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/ti/ti_wdt.c

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    1 /*-
    2  * Copyright (c) 2014 Rui Paulo <rpaulo@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   16  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
   17  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
   18  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   19  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   20  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
   22  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
   23  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   24  * POSSIBILITY OF SUCH DAMAGE.
   25  */
   26 #include <sys/cdefs.h>
   27 __FBSDID("$FreeBSD$");
   28 
   29 #include <sys/param.h>
   30 #include <sys/systm.h>
   31 #include <sys/bus.h>
   32 #include <sys/conf.h>
   33 #include <sys/eventhandler.h>
   34 #include <sys/kernel.h>
   35 #include <sys/module.h>
   36 #include <sys/malloc.h>
   37 #include <sys/rman.h>
   38 #include <sys/event.h>
   39 #include <sys/selinfo.h>
   40 #include <sys/watchdog.h>
   41 #include <machine/bus.h>
   42 #include <machine/cpu.h>
   43 #include <machine/frame.h>
   44 #include <machine/intr.h>
   45 
   46 #include <dev/ofw/openfirm.h>
   47 #include <dev/ofw/ofw_bus.h>
   48 #include <dev/ofw/ofw_bus_subr.h>
   49 
   50 #include <machine/bus.h>
   51 
   52 #include <arm/ti/ti_wdt.h>
   53 
   54 #ifdef DEBUG
   55 #define DPRINTF(fmt, ...)       do {    \
   56         printf("%s: ", __func__);       \
   57         printf(fmt, __VA_ARGS__);       \
   58 } while (0)
   59 #else
   60 #define DPRINTF(fmt, ...)
   61 #endif
   62 
   63 static device_probe_t           ti_wdt_probe;
   64 static device_attach_t          ti_wdt_attach;
   65 static device_detach_t          ti_wdt_detach;
   66 static void                     ti_wdt_intr(void *);
   67 static void                     ti_wdt_event(void *, unsigned int, int *);
   68 
   69 struct ti_wdt_softc {
   70         struct resource         *sc_mem_res;
   71         struct resource         *sc_irq_res;
   72         void                    *sc_intr;
   73         bus_space_tag_t         sc_bt;
   74         bus_space_handle_t      sc_bh;
   75         eventhandler_tag        sc_ev_tag;
   76 };
   77 
   78 static device_method_t ti_wdt_methods[] = {
   79         DEVMETHOD(device_probe,         ti_wdt_probe),
   80         DEVMETHOD(device_attach,        ti_wdt_attach),
   81         DEVMETHOD(device_detach,        ti_wdt_detach),
   82 
   83         DEVMETHOD_END
   84 };
   85 
   86 static driver_t ti_wdt_driver = {
   87         "ti_wdt",
   88         ti_wdt_methods,
   89         sizeof(struct ti_wdt_softc)
   90 };
   91 
   92 static devclass_t ti_wdt_devclass;
   93 
   94 DRIVER_MODULE(ti_wdt, simplebus, ti_wdt_driver, ti_wdt_devclass, 0, 0);
   95 MODULE_DEPEND(ti_wdt, ti_sysc, 1, 1, 1);
   96 
   97 static __inline uint32_t
   98 ti_wdt_reg_read(struct ti_wdt_softc *sc, uint32_t reg)
   99 {
  100 
  101         return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
  102 }
  103 
  104 static __inline void
  105 ti_wdt_reg_write(struct ti_wdt_softc *sc, uint32_t reg, uint32_t val)
  106 {
  107 
  108         bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
  109 }
  110 
  111 /*
  112  * Wait for the write to a specific synchronised register to complete.
  113  */
  114 static __inline void
  115 ti_wdt_reg_wait(struct ti_wdt_softc *sc, uint32_t bit)
  116 {
  117 
  118         while (ti_wdt_reg_read(sc, TI_WDT_WWPS) & bit)
  119                 DELAY(10);
  120 }
  121 
  122 static __inline void
  123 ti_wdt_disable(struct ti_wdt_softc *sc)
  124 {
  125 
  126         DPRINTF("disabling watchdog %p\n", sc);
  127         ti_wdt_reg_write(sc, TI_WDT_WSPR, 0xAAAA);
  128         ti_wdt_reg_wait(sc, TI_W_PEND_WSPR);
  129         ti_wdt_reg_write(sc, TI_WDT_WSPR, 0x5555);
  130         ti_wdt_reg_wait(sc, TI_W_PEND_WSPR);
  131 }
  132 
  133 static __inline void
  134 ti_wdt_enable(struct ti_wdt_softc *sc)
  135 {
  136 
  137         DPRINTF("enabling watchdog %p\n", sc);
  138         ti_wdt_reg_write(sc, TI_WDT_WSPR, 0xBBBB);
  139         ti_wdt_reg_wait(sc, TI_W_PEND_WSPR);
  140         ti_wdt_reg_write(sc, TI_WDT_WSPR, 0x4444);
  141         ti_wdt_reg_wait(sc, TI_W_PEND_WSPR);
  142 }
  143 
  144 static int
  145 ti_wdt_probe(device_t dev)
  146 {
  147 
  148         if (!ofw_bus_status_okay(dev))
  149                 return (ENXIO);
  150         if (ofw_bus_is_compatible(dev, "ti,omap3-wdt")) {
  151                 device_set_desc(dev, "TI Watchdog Timer");
  152                 return (BUS_PROBE_DEFAULT);
  153         }
  154 
  155         return (ENXIO);
  156 }
  157 
  158 static int
  159 ti_wdt_attach(device_t dev)
  160 {
  161         struct ti_wdt_softc *sc;
  162         int rid;
  163 
  164         sc = device_get_softc(dev);
  165         rid = 0;
  166         sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
  167             RF_ACTIVE);
  168         if (sc->sc_mem_res == NULL) {
  169                 device_printf(dev, "could not allocate memory resource\n");
  170                 return (ENXIO);
  171         }
  172         sc->sc_bt = rman_get_bustag(sc->sc_mem_res);
  173         sc->sc_bh = rman_get_bushandle(sc->sc_mem_res);
  174         sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
  175         if (sc->sc_irq_res == NULL) {
  176                 device_printf(dev, "could not allocate interrupt resource\n");
  177                 ti_wdt_detach(dev);
  178                 return (ENXIO);
  179         }
  180         if (bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE | INTR_TYPE_MISC,
  181                 NULL, ti_wdt_intr, sc,  &sc->sc_intr) != 0) {
  182                 device_printf(dev,
  183                     "unable to setup the interrupt handler\n");
  184                 ti_wdt_detach(dev);
  185                 return (ENXIO);
  186         }
  187         /* Reset, enable interrupts and stop the watchdog. */
  188         ti_wdt_reg_write(sc, TI_WDT_WDSC,
  189             ti_wdt_reg_read(sc, TI_WDT_WDSC) | TI_WDSC_SR);
  190         while (ti_wdt_reg_read(sc, TI_WDT_WDSC) & TI_WDSC_SR)
  191                 DELAY(10);
  192         ti_wdt_reg_write(sc, TI_WDT_WIRQENSET, TI_IRQ_EN_OVF | TI_IRQ_EN_DLY);
  193         ti_wdt_disable(sc);
  194         if (bootverbose)
  195                 device_printf(dev, "revision: 0x%x\n",
  196                     ti_wdt_reg_read(sc, TI_WDT_WIDR));
  197         sc->sc_ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ti_wdt_event, sc,
  198             0);
  199 
  200         return (0);
  201 }
  202 
  203 static int
  204 ti_wdt_detach(device_t dev)
  205 {
  206         struct ti_wdt_softc *sc;
  207 
  208         sc = device_get_softc(dev);
  209         if (sc->sc_ev_tag)
  210                 EVENTHANDLER_DEREGISTER(watchdog_list, sc->sc_ev_tag);
  211         if (sc->sc_intr)
  212                 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr);
  213         if (sc->sc_irq_res)
  214                 bus_release_resource(dev, SYS_RES_IRQ,
  215                     rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
  216         if (sc->sc_mem_res)
  217                 bus_release_resource(dev, SYS_RES_MEMORY,
  218                     rman_get_rid(sc->sc_mem_res),  sc->sc_mem_res);
  219 
  220         return (0);
  221 }
  222 
  223 static void
  224 ti_wdt_intr(void *arg)
  225 {
  226         struct ti_wdt_softc *sc;
  227 
  228         sc = arg;
  229         DPRINTF("interrupt %p", sc);
  230         ti_wdt_reg_write(sc, TI_WDT_WIRQSTAT, TI_IRQ_EV_OVF | TI_IRQ_EV_DLY);
  231         /* TODO: handle interrupt */
  232 }
  233 
  234 static void
  235 ti_wdt_event(void *arg, unsigned int cmd, int *error)
  236 {
  237         struct ti_wdt_softc *sc;
  238         uint8_t s;
  239         uint32_t wldr;
  240         uint32_t ptv;
  241 
  242         sc = arg;
  243         ti_wdt_disable(sc);
  244         if (cmd == WD_TO_NEVER) {
  245                 *error = 0;
  246                 return;
  247         }
  248         DPRINTF("cmd 0x%x\n", cmd);
  249         cmd &= WD_INTERVAL;
  250         if (cmd < WD_TO_1SEC) {
  251                 *error = EINVAL;
  252                 return;
  253         }
  254         s = 1 << (cmd - WD_TO_1SEC);
  255         DPRINTF("seconds %u\n", s);
  256         /*
  257          * Leave the pre-scaler with its default values:
  258          * PTV = 0 == 2**0 == 1
  259          * PRE = 1 (enabled)
  260          *
  261          * Compute the load register value assuming a 32kHz clock.
  262          * See OVF_Rate in the WDT section of the AM335x TRM.
  263          */
  264         ptv = 0;
  265         wldr = 0xffffffff - (s * (32768 / (1 << ptv))) + 1;
  266         DPRINTF("wldr 0x%x\n", wldr);
  267         ti_wdt_reg_write(sc, TI_WDT_WLDR, wldr);
  268         /*
  269          * Trigger a timer reload.
  270          */
  271         ti_wdt_reg_write(sc, TI_WDT_WTGR,
  272             ti_wdt_reg_read(sc, TI_WDT_WTGR) + 1);
  273         ti_wdt_reg_wait(sc, TI_W_PEND_WTGR);
  274         ti_wdt_enable(sc);
  275         *error = 0;
  276 }

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