omap_ehci.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2011
    5  *      Ben Gray <ben.r.gray@gmail.com>.
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  */
   29 #include <sys/cdefs.h>
   30 __FBSDID("$FreeBSD$");
   31 
   32 #include <sys/param.h>
   33 #include <sys/systm.h>
   34 #include <sys/conf.h>
   35 #include <sys/kernel.h>
   36 #include <sys/rman.h>
   37 #include <sys/module.h>
   38 #include <sys/proc.h>
   39 #include <sys/condvar.h>
   40 
   41 #include <dev/fdt/simplebus.h>
   42 #include <dev/fdt/fdt_common.h>
   43 #include <dev/ofw/ofw_bus_subr.h>
   44 
   45 #include <dev/usb/usb.h>
   46 #include <dev/usb/usbdi.h>
   47 
   48 #include <dev/usb/usb_core.h>
   49 #include <dev/usb/usb_busdma.h>
   50 #include <dev/usb/usb_process.h>
   51 #include <dev/usb/usb_util.h>
   52 
   53 #include <dev/usb/usb_controller.h>
   54 #include <dev/usb/usb_bus.h>
   55 #include <dev/usb/controller/ehci.h>
   56 #include <dev/usb/controller/ehcireg.h>
   57 
   58 #include <machine/bus.h>
   59 
   60 #include <arm/ti/usb/omap_usb.h>
   61 
   62 #include <arm/ti/omap4/pandaboard/pandaboard.h>
   63 
   64 /* EHCI */
   65 #define OMAP_USBHOST_HCCAPBASE                      0x0000
   66 #define OMAP_USBHOST_HCSPARAMS                      0x0004
   67 #define OMAP_USBHOST_HCCPARAMS                      0x0008
   68 #define OMAP_USBHOST_USBCMD                         0x0010
   69 #define OMAP_USBHOST_USBSTS                         0x0014
   70 #define OMAP_USBHOST_USBINTR                        0x0018
   71 #define OMAP_USBHOST_FRINDEX                        0x001C
   72 #define OMAP_USBHOST_CTRLDSSEGMENT                  0x0020
   73 #define OMAP_USBHOST_PERIODICLISTBASE               0x0024
   74 #define OMAP_USBHOST_ASYNCLISTADDR                  0x0028
   75 #define OMAP_USBHOST_CONFIGFLAG                     0x0050
   76 #define OMAP_USBHOST_PORTSC(i)                      (0x0054 + (0x04 * (i)))
   77 #define OMAP_USBHOST_INSNREG00                      0x0090
   78 #define OMAP_USBHOST_INSNREG01                      0x0094
   79 #define OMAP_USBHOST_INSNREG02                      0x0098
   80 #define OMAP_USBHOST_INSNREG03                      0x009C
   81 #define OMAP_USBHOST_INSNREG04                      0x00A0
   82 #define OMAP_USBHOST_INSNREG05_UTMI                 0x00A4
   83 #define OMAP_USBHOST_INSNREG05_ULPI                 0x00A4
   84 #define OMAP_USBHOST_INSNREG06                      0x00A8
   85 #define OMAP_USBHOST_INSNREG07                      0x00AC
   86 #define OMAP_USBHOST_INSNREG08                      0x00B0
   87 
   88 #define OMAP_USBHOST_INSNREG04_DISABLE_UNSUSPEND   (1 << 5)
   89 
   90 #define OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT   31
   91 #define OMAP_USBHOST_INSNREG05_ULPI_PORTSEL_SHIFT   24
   92 #define OMAP_USBHOST_INSNREG05_ULPI_OPSEL_SHIFT     22
   93 #define OMAP_USBHOST_INSNREG05_ULPI_REGADD_SHIFT    16
   94 #define OMAP_USBHOST_INSNREG05_ULPI_EXTREGADD_SHIFT 8
   95 #define OMAP_USBHOST_INSNREG05_ULPI_WRDATA_SHIFT    0
   96 
   97 #define ULPI_FUNC_CTRL_RESET                    (1 << 5)
   98 
   99 /*-------------------------------------------------------------------------*/
  100 
  101 /*
  102  * Macros for Set and Clear
  103  * See ULPI 1.1 specification to find the registers with Set and Clear offsets
  104  */
  105 #define ULPI_SET(a)                             (a + 1)
  106 #define ULPI_CLR(a)                             (a + 2)
  107 
  108 /*-------------------------------------------------------------------------*/
  109 
  110 /*
  111  * Register Map
  112  */
  113 #define ULPI_VENDOR_ID_LOW                      0x00
  114 #define ULPI_VENDOR_ID_HIGH                     0x01
  115 #define ULPI_PRODUCT_ID_LOW                     0x02
  116 #define ULPI_PRODUCT_ID_HIGH                    0x03
  117 #define ULPI_FUNC_CTRL                          0x04
  118 #define ULPI_IFC_CTRL                           0x07
  119 #define ULPI_OTG_CTRL                           0x0a
  120 #define ULPI_USB_INT_EN_RISE                    0x0d
  121 #define ULPI_USB_INT_EN_FALL                    0x10
  122 #define ULPI_USB_INT_STS                        0x13
  123 #define ULPI_USB_INT_LATCH                      0x14
  124 #define ULPI_DEBUG                              0x15
  125 #define ULPI_SCRATCH                            0x16
  126 
  127 #define OMAP_EHCI_HC_DEVSTR    "TI OMAP USB 2.0 controller"
  128 
  129 struct omap_ehci_softc {
  130         ehci_softc_t        base;       /* storage for EHCI code */
  131         device_t            sc_dev;
  132 };
  133 
  134 static device_attach_t omap_ehci_attach;
  135 static device_detach_t omap_ehci_detach;
  136 
  137 /**
  138  *      omap_ehci_read_4 - read a 32-bit value from the EHCI registers
  139  *      omap_ehci_write_4 - write a 32-bit value from the EHCI registers
  140  *      @sc: omap ehci device context
  141  *      @off: byte offset within the register set to read from
  142  *      @val: the value to write into the register
  143  *      
  144  *
  145  *      LOCKING:
  146  *      None
  147  *
  148  *      RETURNS:
  149  *      nothing in case of write function, if read function returns the value read.
  150  */
  151 static inline uint32_t
  152 omap_ehci_read_4(struct omap_ehci_softc *sc, bus_size_t off)
  153 {
  154         return (bus_read_4(sc->base.sc_io_res, off));
  155 }
  156 
  157 static inline void
  158 omap_ehci_write_4(struct omap_ehci_softc *sc, bus_size_t off, uint32_t val)
  159 {
  160         bus_write_4(sc->base.sc_io_res, off, val);
  161 }
  162 
  163 /**
  164  *      omap_ehci_soft_phy_reset - resets the phy using the reset command
  165  *      @isc: omap ehci device context
  166  *      @port: port to send the reset over
  167  *      
  168  *
  169  *      LOCKING:
  170  *      none
  171  *
  172  *      RETURNS:
  173  *      nothing
  174  */
  175 static void 
  176 omap_ehci_soft_phy_reset(struct omap_ehci_softc *isc, unsigned int port)
  177 {
  178         unsigned long timeout = (hz < 10) ? 1 : ((100 * hz) / 1000);
  179         uint32_t reg;
  180 
  181         reg = ULPI_FUNC_CTRL_RESET
  182                 /* FUNCTION_CTRL_SET register */
  183                 | (ULPI_SET(ULPI_FUNC_CTRL) << OMAP_USBHOST_INSNREG05_ULPI_REGADD_SHIFT)
  184                 /* Write */
  185                 | (2 << OMAP_USBHOST_INSNREG05_ULPI_OPSEL_SHIFT)
  186                 /* PORTn */
  187                 | ((port + 1) << OMAP_USBHOST_INSNREG05_ULPI_PORTSEL_SHIFT)
  188                 /* start ULPI access*/
  189                 | (1 << OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT);
  190 
  191         omap_ehci_write_4(isc, OMAP_USBHOST_INSNREG05_ULPI, reg);
  192 
  193         /* Wait for ULPI access completion */
  194         while ((omap_ehci_read_4(isc, OMAP_USBHOST_INSNREG05_ULPI)
  195                & (1 << OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT))) {
  196                 /* Sleep for a tick */
  197                 pause("USBPHY_RESET", 1);
  198                 
  199                 if (timeout-- == 0) {
  200                         device_printf(isc->sc_dev, "PHY reset operation timed out\n");
  201                         break;
  202                 }
  203         }
  204 }
  205 
  206 /**
  207  *      omap_ehci_init - initialises the USB host EHCI controller
  208  *      @isc: omap ehci device context
  209  *
  210  *      This initialisation routine is quite heavily based on the work done by the
  211  *      OMAP Linux team (for which I thank them very much).  The init sequence is
  212  *      almost identical, diverging only for the FreeBSD specifics.
  213  *
  214  *      LOCKING:
  215  *      none
  216  *
  217  *      RETURNS:
  218  *      0 on success, a negative error code on failure.
  219  */
  220 static int
  221 omap_ehci_init(struct omap_ehci_softc *isc)
  222 {
  223         uint32_t reg = 0;
  224         int i;
  225         device_t uhh_dev;
  226 
  227         uhh_dev = device_get_parent(isc->sc_dev);
  228         device_printf(isc->sc_dev, "Starting TI EHCI USB Controller\n");
  229 
  230         /* Set the interrupt threshold control, it controls the maximum rate at
  231          * which the host controller issues interrupts.  We set it to 1 microframe
  232          * at startup - the default is 8 mircoframes (equates to 1ms).
  233          */
  234         reg = omap_ehci_read_4(isc, OMAP_USBHOST_USBCMD);
  235         reg &= 0xff00ffff;
  236         reg |= (1 << 16);
  237         omap_ehci_write_4(isc, OMAP_USBHOST_USBCMD, reg);
  238 
  239         /* Soft reset the PHY using PHY reset command over ULPI */
  240         for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
  241                 if (omap_usb_port_mode(uhh_dev, i) == EHCI_HCD_OMAP_MODE_PHY)
  242                         omap_ehci_soft_phy_reset(isc, i);
  243         }
  244 
  245         return(0);
  246 }
  247 
  248 /**
  249  *      omap_ehci_probe - starts the given command
  250  *      @dev: 
  251  *      
  252  *      Effectively boilerplate EHCI resume code.
  253  *
  254  *      LOCKING:
  255  *      Caller should be holding the OMAP3_MMC lock.
  256  *
  257  *      RETURNS:
  258  *      EH_HANDLED or EH_NOT_HANDLED
  259  */
  260 static int
  261 omap_ehci_probe(device_t dev)
  262 {
  263         if (!ofw_bus_status_okay(dev))
  264                 return (ENXIO);
  265 
  266         if (!ofw_bus_is_compatible(dev, "ti,ehci-omap"))
  267                 return (ENXIO);
  268 
  269         device_set_desc(dev, OMAP_EHCI_HC_DEVSTR);
  270 
  271         return (BUS_PROBE_DEFAULT);
  272 }
  273 
  274 /**
  275  *      omap_ehci_attach - driver entry point, sets up the ECHI controller/driver
  276  *      @dev: the new device handle
  277  *      
  278  *      Sets up bus spaces, interrupt handles, etc for the EHCI controller.  It also
  279  *      parses the resource hints and calls omap_ehci_init() to initialise the
  280  *      H/W.
  281  *
  282  *      LOCKING:
  283  *      none
  284  *
  285  *      RETURNS:
  286  *      0 on success or a positive error code on failure.
  287  */
  288 static int
  289 omap_ehci_attach(device_t dev)
  290 {
  291         struct omap_ehci_softc *isc = device_get_softc(dev);
  292         ehci_softc_t *sc = &isc->base;
  293 #ifdef SOC_OMAP4
  294         phandle_t root;
  295 #endif
  296         int err;
  297         int rid;
  298 
  299 #ifdef SOC_OMAP4
  300         /* 
  301          * If we're running a Pandaboard, run Pandaboard-specific 
  302          * init code.
  303          */
  304         root = OF_finddevice("/");
  305         if (ofw_bus_node_is_compatible(root, "ti,omap4-panda"))
  306                 pandaboard_usb_hub_init();
  307 #endif
  308 
  309         /* initialise some bus fields */
  310         sc->sc_bus.parent = dev;
  311         sc->sc_bus.devices = sc->sc_devices;
  312         sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
  313         sc->sc_bus.dma_bits = 32;
  314 
  315         sprintf(sc->sc_vendor, "Texas Instruments");
  316 
  317         /* save the device */
  318         isc->sc_dev = dev;
  319 
  320         /* get all DMA memory */
  321         if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev),
  322                                   &ehci_iterate_hw_softc)) {
  323                 return (ENOMEM);
  324         }
  325 
  326         /* Allocate resource for the EHCI register set */
  327         rid = 0;
  328         sc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
  329         if (!sc->sc_io_res) {
  330                 device_printf(dev, "Error: Could not map EHCI memory\n");
  331                 goto error;
  332         }
  333         /* Request an interrupt resource */
  334         rid = 0;
  335         sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
  336         if (sc->sc_irq_res == NULL) {
  337                 device_printf(dev, "Error: could not allocate irq\n");
  338                 goto error;
  339         }
  340 
  341         /* Add this device as a child of the USBus device */
  342         sc->sc_bus.bdev = device_add_child(dev, "usbus", -1);
  343         if (!sc->sc_bus.bdev) {
  344                 device_printf(dev, "Error: could not add USB device\n");
  345                 goto error;
  346         }
  347 
  348         device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
  349         device_set_desc(sc->sc_bus.bdev, OMAP_EHCI_HC_DEVSTR);
  350 
  351         /* Initialise the ECHI registers */
  352         err = omap_ehci_init(isc);
  353         if (err) {
  354                 device_printf(dev, "Error: could not setup OMAP EHCI, %d\n", err);
  355                 goto error;
  356         }
  357                 
  358         /* Set the tag and size of the register set in the EHCI context */
  359         sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
  360         sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
  361         sc->sc_io_size = rman_get_size(sc->sc_io_res);
  362 
  363         /* Setup the interrupt */
  364         err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
  365                                                  NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
  366         if (err) {
  367                 device_printf(dev, "Error: could not setup irq, %d\n", err);
  368                 sc->sc_intr_hdl = NULL;
  369                 goto error;
  370         }
  371 
  372         /* Finally we are ready to kick off the ECHI host controller */
  373         err = ehci_init(sc);
  374         if (err == 0) {
  375                 err = device_probe_and_attach(sc->sc_bus.bdev);
  376         }
  377         if (err) {
  378                 device_printf(dev, "Error: USB init failed err=%d\n", err);
  379                 goto error;
  380         }
  381 
  382         return (0);
  383 
  384 error:
  385         omap_ehci_detach(dev);
  386         return (ENXIO);
  387 }
  388 
  389 /**
  390  *      omap_ehci_detach - detach the device and cleanup the driver
  391  *      @dev: device handle
  392  *      
  393  *      Clean-up routine where everything initialised in omap_ehci_attach is
  394  *      freed and cleaned up.  This function calls omap_ehci_fini() to shutdown
  395  *      the on-chip module.
  396  *
  397  *      LOCKING:
  398  *      none
  399  *
  400  *      RETURNS:
  401  *      Always returns 0 (success).
  402  */
  403 static int
  404 omap_ehci_detach(device_t dev)
  405 {
  406         struct omap_ehci_softc *isc = device_get_softc(dev);
  407         ehci_softc_t *sc = &isc->base;
  408         int err;
  409 
  410         /* during module unload there are lots of children leftover */
  411         device_delete_children(dev);
  412 
  413         /*
  414          * disable interrupts that might have been switched on in ehci_init
  415          */
  416         if (sc->sc_io_res) {
  417                 EWRITE4(sc, EHCI_USBINTR, 0);
  418         }
  419 
  420         if (sc->sc_irq_res && sc->sc_intr_hdl) {
  421                 /*
  422                  * only call ehci_detach() after ehci_init()
  423                  */
  424                 ehci_detach(sc);
  425                 
  426                 err = bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr_hdl);
  427                 if (err)
  428                         device_printf(dev, "Error: could not tear down irq, %d\n", err);
  429                 sc->sc_intr_hdl = NULL;
  430         }
  431 
  432         /* Free the resources stored in the base EHCI handler */
  433         if (sc->sc_irq_res) {
  434                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
  435                 sc->sc_irq_res = NULL;
  436         }
  437         if (sc->sc_io_res) {
  438                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_io_res);
  439                 sc->sc_io_res = NULL;
  440         }
  441 
  442         return (0);
  443 }
  444 
  445 static device_method_t ehci_methods[] = {
  446         /* Device interface */
  447         DEVMETHOD(device_probe, omap_ehci_probe),
  448         DEVMETHOD(device_attach, omap_ehci_attach),
  449         DEVMETHOD(device_detach, omap_ehci_detach),
  450 
  451         DEVMETHOD(device_suspend, bus_generic_suspend),
  452         DEVMETHOD(device_resume, bus_generic_resume),
  453         DEVMETHOD(device_shutdown, bus_generic_shutdown),
  454 
  455         /* Bus interface */
  456         DEVMETHOD(bus_print_child, bus_generic_print_child),
  457         {0, 0}
  458 };
  459 
  460 static driver_t ehci_driver = {
  461         "ehci",
  462         ehci_methods,
  463         sizeof(struct omap_ehci_softc),
  464 };
  465 
  466 DRIVER_MODULE(omap_ehci, omap_uhh, ehci_driver, 0, 0);
Cache object: 43ff7dbe7f4a478546ed5bfab1d80f26
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FreeBSD/Linux Kernel Cross Reference sys/arm/ti/usb/omap_ehci.c

FreeBSD/Linux Kernel Cross Reference
sys/arm/ti/usb/omap_ehci.c
