The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/arm/versatile/sp804.c

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*
    2  * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
    3  * Copyright (c) 2012 Damjan Marion <dmarion@freebsd.org>
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  */
   27 
   28 #include <sys/cdefs.h>
   29 __FBSDID("$FreeBSD: releng/10.4/sys/arm/versatile/sp804.c 266152 2014-05-15 16:11:06Z ian $");
   30 
   31 #include <sys/param.h>
   32 #include <sys/systm.h>
   33 #include <sys/bus.h>
   34 #include <sys/kernel.h>
   35 #include <sys/module.h>
   36 #include <sys/malloc.h>
   37 #include <sys/rman.h>
   38 #include <sys/timeet.h>
   39 #include <sys/timetc.h>
   40 #include <sys/watchdog.h>
   41 #include <machine/bus.h>
   42 #include <machine/cpu.h>
   43 #include <machine/intr.h>
   44 
   45 #include <dev/fdt/fdt_common.h>
   46 #include <dev/ofw/openfirm.h>
   47 #include <dev/ofw/ofw_bus.h>
   48 #include <dev/ofw/ofw_bus_subr.h>
   49 
   50 #include <machine/bus.h>
   51 #include <machine/fdt.h>
   52 
   53 #define SP804_TIMER1_LOAD       0x00
   54 #define SP804_TIMER1_VALUE      0x04
   55 #define SP804_TIMER1_CONTROL    0x08
   56 #define         TIMER_CONTROL_EN        (1 << 7)
   57 #define         TIMER_CONTROL_FREERUN   (0 << 6)
   58 #define         TIMER_CONTROL_PERIODIC  (1 << 6)
   59 #define         TIMER_CONTROL_INTREN    (1 << 5)
   60 #define         TIMER_CONTROL_DIV1      (0 << 2)
   61 #define         TIMER_CONTROL_DIV16     (1 << 2)
   62 #define         TIMER_CONTROL_DIV256    (2 << 2)
   63 #define         TIMER_CONTROL_32BIT     (1 << 1)
   64 #define         TIMER_CONTROL_ONESHOT   (1 << 0)
   65 #define SP804_TIMER1_INTCLR     0x0C
   66 #define SP804_TIMER1_RIS        0x10
   67 #define SP804_TIMER1_MIS        0x14
   68 #define SP804_TIMER1_BGLOAD     0x18
   69 #define SP804_TIMER2_LOAD       0x20
   70 #define SP804_TIMER2_VALUE      0x24
   71 #define SP804_TIMER2_CONTROL    0x28
   72 #define SP804_TIMER2_INTCLR     0x2C
   73 #define SP804_TIMER2_RIS        0x30
   74 #define SP804_TIMER2_MIS        0x34
   75 #define SP804_TIMER2_BGLOAD     0x38
   76 
   77 #define SP804_PERIPH_ID0        0xFE0
   78 #define SP804_PERIPH_ID1        0xFE4
   79 #define SP804_PERIPH_ID2        0xFE8
   80 #define SP804_PERIPH_ID3        0xFEC
   81 #define SP804_PRIMECELL_ID0     0xFF0
   82 #define SP804_PRIMECELL_ID1     0xFF4
   83 #define SP804_PRIMECELL_ID2     0xFF8
   84 #define SP804_PRIMECELL_ID3     0xFFC
   85 
   86 #define DEFAULT_FREQUENCY       1000000
   87 /*
   88  * QEMU seems to have problem with full frequency
   89  */
   90 #define DEFAULT_DIVISOR         16
   91 #define DEFAULT_CONTROL_DIV     TIMER_CONTROL_DIV16
   92 
   93 struct sp804_timer_softc {
   94         struct resource*        mem_res;
   95         struct resource*        irq_res;
   96         void*                   intr_hl;
   97         uint32_t                sysclk_freq;
   98         bus_space_tag_t         bst;
   99         bus_space_handle_t      bsh;
  100         struct timecounter      tc;
  101         bool                    et_enabled;
  102         struct eventtimer       et;
  103         int                     timer_initialized;
  104 };
  105 
  106 /* Read/Write macros for Timer used as timecounter */
  107 #define sp804_timer_tc_read_4(reg)              \
  108         bus_space_read_4(sc->bst, sc->bsh, reg)
  109 
  110 #define sp804_timer_tc_write_4(reg, val)        \
  111         bus_space_write_4(sc->bst, sc->bsh, reg, val)
  112 
  113 static unsigned sp804_timer_tc_get_timecount(struct timecounter *);
  114 
  115 static unsigned
  116 sp804_timer_tc_get_timecount(struct timecounter *tc)
  117 {
  118         struct sp804_timer_softc *sc = tc->tc_priv;
  119         return 0xffffffff - sp804_timer_tc_read_4(SP804_TIMER1_VALUE);
  120 }
  121 
  122 static int
  123 sp804_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
  124 {
  125         struct sp804_timer_softc *sc = et->et_priv;
  126         uint32_t count, reg;
  127 
  128         if (first != 0) {
  129                 sc->et_enabled = 1;
  130 
  131                 count = ((uint32_t)et->et_frequency * first) >> 32;
  132 
  133                 sp804_timer_tc_write_4(SP804_TIMER2_LOAD, count);
  134                 reg = TIMER_CONTROL_32BIT | TIMER_CONTROL_INTREN |
  135                     TIMER_CONTROL_PERIODIC | DEFAULT_CONTROL_DIV |
  136                     TIMER_CONTROL_EN;
  137                 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg);
  138 
  139                 return (0);
  140         } 
  141 
  142         if (period != 0) {
  143                 panic("period");
  144         }
  145 
  146         return (EINVAL);
  147 }
  148 
  149 static int
  150 sp804_timer_stop(struct eventtimer *et)
  151 {
  152         struct sp804_timer_softc *sc = et->et_priv;
  153         uint32_t reg;
  154 
  155         sc->et_enabled = 0;
  156         reg = sp804_timer_tc_read_4(SP804_TIMER2_CONTROL);
  157         reg &= ~(TIMER_CONTROL_EN);
  158         sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg);
  159 
  160         return (0);
  161 }
  162 
  163 static int
  164 sp804_timer_intr(void *arg)
  165 {
  166         struct sp804_timer_softc *sc = arg;
  167         static uint32_t prev = 0;
  168         uint32_t x = 0;
  169 
  170         x = sp804_timer_tc_read_4(SP804_TIMER1_VALUE);
  171 
  172         prev =x ;
  173         sp804_timer_tc_write_4(SP804_TIMER2_INTCLR, 1);
  174         if (sc->et_enabled) {
  175                 if (sc->et.et_active) {
  176                         sc->et.et_event_cb(&sc->et, sc->et.et_arg);
  177                 }
  178         }
  179 
  180         return (FILTER_HANDLED);
  181 }
  182 
  183 static int
  184 sp804_timer_probe(device_t dev)
  185 {
  186 
  187         if (!ofw_bus_status_okay(dev))
  188                 return (ENXIO);
  189 
  190         if (ofw_bus_is_compatible(dev, "arm,sp804")) {
  191                 device_set_desc(dev, "SP804 System Timer");
  192                 return (BUS_PROBE_DEFAULT);
  193         }
  194 
  195         return (ENXIO);
  196 }
  197 
  198 static int
  199 sp804_timer_attach(device_t dev)
  200 {
  201         struct sp804_timer_softc *sc = device_get_softc(dev);
  202         int rid = 0;
  203         int i;
  204         uint32_t id, reg;
  205         phandle_t node;
  206         pcell_t clock;
  207 
  208         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
  209         if (sc->mem_res == NULL) {
  210                 device_printf(dev, "could not allocate memory resource\n");
  211                 return (ENXIO);
  212         }
  213 
  214         sc->bst = rman_get_bustag(sc->mem_res);
  215         sc->bsh = rman_get_bushandle(sc->mem_res);
  216 
  217         /* Request the IRQ resources */
  218         sc->irq_res =  bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
  219         if (sc->irq_res == NULL) {
  220                 device_printf(dev, "Error: could not allocate irq resources\n");
  221                 return (ENXIO);
  222         }
  223 
  224         sc->sysclk_freq = DEFAULT_FREQUENCY;
  225         /* Get the base clock frequency */
  226         node = ofw_bus_get_node(dev);
  227         if ((OF_getprop(node, "clock-frequency", &clock, sizeof(clock))) > 0) {
  228                 sc->sysclk_freq = fdt32_to_cpu(clock);
  229         }
  230 
  231         /* Setup and enable the timer */
  232         if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_CLK,
  233                         sp804_timer_intr, NULL, sc,
  234                         &sc->intr_hl) != 0) {
  235                 bus_release_resource(dev, SYS_RES_IRQ, rid,
  236                         sc->irq_res);
  237                 device_printf(dev, "Unable to setup the clock irq handler.\n");
  238                 return (ENXIO);
  239         }
  240 
  241         sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, 0);
  242         sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, 0);
  243 
  244         /*
  245          * Timer 1, timecounter
  246          */
  247         sc->tc.tc_frequency = sc->sysclk_freq;
  248         sc->tc.tc_name = "SP804 Time Counter";
  249         sc->tc.tc_get_timecount = sp804_timer_tc_get_timecount;
  250         sc->tc.tc_poll_pps = NULL;
  251         sc->tc.tc_counter_mask = ~0u;
  252         sc->tc.tc_quality = 1000;
  253         sc->tc.tc_priv = sc;
  254 
  255         sp804_timer_tc_write_4(SP804_TIMER1_VALUE, 0xffffffff);
  256         sp804_timer_tc_write_4(SP804_TIMER1_LOAD, 0xffffffff);
  257         reg = TIMER_CONTROL_PERIODIC | TIMER_CONTROL_32BIT;
  258         sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg);
  259         reg |= TIMER_CONTROL_EN;
  260         sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg);
  261         tc_init(&sc->tc);
  262 
  263         /* 
  264          * Timer 2, event timer
  265          */
  266         sc->et_enabled = 0;
  267         sc->et.et_name = malloc(64, M_DEVBUF, M_NOWAIT | M_ZERO);
  268         sprintf(sc->et.et_name, "SP804 Event Timer %d",
  269                 device_get_unit(dev));
  270         sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
  271         sc->et.et_quality = 1000;
  272         sc->et.et_frequency = sc->sysclk_freq / DEFAULT_DIVISOR;
  273         sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
  274         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
  275         sc->et.et_start = sp804_timer_start;
  276         sc->et.et_stop = sp804_timer_stop;
  277         sc->et.et_priv = sc;
  278         et_register(&sc->et);
  279 
  280         id = 0;
  281         for (i = 3; i >= 0; i--) {
  282                 id = (id << 8) | 
  283                      (sp804_timer_tc_read_4(SP804_PERIPH_ID0 + i*4) & 0xff);
  284         }
  285 
  286         device_printf(dev, "peripheral ID: %08x\n", id);
  287 
  288         id = 0;
  289         for (i = 3; i >= 0; i--) {
  290                 id = (id << 8) | 
  291                      (sp804_timer_tc_read_4(SP804_PRIMECELL_ID0 + i*4) & 0xff);
  292         }
  293 
  294         device_printf(dev, "PrimeCell ID: %08x\n", id);
  295 
  296         sc->timer_initialized = 1;
  297 
  298         return (0);
  299 }
  300 
  301 static device_method_t sp804_timer_methods[] = {
  302         DEVMETHOD(device_probe,         sp804_timer_probe),
  303         DEVMETHOD(device_attach,        sp804_timer_attach),
  304         { 0, 0 }
  305 };
  306 
  307 static driver_t sp804_timer_driver = {
  308         "timer",
  309         sp804_timer_methods,
  310         sizeof(struct sp804_timer_softc),
  311 };
  312 
  313 static devclass_t sp804_timer_devclass;
  314 
  315 DRIVER_MODULE(sp804_timer, simplebus, sp804_timer_driver, sp804_timer_devclass, 0, 0);
  316 
  317 void
  318 DELAY(int usec)
  319 {
  320         int32_t counts;
  321         uint32_t first, last;
  322         device_t timer_dev;
  323         struct sp804_timer_softc *sc;
  324         int timer_initialized = 0;
  325 
  326         timer_dev = devclass_get_device(sp804_timer_devclass, 0);
  327 
  328         if (timer_dev) {
  329                 sc = device_get_softc(timer_dev);
  330 
  331                 if (sc)
  332                         timer_initialized = sc->timer_initialized;
  333         }
  334 
  335         if (!timer_initialized) {
  336                 /*
  337                  * Timer is not initialized yet
  338                  */
  339                 for (; usec > 0; usec--)
  340                         for (counts = 200; counts > 0; counts--)
  341                                 /* Prevent gcc from optimizing  out the loop */
  342                                 cpufunc_nullop();
  343                 return;
  344         }
  345 
  346         /* Get the number of times to count */
  347         counts = usec * ((sc->tc.tc_frequency / 1000000) + 1);
  348 
  349         first = sp804_timer_tc_get_timecount(&sc->tc);
  350 
  351         while (counts > 0) {
  352                 last = sp804_timer_tc_get_timecount(&sc->tc);
  353                 if (last == first)
  354                         continue;
  355                 if (last>first) {
  356                         counts -= (int32_t)(last - first);
  357                 } else {
  358                         counts -= (int32_t)((0xFFFFFFFF - first) + last);
  359                 }
  360                 first = last;
  361         }
  362 }

Cache object: 62bd6de038831e24f4eecf2168f9be5a


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.