The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/versatile/sp804.c

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    1 /*
    2  * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
    3  * Copyright (c) 2012 Damjan Marion <dmarion@freebsd.org>
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  */
   27 
   28 #include <sys/cdefs.h>
   29 __FBSDID("$FreeBSD: releng/11.0/sys/arm/versatile/sp804.c 286783 2015-08-14 16:48:07Z ian $");
   30 
   31 #include <sys/param.h>
   32 #include <sys/systm.h>
   33 #include <sys/bus.h>
   34 #include <sys/kernel.h>
   35 #include <sys/module.h>
   36 #include <sys/malloc.h>
   37 #include <sys/rman.h>
   38 #include <sys/timeet.h>
   39 #include <sys/timetc.h>
   40 #include <sys/watchdog.h>
   41 #include <machine/bus.h>
   42 #include <machine/cpu.h>
   43 #include <machine/intr.h>
   44 
   45 #include <dev/fdt/fdt_common.h>
   46 #include <dev/ofw/openfirm.h>
   47 #include <dev/ofw/ofw_bus.h>
   48 #include <dev/ofw/ofw_bus_subr.h>
   49 
   50 #include <machine/bus.h>
   51 
   52 #define SP804_TIMER1_LOAD       0x00
   53 #define SP804_TIMER1_VALUE      0x04
   54 #define SP804_TIMER1_CONTROL    0x08
   55 #define         TIMER_CONTROL_EN        (1 << 7)
   56 #define         TIMER_CONTROL_FREERUN   (0 << 6)
   57 #define         TIMER_CONTROL_PERIODIC  (1 << 6)
   58 #define         TIMER_CONTROL_INTREN    (1 << 5)
   59 #define         TIMER_CONTROL_DIV1      (0 << 2)
   60 #define         TIMER_CONTROL_DIV16     (1 << 2)
   61 #define         TIMER_CONTROL_DIV256    (2 << 2)
   62 #define         TIMER_CONTROL_32BIT     (1 << 1)
   63 #define         TIMER_CONTROL_ONESHOT   (1 << 0)
   64 #define SP804_TIMER1_INTCLR     0x0C
   65 #define SP804_TIMER1_RIS        0x10
   66 #define SP804_TIMER1_MIS        0x14
   67 #define SP804_TIMER1_BGLOAD     0x18
   68 #define SP804_TIMER2_LOAD       0x20
   69 #define SP804_TIMER2_VALUE      0x24
   70 #define SP804_TIMER2_CONTROL    0x28
   71 #define SP804_TIMER2_INTCLR     0x2C
   72 #define SP804_TIMER2_RIS        0x30
   73 #define SP804_TIMER2_MIS        0x34
   74 #define SP804_TIMER2_BGLOAD     0x38
   75 
   76 #define SP804_PERIPH_ID0        0xFE0
   77 #define SP804_PERIPH_ID1        0xFE4
   78 #define SP804_PERIPH_ID2        0xFE8
   79 #define SP804_PERIPH_ID3        0xFEC
   80 #define SP804_PRIMECELL_ID0     0xFF0
   81 #define SP804_PRIMECELL_ID1     0xFF4
   82 #define SP804_PRIMECELL_ID2     0xFF8
   83 #define SP804_PRIMECELL_ID3     0xFFC
   84 
   85 #define DEFAULT_FREQUENCY       1000000
   86 /*
   87  * QEMU seems to have problem with full frequency
   88  */
   89 #define DEFAULT_DIVISOR         16
   90 #define DEFAULT_CONTROL_DIV     TIMER_CONTROL_DIV16
   91 
   92 struct sp804_timer_softc {
   93         struct resource*        mem_res;
   94         struct resource*        irq_res;
   95         void*                   intr_hl;
   96         uint32_t                sysclk_freq;
   97         bus_space_tag_t         bst;
   98         bus_space_handle_t      bsh;
   99         struct timecounter      tc;
  100         bool                    et_enabled;
  101         struct eventtimer       et;
  102         int                     timer_initialized;
  103 };
  104 
  105 /* Read/Write macros for Timer used as timecounter */
  106 #define sp804_timer_tc_read_4(reg)              \
  107         bus_space_read_4(sc->bst, sc->bsh, reg)
  108 
  109 #define sp804_timer_tc_write_4(reg, val)        \
  110         bus_space_write_4(sc->bst, sc->bsh, reg, val)
  111 
  112 static unsigned sp804_timer_tc_get_timecount(struct timecounter *);
  113 
  114 static unsigned
  115 sp804_timer_tc_get_timecount(struct timecounter *tc)
  116 {
  117         struct sp804_timer_softc *sc = tc->tc_priv;
  118         return 0xffffffff - sp804_timer_tc_read_4(SP804_TIMER1_VALUE);
  119 }
  120 
  121 static int
  122 sp804_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
  123 {
  124         struct sp804_timer_softc *sc = et->et_priv;
  125         uint32_t count, reg;
  126 
  127         if (first != 0) {
  128                 sc->et_enabled = 1;
  129 
  130                 count = ((uint32_t)et->et_frequency * first) >> 32;
  131 
  132                 sp804_timer_tc_write_4(SP804_TIMER2_LOAD, count);
  133                 reg = TIMER_CONTROL_32BIT | TIMER_CONTROL_INTREN |
  134                     TIMER_CONTROL_PERIODIC | DEFAULT_CONTROL_DIV |
  135                     TIMER_CONTROL_EN;
  136                 sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg);
  137 
  138                 return (0);
  139         } 
  140 
  141         if (period != 0) {
  142                 panic("period");
  143         }
  144 
  145         return (EINVAL);
  146 }
  147 
  148 static int
  149 sp804_timer_stop(struct eventtimer *et)
  150 {
  151         struct sp804_timer_softc *sc = et->et_priv;
  152         uint32_t reg;
  153 
  154         sc->et_enabled = 0;
  155         reg = sp804_timer_tc_read_4(SP804_TIMER2_CONTROL);
  156         reg &= ~(TIMER_CONTROL_EN);
  157         sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg);
  158 
  159         return (0);
  160 }
  161 
  162 static int
  163 sp804_timer_intr(void *arg)
  164 {
  165         struct sp804_timer_softc *sc = arg;
  166         static uint32_t prev = 0;
  167         uint32_t x = 0;
  168 
  169         x = sp804_timer_tc_read_4(SP804_TIMER1_VALUE);
  170 
  171         prev =x ;
  172         sp804_timer_tc_write_4(SP804_TIMER2_INTCLR, 1);
  173         if (sc->et_enabled) {
  174                 if (sc->et.et_active) {
  175                         sc->et.et_event_cb(&sc->et, sc->et.et_arg);
  176                 }
  177         }
  178 
  179         return (FILTER_HANDLED);
  180 }
  181 
  182 static int
  183 sp804_timer_probe(device_t dev)
  184 {
  185 
  186         if (!ofw_bus_status_okay(dev))
  187                 return (ENXIO);
  188 
  189         if (ofw_bus_is_compatible(dev, "arm,sp804")) {
  190                 device_set_desc(dev, "SP804 System Timer");
  191                 return (BUS_PROBE_DEFAULT);
  192         }
  193 
  194         return (ENXIO);
  195 }
  196 
  197 static int
  198 sp804_timer_attach(device_t dev)
  199 {
  200         struct sp804_timer_softc *sc = device_get_softc(dev);
  201         int rid = 0;
  202         int i;
  203         uint32_t id, reg;
  204         phandle_t node;
  205         pcell_t clock;
  206 
  207         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
  208         if (sc->mem_res == NULL) {
  209                 device_printf(dev, "could not allocate memory resource\n");
  210                 return (ENXIO);
  211         }
  212 
  213         sc->bst = rman_get_bustag(sc->mem_res);
  214         sc->bsh = rman_get_bushandle(sc->mem_res);
  215 
  216         /* Request the IRQ resources */
  217         sc->irq_res =  bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
  218         if (sc->irq_res == NULL) {
  219                 device_printf(dev, "Error: could not allocate irq resources\n");
  220                 return (ENXIO);
  221         }
  222 
  223         sc->sysclk_freq = DEFAULT_FREQUENCY;
  224         /* Get the base clock frequency */
  225         node = ofw_bus_get_node(dev);
  226         if ((OF_getprop(node, "clock-frequency", &clock, sizeof(clock))) > 0) {
  227                 sc->sysclk_freq = fdt32_to_cpu(clock);
  228         }
  229 
  230         /* Setup and enable the timer */
  231         if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_CLK,
  232                         sp804_timer_intr, NULL, sc,
  233                         &sc->intr_hl) != 0) {
  234                 bus_release_resource(dev, SYS_RES_IRQ, rid,
  235                         sc->irq_res);
  236                 device_printf(dev, "Unable to setup the clock irq handler.\n");
  237                 return (ENXIO);
  238         }
  239 
  240         sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, 0);
  241         sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, 0);
  242 
  243         /*
  244          * Timer 1, timecounter
  245          */
  246         sc->tc.tc_frequency = sc->sysclk_freq;
  247         sc->tc.tc_name = "SP804-1";
  248         sc->tc.tc_get_timecount = sp804_timer_tc_get_timecount;
  249         sc->tc.tc_poll_pps = NULL;
  250         sc->tc.tc_counter_mask = ~0u;
  251         sc->tc.tc_quality = 1000;
  252         sc->tc.tc_priv = sc;
  253 
  254         sp804_timer_tc_write_4(SP804_TIMER1_VALUE, 0xffffffff);
  255         sp804_timer_tc_write_4(SP804_TIMER1_LOAD, 0xffffffff);
  256         reg = TIMER_CONTROL_PERIODIC | TIMER_CONTROL_32BIT;
  257         sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg);
  258         reg |= TIMER_CONTROL_EN;
  259         sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg);
  260         tc_init(&sc->tc);
  261 
  262         /* 
  263          * Timer 2, event timer
  264          */
  265         sc->et_enabled = 0;
  266         sc->et.et_name = "SP804-2";
  267         sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
  268         sc->et.et_quality = 1000;
  269         sc->et.et_frequency = sc->sysclk_freq / DEFAULT_DIVISOR;
  270         sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
  271         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
  272         sc->et.et_start = sp804_timer_start;
  273         sc->et.et_stop = sp804_timer_stop;
  274         sc->et.et_priv = sc;
  275         et_register(&sc->et);
  276 
  277         id = 0;
  278         for (i = 3; i >= 0; i--) {
  279                 id = (id << 8) | 
  280                      (sp804_timer_tc_read_4(SP804_PERIPH_ID0 + i*4) & 0xff);
  281         }
  282 
  283         device_printf(dev, "peripheral ID: %08x\n", id);
  284 
  285         id = 0;
  286         for (i = 3; i >= 0; i--) {
  287                 id = (id << 8) | 
  288                      (sp804_timer_tc_read_4(SP804_PRIMECELL_ID0 + i*4) & 0xff);
  289         }
  290 
  291         device_printf(dev, "PrimeCell ID: %08x\n", id);
  292 
  293         sc->timer_initialized = 1;
  294 
  295         return (0);
  296 }
  297 
  298 static device_method_t sp804_timer_methods[] = {
  299         DEVMETHOD(device_probe,         sp804_timer_probe),
  300         DEVMETHOD(device_attach,        sp804_timer_attach),
  301         { 0, 0 }
  302 };
  303 
  304 static driver_t sp804_timer_driver = {
  305         "timer",
  306         sp804_timer_methods,
  307         sizeof(struct sp804_timer_softc),
  308 };
  309 
  310 static devclass_t sp804_timer_devclass;
  311 
  312 DRIVER_MODULE(sp804_timer, simplebus, sp804_timer_driver, sp804_timer_devclass, 0, 0);
  313 
  314 void
  315 DELAY(int usec)
  316 {
  317         int32_t counts;
  318         uint32_t first, last;
  319         device_t timer_dev;
  320         struct sp804_timer_softc *sc;
  321         int timer_initialized = 0;
  322 
  323         timer_dev = devclass_get_device(sp804_timer_devclass, 0);
  324 
  325         if (timer_dev) {
  326                 sc = device_get_softc(timer_dev);
  327 
  328                 if (sc)
  329                         timer_initialized = sc->timer_initialized;
  330         }
  331 
  332         if (!timer_initialized) {
  333                 /*
  334                  * Timer is not initialized yet
  335                  */
  336                 for (; usec > 0; usec--)
  337                         for (counts = 200; counts > 0; counts--)
  338                                 /* Prevent gcc from optimizing  out the loop */
  339                                 cpufunc_nullop();
  340                 return;
  341         }
  342 
  343         /* Get the number of times to count */
  344         counts = usec * ((sc->tc.tc_frequency / 1000000) + 1);
  345 
  346         first = sp804_timer_tc_get_timecount(&sc->tc);
  347 
  348         while (counts > 0) {
  349                 last = sp804_timer_tc_get_timecount(&sc->tc);
  350                 if (last == first)
  351                         continue;
  352                 if (last>first) {
  353                         counts -= (int32_t)(last - first);
  354                 } else {
  355                         counts -= (int32_t)((0xFFFFFFFF - first) + last);
  356                 }
  357                 first = last;
  358         }
  359 }

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