The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/arm/versatile/versatile_pci.c

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*
    2  * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: releng/10.1/sys/arm/versatile/versatile_pci.c 266152 2014-05-15 16:11:06Z ian $");
   29 
   30 #include <sys/param.h>
   31 #include <sys/systm.h>
   32 #include <sys/bus.h>
   33 #include <sys/kernel.h>
   34 #include <sys/module.h>
   35 #include <sys/malloc.h>
   36 #include <sys/rman.h>
   37 #include <sys/watchdog.h>
   38 #include <machine/bus.h>
   39 #include <machine/cpu.h>
   40 #include <machine/intr.h>
   41 
   42 #include <dev/pci/pcivar.h>
   43 #include <dev/pci/pcireg.h>
   44 
   45 #include <dev/pci/pcib_private.h>
   46 #include "pcib_if.h"
   47 
   48 #include <dev/fdt/fdt_common.h>
   49 #include <dev/ofw/openfirm.h>
   50 #include <dev/ofw/ofw_bus.h>
   51 #include <dev/ofw/ofw_bus_subr.h>
   52 
   53 #include <machine/bus.h>
   54 #include <machine/fdt.h>
   55 
   56 #include <arm/versatile/versatile_pci_bus_space.h>
   57 
   58 #define MEM_SYS         0
   59 #define MEM_CORE        1
   60 #define MEM_BASE        2
   61 #define MEM_CONF_BASE   3
   62 #define MEM_REGIONS     4
   63 
   64 #define SYS_PCICTL              0x00
   65 
   66 #define PCI_CORE_IMAP0          0x00
   67 #define PCI_CORE_IMAP1          0x04
   68 #define PCI_CORE_IMAP2          0x08
   69 #define PCI_CORE_SELFID         0x0C
   70 #define PCI_CORE_SMAP0          0x10
   71 #define PCI_CORE_SMAP1          0x14
   72 #define PCI_CORE_SMAP2          0x18
   73 
   74 #define VERSATILE_PCI_DEV       0x030010ee
   75 #define VERSATILE_PCI_CLASS     0x0b400000
   76 
   77 #define PCI_IO_WINDOW           0x44000000
   78 #define PCI_IO_SIZE             0x0c000000
   79 #define PCI_NPREFETCH_WINDOW    0x50000000
   80 #define PCI_NPREFETCH_SIZE      0x10000000
   81 #define PCI_PREFETCH_WINDOW     0x60000000
   82 #define PCI_PREFETCH_SIZE       0x10000000
   83 
   84 #define VERSATILE_PCI_IRQ_START 27
   85 #define VERSATILE_PCI_IRQ_END   30
   86 
   87 #ifdef DEBUG
   88 #define dprintf(fmt, args...) do { printf("%s(): ", __func__);   \
   89     printf(fmt,##args); } while (0)
   90 #else
   91 #define dprintf(fmt, args...)
   92 #endif
   93 
   94 
   95 #define versatile_pci_sys_read_4(reg)   \
   96         bus_read_4(sc->mem_res[MEM_SYS], (reg))
   97 #define versatile_pci_sys_write_4(reg, val)     \
   98         bus_write_4(sc->mem_res[MEM_SYS], (reg), (val))
   99 
  100 #define versatile_pci_core_read_4(reg)  \
  101         bus_read_4(sc->mem_res[MEM_CORE], (reg))
  102 #define versatile_pci_core_write_4(reg, val)    \
  103         bus_write_4(sc->mem_res[MEM_CORE], (reg), (val))
  104 
  105 #define versatile_pci_read_4(reg)       \
  106         bus_read_4(sc->mem_res[MEM_BASE], (reg))
  107 #define versatile_pci_write_4(reg, val) \
  108         bus_write_4(sc->mem_res[MEM_BASE], (reg), (val))
  109 
  110 #define versatile_pci_conf_read_4(reg)  \
  111         bus_read_4(sc->mem_res[MEM_CONF_BASE], (reg))
  112 #define versatile_pci_conf_write_4(reg, val)    \
  113         bus_write_4(sc->mem_res[MEM_CONF_BASE], (reg), (val))
  114 #define versatile_pci_conf_write_2(reg, val)    \
  115         bus_write_2(sc->mem_res[MEM_CONF_BASE], (reg), (val))
  116 #define versatile_pci_conf_write_1(reg, val)    \
  117         bus_write_1(sc->mem_res[MEM_CONF_BASE], (reg), (val))
  118 
  119 struct versatile_pci_softc {
  120         struct resource*        mem_res[MEM_REGIONS];
  121         struct resource*        irq_res;
  122         void*                   intr_hl;
  123 
  124         int                     pcib_slot;
  125 
  126         /* Bus part */
  127         int                     busno;
  128         struct rman             io_rman;
  129         struct rman             irq_rman;
  130         struct rman             mem_rman;
  131 
  132         struct mtx              mtx;
  133 };
  134 
  135 static struct resource_spec versatile_pci_mem_spec[] = {
  136         { SYS_RES_MEMORY, 0, RF_ACTIVE },
  137         { SYS_RES_MEMORY, 1, RF_ACTIVE },
  138         { SYS_RES_MEMORY, 2, RF_ACTIVE },
  139         { SYS_RES_MEMORY, 3, RF_ACTIVE },
  140         { -1, 0, 0 }
  141 };
  142 
  143 static int
  144 versatile_pci_probe(device_t dev)
  145 {
  146 
  147         if (!ofw_bus_status_okay(dev))
  148                 return (ENXIO);
  149 
  150         if (ofw_bus_is_compatible(dev, "versatile,pci")) {
  151                 device_set_desc(dev, "Versatile PCI controller");
  152                 return (BUS_PROBE_DEFAULT);
  153         }
  154 
  155         return (ENXIO);
  156 }
  157 
  158 static int
  159 versatile_pci_attach(device_t dev)
  160 {
  161         struct versatile_pci_softc *sc = device_get_softc(dev);
  162         int err;
  163         int slot;
  164         uint32_t vendordev_id, class_id;
  165         uint32_t val;
  166 
  167         /* Request memory resources */
  168         err = bus_alloc_resources(dev, versatile_pci_mem_spec,
  169                 sc->mem_res);
  170         if (err) {
  171                 device_printf(dev, "Error: could not allocate memory resources\n");
  172                 return (ENXIO);
  173         }
  174 
  175         /*
  176          * Setup memory windows
  177          */
  178         versatile_pci_core_write_4(PCI_CORE_IMAP0, (PCI_IO_WINDOW >> 28));
  179         versatile_pci_core_write_4(PCI_CORE_IMAP1, (PCI_NPREFETCH_WINDOW >> 28));
  180         versatile_pci_core_write_4(PCI_CORE_IMAP2, (PCI_PREFETCH_WINDOW >> 28));
  181 
  182         /*
  183          * XXX: this is SDRAM offset >> 28
  184          * Unused as of QEMU 1.5
  185          */
  186         versatile_pci_core_write_4(PCI_CORE_SMAP0, (PCI_IO_WINDOW >> 28));
  187         versatile_pci_core_write_4(PCI_CORE_SMAP1, (PCI_NPREFETCH_WINDOW >> 28));
  188         versatile_pci_core_write_4(PCI_CORE_SMAP2, (PCI_NPREFETCH_WINDOW >> 28));
  189 
  190         versatile_pci_sys_write_4(SYS_PCICTL, 1);
  191 
  192         for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
  193                 vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
  194                 class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
  195                 if ((vendordev_id == VERSATILE_PCI_DEV) &&
  196                     (class_id == VERSATILE_PCI_CLASS))
  197                         break;
  198         }
  199 
  200         if (slot == (PCI_SLOTMAX + 1)) {
  201                 bus_release_resources(dev, versatile_pci_mem_spec,
  202                     sc->mem_res);
  203                 device_printf(dev, "Versatile PCI core not found\n");
  204                 return (ENXIO);
  205         }
  206 
  207         sc->pcib_slot = slot;
  208         device_printf(dev, "PCI core at slot #%d\n", slot);
  209 
  210         versatile_pci_core_write_4(PCI_CORE_SELFID, slot);
  211         val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
  212         val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_MWRICEN);
  213         versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
  214 
  215         /* Again SDRAM start >> 28  */
  216         versatile_pci_write_4((slot << 11) + PCIR_BAR(0), 0);
  217         versatile_pci_write_4((slot << 11) + PCIR_BAR(1), 0);
  218         versatile_pci_write_4((slot << 11) + PCIR_BAR(2), 0);
  219 
  220         /* Prepare resource managers */
  221         sc->mem_rman.rm_type = RMAN_ARRAY;
  222         sc->mem_rman.rm_descr = "versatile PCI memory window";
  223         if (rman_init(&sc->mem_rman) != 0 || 
  224             rman_manage_region(&sc->mem_rman, PCI_NPREFETCH_WINDOW, 
  225                 PCI_NPREFETCH_WINDOW + PCI_NPREFETCH_SIZE - 1) != 0) {
  226                 panic("versatile_pci_attach: failed to set up memory rman");
  227         }
  228 
  229         bootverbose = 1;
  230         sc->io_rman.rm_type = RMAN_ARRAY;
  231         sc->io_rman.rm_descr = "versatile PCI IO window";
  232         if (rman_init(&sc->io_rman) != 0 || 
  233             rman_manage_region(&sc->io_rman, PCI_IO_WINDOW, 
  234                 PCI_IO_WINDOW + PCI_IO_SIZE - 1) != 0) {
  235                 panic("versatile_pci_attach: failed to set up I/O rman");
  236         }
  237 
  238         sc->irq_rman.rm_type = RMAN_ARRAY;
  239         sc->irq_rman.rm_descr = "versatile PCI IRQs";
  240         if (rman_init(&sc->irq_rman) != 0 ||
  241             rman_manage_region(&sc->irq_rman, VERSATILE_PCI_IRQ_START, 
  242                 VERSATILE_PCI_IRQ_END) != 0) {
  243                 panic("versatile_pci_attach: failed to set up IRQ rman");
  244         }
  245 
  246         mtx_init(&sc->mtx, device_get_nameunit(dev), "versatilepci",
  247                         MTX_SPIN);
  248 
  249         val = versatile_pci_conf_read_4((12 << 11) + PCIR_COMMAND);
  250 
  251         for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
  252                 vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
  253                 class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
  254 
  255                 if (slot == sc->pcib_slot)
  256                         continue;
  257 
  258                 if ((vendordev_id == 0xffffffff) &&
  259                     (class_id == 0xffffffff))
  260                         continue;
  261 
  262                 val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
  263                 val |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
  264                 versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
  265         }
  266 
  267         device_add_child(dev, "pci", 0);
  268         return (bus_generic_attach(dev));
  269 }
  270 
  271 static int
  272 versatile_pci_read_ivar(device_t dev, device_t child, int which,
  273     uintptr_t *result)
  274 {
  275         struct versatile_pci_softc *sc = device_get_softc(dev);
  276 
  277         switch (which) {
  278         case PCIB_IVAR_DOMAIN:
  279                 *result = 0;
  280                 return (0);
  281         case PCIB_IVAR_BUS:
  282                 *result = sc->busno;
  283                 return (0);
  284         }
  285 
  286         return (ENOENT);
  287 }
  288 
  289 static int
  290 versatile_pci_write_ivar(device_t dev, device_t child, int which,
  291     uintptr_t result)
  292 {
  293         struct versatile_pci_softc * sc = device_get_softc(dev);
  294 
  295         switch (which) {
  296         case PCIB_IVAR_BUS:
  297                 sc->busno = result;
  298                 return (0);
  299         }
  300 
  301         return (ENOENT);
  302 }
  303 
  304 static struct resource *
  305 versatile_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
  306     u_long start, u_long end, u_long count, u_int flags)
  307 {
  308 
  309         struct versatile_pci_softc *sc = device_get_softc(bus);
  310         struct resource *rv;
  311         struct rman *rm;
  312 
  313         dprintf("Alloc resources %d, %08lx..%08lx, %ld\n", type, start, end, count);
  314 
  315         switch (type) {
  316         case SYS_RES_IOPORT:
  317                 rm = &sc->io_rman;
  318                 break;
  319         case SYS_RES_IRQ:
  320                 rm = &sc->irq_rman;
  321                 break;
  322         case SYS_RES_MEMORY:
  323                 rm = &sc->mem_rman;
  324                 break;
  325         default:
  326                 return (NULL);
  327         }
  328 
  329         rv = rman_reserve_resource(rm, start, end, count, flags, child);
  330 
  331         if (rv == NULL)
  332                 return (NULL);
  333 
  334         rman_set_rid(rv, *rid);
  335 
  336         if (flags & RF_ACTIVE) {
  337                 if (bus_activate_resource(child, type, *rid, rv)) {
  338                         rman_release_resource(rv);
  339                         return (NULL);
  340                 }
  341         }
  342         return (rv);
  343 }
  344 
  345 static int
  346 versatile_pci_activate_resource(device_t bus, device_t child, int type, int rid,
  347     struct resource *r)
  348 {
  349         vm_offset_t vaddr;
  350         int res;
  351 
  352         switch(type) {
  353         case SYS_RES_MEMORY:
  354         case SYS_RES_IOPORT:
  355                 vaddr = (vm_offset_t)pmap_mapdev(rman_get_start(r),
  356                                 rman_get_size(r));
  357                 rman_set_bushandle(r, vaddr);
  358                 rman_set_bustag(r, versatile_bus_space_pcimem);
  359                 res = rman_activate_resource(r);
  360                 break;
  361         case SYS_RES_IRQ:
  362                 res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
  363                     child, type, rid, r));
  364                 break;
  365         default:
  366                 res = ENXIO;
  367                 break;
  368         }
  369 
  370         return (res);
  371 }
  372 
  373 static int
  374 versatile_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
  375             int flags, driver_filter_t *filt, driver_intr_t *handler,
  376             void *arg, void **cookiep)
  377 {
  378 
  379         return BUS_SETUP_INTR(device_get_parent(bus), bus, ires, flags,
  380             filt, handler, arg, cookiep);
  381 }
  382 
  383 static int
  384 versatile_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
  385     void *cookie)
  386 {
  387 
  388         return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, ires, cookie);
  389 }
  390 
  391 
  392 
  393 static int
  394 versatile_pci_maxslots(device_t dev)
  395 {
  396 
  397         return (PCI_SLOTMAX);
  398 }
  399 
  400 static int
  401 versatile_pci_route_interrupt(device_t pcib, device_t device, int pin)
  402 {
  403 
  404         return (27 + ((pci_get_slot(device) + pin - 1) & 3));
  405 }
  406 
  407 static uint32_t
  408 versatile_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
  409     u_int reg, int bytes)
  410 {
  411         struct versatile_pci_softc *sc = device_get_softc(dev);
  412         uint32_t data;
  413         uint32_t shift, mask;
  414         uint32_t addr;
  415 
  416         if (sc->pcib_slot == slot) {
  417                 switch (bytes) {
  418                         case 4: 
  419                                 return (0xffffffff);
  420                                 break;
  421                         case 2:
  422                                 return (0xffff);
  423                                 break;
  424                         case 1:
  425                                 return (0xff);
  426                                 break;
  427                 }
  428         }
  429 
  430         addr = (bus << 16) | (slot << 11) | (func << 8) | (reg & ~3);
  431 
  432         /* register access is 32-bit aligned */
  433         shift = (reg & 3) * 8;
  434 
  435         /* Create a mask based on the width, post-shift */
  436         if (bytes == 2)
  437                 mask = 0xffff;
  438         else if (bytes == 1)
  439                 mask = 0xff;
  440         else
  441                 mask = 0xffffffff;
  442 
  443         dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, 
  444             func, reg, bytes);
  445 
  446         mtx_lock_spin(&sc->mtx);
  447         data = versatile_pci_conf_read_4(addr);
  448         mtx_unlock_spin(&sc->mtx);
  449 
  450         /* get request bytes from 32-bit word */
  451         data = (data >> shift) & mask;
  452 
  453         dprintf("%s: read 0x%x\n", __func__, data);
  454 
  455         return (data);
  456 }
  457 
  458 static void
  459 versatile_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
  460     u_int reg, uint32_t data, int bytes)
  461 {
  462 
  463         struct versatile_pci_softc *sc = device_get_softc(dev);
  464         uint32_t addr;
  465 
  466         dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
  467             func, reg, bytes);
  468 
  469         if (sc->pcib_slot == slot)
  470                 return;
  471 
  472         addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
  473         mtx_lock_spin(&sc->mtx);
  474         switch (bytes) {
  475                 case 4: 
  476                         versatile_pci_conf_write_4(addr, data);
  477                         break;
  478                 case 2:
  479                         versatile_pci_conf_write_2(addr, data);
  480                         break;
  481                 case 1:
  482                         versatile_pci_conf_write_1(addr, data);
  483                         break;
  484         }
  485         mtx_unlock_spin(&sc->mtx);
  486 }
  487 
  488 static device_method_t versatile_pci_methods[] = {
  489         DEVMETHOD(device_probe,         versatile_pci_probe),
  490         DEVMETHOD(device_attach,        versatile_pci_attach),
  491 
  492         /* Bus interface */
  493         DEVMETHOD(bus_read_ivar,        versatile_pci_read_ivar),
  494         DEVMETHOD(bus_write_ivar,       versatile_pci_write_ivar),
  495         DEVMETHOD(bus_alloc_resource,   versatile_pci_alloc_resource),
  496         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
  497         DEVMETHOD(bus_activate_resource, versatile_pci_activate_resource),
  498         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
  499         DEVMETHOD(bus_setup_intr,       versatile_pci_setup_intr),
  500         DEVMETHOD(bus_teardown_intr,    versatile_pci_teardown_intr),
  501 
  502         /* pcib interface */
  503         DEVMETHOD(pcib_maxslots,        versatile_pci_maxslots),
  504         DEVMETHOD(pcib_read_config,     versatile_pci_read_config),
  505         DEVMETHOD(pcib_write_config,    versatile_pci_write_config),
  506         DEVMETHOD(pcib_route_interrupt, versatile_pci_route_interrupt),
  507 
  508         DEVMETHOD_END
  509 };
  510 
  511 static driver_t versatile_pci_driver = {
  512         "pcib",
  513         versatile_pci_methods,
  514         sizeof(struct versatile_pci_softc),
  515 };
  516 
  517 static devclass_t versatile_pci_devclass;
  518 
  519 DRIVER_MODULE(versatile_pci, simplebus, versatile_pci_driver, versatile_pci_devclass, 0, 0);

Cache object: 26403072de824e372d0b6873d6dd88d2


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.