The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/versatile/versatile_pci.c

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    1 /*
    2  * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: releng/10.3/sys/arm/versatile/versatile_pci.c 278727 2015-02-13 22:32:02Z ian $");
   29 
   30 #include <sys/param.h>
   31 #include <sys/systm.h>
   32 #include <sys/bus.h>
   33 #include <sys/kernel.h>
   34 #include <sys/module.h>
   35 #include <sys/malloc.h>
   36 #include <sys/rman.h>
   37 #include <sys/watchdog.h>
   38 #include <machine/bus.h>
   39 #include <machine/cpu.h>
   40 #include <machine/intr.h>
   41 
   42 #include <dev/pci/pcivar.h>
   43 #include <dev/pci/pcireg.h>
   44 
   45 #include <dev/pci/pcib_private.h>
   46 #include "pcib_if.h"
   47 
   48 #include <dev/fdt/fdt_common.h>
   49 #include <dev/ofw/openfirm.h>
   50 #include <dev/ofw/ofw_bus.h>
   51 #include <dev/ofw/ofw_bus_subr.h>
   52 
   53 #include <machine/bus.h>
   54 #include <machine/fdt.h>
   55 
   56 #define MEM_SYS         0
   57 #define MEM_CORE        1
   58 #define MEM_BASE        2
   59 #define MEM_CONF_BASE   3
   60 #define MEM_REGIONS     4
   61 
   62 #define SYS_PCICTL              0x00
   63 
   64 #define PCI_CORE_IMAP0          0x00
   65 #define PCI_CORE_IMAP1          0x04
   66 #define PCI_CORE_IMAP2          0x08
   67 #define PCI_CORE_SELFID         0x0C
   68 #define PCI_CORE_SMAP0          0x10
   69 #define PCI_CORE_SMAP1          0x14
   70 #define PCI_CORE_SMAP2          0x18
   71 
   72 #define VERSATILE_PCI_DEV       0x030010ee
   73 #define VERSATILE_PCI_CLASS     0x0b400000
   74 
   75 #define PCI_IO_WINDOW           0x44000000
   76 #define PCI_IO_SIZE             0x0c000000
   77 #define PCI_NPREFETCH_WINDOW    0x50000000
   78 #define PCI_NPREFETCH_SIZE      0x10000000
   79 #define PCI_PREFETCH_WINDOW     0x60000000
   80 #define PCI_PREFETCH_SIZE       0x10000000
   81 
   82 #define VERSATILE_PCI_IRQ_START 27
   83 #define VERSATILE_PCI_IRQ_END   30
   84 
   85 #ifdef DEBUG
   86 #define dprintf(fmt, args...) do { printf("%s(): ", __func__);   \
   87     printf(fmt,##args); } while (0)
   88 #else
   89 #define dprintf(fmt, args...)
   90 #endif
   91 
   92 
   93 #define versatile_pci_sys_read_4(reg)   \
   94         bus_read_4(sc->mem_res[MEM_SYS], (reg))
   95 #define versatile_pci_sys_write_4(reg, val)     \
   96         bus_write_4(sc->mem_res[MEM_SYS], (reg), (val))
   97 
   98 #define versatile_pci_core_read_4(reg)  \
   99         bus_read_4(sc->mem_res[MEM_CORE], (reg))
  100 #define versatile_pci_core_write_4(reg, val)    \
  101         bus_write_4(sc->mem_res[MEM_CORE], (reg), (val))
  102 
  103 #define versatile_pci_read_4(reg)       \
  104         bus_read_4(sc->mem_res[MEM_BASE], (reg))
  105 #define versatile_pci_write_4(reg, val) \
  106         bus_write_4(sc->mem_res[MEM_BASE], (reg), (val))
  107 
  108 #define versatile_pci_conf_read_4(reg)  \
  109         bus_read_4(sc->mem_res[MEM_CONF_BASE], (reg))
  110 #define versatile_pci_conf_write_4(reg, val)    \
  111         bus_write_4(sc->mem_res[MEM_CONF_BASE], (reg), (val))
  112 #define versatile_pci_conf_write_2(reg, val)    \
  113         bus_write_2(sc->mem_res[MEM_CONF_BASE], (reg), (val))
  114 #define versatile_pci_conf_write_1(reg, val)    \
  115         bus_write_1(sc->mem_res[MEM_CONF_BASE], (reg), (val))
  116 
  117 struct versatile_pci_softc {
  118         struct resource*        mem_res[MEM_REGIONS];
  119         struct resource*        irq_res;
  120         void*                   intr_hl;
  121 
  122         int                     pcib_slot;
  123 
  124         /* Bus part */
  125         int                     busno;
  126         struct rman             io_rman;
  127         struct rman             irq_rman;
  128         struct rman             mem_rman;
  129 
  130         struct mtx              mtx;
  131 };
  132 
  133 static struct resource_spec versatile_pci_mem_spec[] = {
  134         { SYS_RES_MEMORY, 0, RF_ACTIVE },
  135         { SYS_RES_MEMORY, 1, RF_ACTIVE },
  136         { SYS_RES_MEMORY, 2, RF_ACTIVE },
  137         { SYS_RES_MEMORY, 3, RF_ACTIVE },
  138         { -1, 0, 0 }
  139 };
  140 
  141 static int
  142 versatile_pci_probe(device_t dev)
  143 {
  144 
  145         if (!ofw_bus_status_okay(dev))
  146                 return (ENXIO);
  147 
  148         if (ofw_bus_is_compatible(dev, "versatile,pci")) {
  149                 device_set_desc(dev, "Versatile PCI controller");
  150                 return (BUS_PROBE_DEFAULT);
  151         }
  152 
  153         return (ENXIO);
  154 }
  155 
  156 static int
  157 versatile_pci_attach(device_t dev)
  158 {
  159         struct versatile_pci_softc *sc = device_get_softc(dev);
  160         int err;
  161         int slot;
  162         uint32_t vendordev_id, class_id;
  163         uint32_t val;
  164 
  165         /* Request memory resources */
  166         err = bus_alloc_resources(dev, versatile_pci_mem_spec,
  167                 sc->mem_res);
  168         if (err) {
  169                 device_printf(dev, "Error: could not allocate memory resources\n");
  170                 return (ENXIO);
  171         }
  172 
  173         /*
  174          * Setup memory windows
  175          */
  176         versatile_pci_core_write_4(PCI_CORE_IMAP0, (PCI_IO_WINDOW >> 28));
  177         versatile_pci_core_write_4(PCI_CORE_IMAP1, (PCI_NPREFETCH_WINDOW >> 28));
  178         versatile_pci_core_write_4(PCI_CORE_IMAP2, (PCI_PREFETCH_WINDOW >> 28));
  179 
  180         /*
  181          * XXX: this is SDRAM offset >> 28
  182          * Unused as of QEMU 1.5
  183          */
  184         versatile_pci_core_write_4(PCI_CORE_SMAP0, (PCI_IO_WINDOW >> 28));
  185         versatile_pci_core_write_4(PCI_CORE_SMAP1, (PCI_NPREFETCH_WINDOW >> 28));
  186         versatile_pci_core_write_4(PCI_CORE_SMAP2, (PCI_NPREFETCH_WINDOW >> 28));
  187 
  188         versatile_pci_sys_write_4(SYS_PCICTL, 1);
  189 
  190         for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
  191                 vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
  192                 class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
  193                 if ((vendordev_id == VERSATILE_PCI_DEV) &&
  194                     (class_id == VERSATILE_PCI_CLASS))
  195                         break;
  196         }
  197 
  198         if (slot == (PCI_SLOTMAX + 1)) {
  199                 bus_release_resources(dev, versatile_pci_mem_spec,
  200                     sc->mem_res);
  201                 device_printf(dev, "Versatile PCI core not found\n");
  202                 return (ENXIO);
  203         }
  204 
  205         sc->pcib_slot = slot;
  206         device_printf(dev, "PCI core at slot #%d\n", slot);
  207 
  208         versatile_pci_core_write_4(PCI_CORE_SELFID, slot);
  209         val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
  210         val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_MWRICEN);
  211         versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
  212 
  213         /* Again SDRAM start >> 28  */
  214         versatile_pci_write_4((slot << 11) + PCIR_BAR(0), 0);
  215         versatile_pci_write_4((slot << 11) + PCIR_BAR(1), 0);
  216         versatile_pci_write_4((slot << 11) + PCIR_BAR(2), 0);
  217 
  218         /* Prepare resource managers */
  219         sc->mem_rman.rm_type = RMAN_ARRAY;
  220         sc->mem_rman.rm_descr = "versatile PCI memory window";
  221         if (rman_init(&sc->mem_rman) != 0 || 
  222             rman_manage_region(&sc->mem_rman, PCI_NPREFETCH_WINDOW, 
  223                 PCI_NPREFETCH_WINDOW + PCI_NPREFETCH_SIZE - 1) != 0) {
  224                 panic("versatile_pci_attach: failed to set up memory rman");
  225         }
  226 
  227         bootverbose = 1;
  228         sc->io_rman.rm_type = RMAN_ARRAY;
  229         sc->io_rman.rm_descr = "versatile PCI IO window";
  230         if (rman_init(&sc->io_rman) != 0 || 
  231             rman_manage_region(&sc->io_rman, PCI_IO_WINDOW, 
  232                 PCI_IO_WINDOW + PCI_IO_SIZE - 1) != 0) {
  233                 panic("versatile_pci_attach: failed to set up I/O rman");
  234         }
  235 
  236         sc->irq_rman.rm_type = RMAN_ARRAY;
  237         sc->irq_rman.rm_descr = "versatile PCI IRQs";
  238         if (rman_init(&sc->irq_rman) != 0 ||
  239             rman_manage_region(&sc->irq_rman, VERSATILE_PCI_IRQ_START, 
  240                 VERSATILE_PCI_IRQ_END) != 0) {
  241                 panic("versatile_pci_attach: failed to set up IRQ rman");
  242         }
  243 
  244         mtx_init(&sc->mtx, device_get_nameunit(dev), "versatilepci",
  245                         MTX_SPIN);
  246 
  247         val = versatile_pci_conf_read_4((12 << 11) + PCIR_COMMAND);
  248 
  249         for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
  250                 vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
  251                 class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
  252 
  253                 if (slot == sc->pcib_slot)
  254                         continue;
  255 
  256                 if ((vendordev_id == 0xffffffff) &&
  257                     (class_id == 0xffffffff))
  258                         continue;
  259 
  260                 val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
  261                 val |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
  262                 versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
  263         }
  264 
  265         device_add_child(dev, "pci", 0);
  266         return (bus_generic_attach(dev));
  267 }
  268 
  269 static int
  270 versatile_pci_read_ivar(device_t dev, device_t child, int which,
  271     uintptr_t *result)
  272 {
  273         struct versatile_pci_softc *sc = device_get_softc(dev);
  274 
  275         switch (which) {
  276         case PCIB_IVAR_DOMAIN:
  277                 *result = 0;
  278                 return (0);
  279         case PCIB_IVAR_BUS:
  280                 *result = sc->busno;
  281                 return (0);
  282         }
  283 
  284         return (ENOENT);
  285 }
  286 
  287 static int
  288 versatile_pci_write_ivar(device_t dev, device_t child, int which,
  289     uintptr_t result)
  290 {
  291         struct versatile_pci_softc * sc = device_get_softc(dev);
  292 
  293         switch (which) {
  294         case PCIB_IVAR_BUS:
  295                 sc->busno = result;
  296                 return (0);
  297         }
  298 
  299         return (ENOENT);
  300 }
  301 
  302 static struct resource *
  303 versatile_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
  304     u_long start, u_long end, u_long count, u_int flags)
  305 {
  306 
  307         struct versatile_pci_softc *sc = device_get_softc(bus);
  308         struct resource *rv;
  309         struct rman *rm;
  310 
  311         dprintf("Alloc resources %d, %08lx..%08lx, %ld\n", type, start, end, count);
  312 
  313         switch (type) {
  314         case SYS_RES_IOPORT:
  315                 rm = &sc->io_rman;
  316                 break;
  317         case SYS_RES_IRQ:
  318                 rm = &sc->irq_rman;
  319                 break;
  320         case SYS_RES_MEMORY:
  321                 rm = &sc->mem_rman;
  322                 break;
  323         default:
  324                 return (NULL);
  325         }
  326 
  327         rv = rman_reserve_resource(rm, start, end, count, flags, child);
  328 
  329         if (rv == NULL)
  330                 return (NULL);
  331 
  332         rman_set_rid(rv, *rid);
  333 
  334         if (flags & RF_ACTIVE) {
  335                 if (bus_activate_resource(child, type, *rid, rv)) {
  336                         rman_release_resource(rv);
  337                         return (NULL);
  338                 }
  339         }
  340         return (rv);
  341 }
  342 
  343 static int
  344 versatile_pci_activate_resource(device_t bus, device_t child, int type, int rid,
  345     struct resource *r)
  346 {
  347         vm_offset_t vaddr;
  348         int res;
  349 
  350         switch(type) {
  351         case SYS_RES_MEMORY:
  352         case SYS_RES_IOPORT:
  353                 vaddr = (vm_offset_t)pmap_mapdev(rman_get_start(r),
  354                                 rman_get_size(r));
  355                 rman_set_bushandle(r, vaddr);
  356                 rman_set_bustag(r, arm_base_bs_tag);
  357                 res = rman_activate_resource(r);
  358                 break;
  359         case SYS_RES_IRQ:
  360                 res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
  361                     child, type, rid, r));
  362                 break;
  363         default:
  364                 res = ENXIO;
  365                 break;
  366         }
  367 
  368         return (res);
  369 }
  370 
  371 static int
  372 versatile_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
  373             int flags, driver_filter_t *filt, driver_intr_t *handler,
  374             void *arg, void **cookiep)
  375 {
  376 
  377         return BUS_SETUP_INTR(device_get_parent(bus), bus, ires, flags,
  378             filt, handler, arg, cookiep);
  379 }
  380 
  381 static int
  382 versatile_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
  383     void *cookie)
  384 {
  385 
  386         return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, ires, cookie);
  387 }
  388 
  389 
  390 
  391 static int
  392 versatile_pci_maxslots(device_t dev)
  393 {
  394 
  395         return (PCI_SLOTMAX);
  396 }
  397 
  398 static int
  399 versatile_pci_route_interrupt(device_t pcib, device_t device, int pin)
  400 {
  401 
  402         return (27 + ((pci_get_slot(device) + pin - 1) & 3));
  403 }
  404 
  405 static uint32_t
  406 versatile_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
  407     u_int reg, int bytes)
  408 {
  409         struct versatile_pci_softc *sc = device_get_softc(dev);
  410         uint32_t data;
  411         uint32_t shift, mask;
  412         uint32_t addr;
  413 
  414         if (sc->pcib_slot == slot) {
  415                 switch (bytes) {
  416                         case 4: 
  417                                 return (0xffffffff);
  418                                 break;
  419                         case 2:
  420                                 return (0xffff);
  421                                 break;
  422                         case 1:
  423                                 return (0xff);
  424                                 break;
  425                 }
  426         }
  427 
  428         addr = (bus << 16) | (slot << 11) | (func << 8) | (reg & ~3);
  429 
  430         /* register access is 32-bit aligned */
  431         shift = (reg & 3) * 8;
  432 
  433         /* Create a mask based on the width, post-shift */
  434         if (bytes == 2)
  435                 mask = 0xffff;
  436         else if (bytes == 1)
  437                 mask = 0xff;
  438         else
  439                 mask = 0xffffffff;
  440 
  441         dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, 
  442             func, reg, bytes);
  443 
  444         mtx_lock_spin(&sc->mtx);
  445         data = versatile_pci_conf_read_4(addr);
  446         mtx_unlock_spin(&sc->mtx);
  447 
  448         /* get request bytes from 32-bit word */
  449         data = (data >> shift) & mask;
  450 
  451         dprintf("%s: read 0x%x\n", __func__, data);
  452 
  453         return (data);
  454 }
  455 
  456 static void
  457 versatile_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
  458     u_int reg, uint32_t data, int bytes)
  459 {
  460 
  461         struct versatile_pci_softc *sc = device_get_softc(dev);
  462         uint32_t addr;
  463 
  464         dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
  465             func, reg, bytes);
  466 
  467         if (sc->pcib_slot == slot)
  468                 return;
  469 
  470         addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
  471         mtx_lock_spin(&sc->mtx);
  472         switch (bytes) {
  473                 case 4: 
  474                         versatile_pci_conf_write_4(addr, data);
  475                         break;
  476                 case 2:
  477                         versatile_pci_conf_write_2(addr, data);
  478                         break;
  479                 case 1:
  480                         versatile_pci_conf_write_1(addr, data);
  481                         break;
  482         }
  483         mtx_unlock_spin(&sc->mtx);
  484 }
  485 
  486 static device_method_t versatile_pci_methods[] = {
  487         DEVMETHOD(device_probe,         versatile_pci_probe),
  488         DEVMETHOD(device_attach,        versatile_pci_attach),
  489 
  490         /* Bus interface */
  491         DEVMETHOD(bus_read_ivar,        versatile_pci_read_ivar),
  492         DEVMETHOD(bus_write_ivar,       versatile_pci_write_ivar),
  493         DEVMETHOD(bus_alloc_resource,   versatile_pci_alloc_resource),
  494         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
  495         DEVMETHOD(bus_activate_resource, versatile_pci_activate_resource),
  496         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
  497         DEVMETHOD(bus_setup_intr,       versatile_pci_setup_intr),
  498         DEVMETHOD(bus_teardown_intr,    versatile_pci_teardown_intr),
  499 
  500         /* pcib interface */
  501         DEVMETHOD(pcib_maxslots,        versatile_pci_maxslots),
  502         DEVMETHOD(pcib_read_config,     versatile_pci_read_config),
  503         DEVMETHOD(pcib_write_config,    versatile_pci_write_config),
  504         DEVMETHOD(pcib_route_interrupt, versatile_pci_route_interrupt),
  505 
  506         DEVMETHOD_END
  507 };
  508 
  509 static driver_t versatile_pci_driver = {
  510         "pcib",
  511         versatile_pci_methods,
  512         sizeof(struct versatile_pci_softc),
  513 };
  514 
  515 static devclass_t versatile_pci_devclass;
  516 
  517 DRIVER_MODULE(versatile_pci, simplebus, versatile_pci_driver, versatile_pci_devclass, 0, 0);

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