The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/versatile/versatile_pci.c

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    1 /*
    2  * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: releng/11.1/sys/arm/versatile/versatile_pci.c 294883 2016-01-27 02:23:54Z jhibbits $");
   29 
   30 #include <sys/param.h>
   31 #include <sys/systm.h>
   32 #include <sys/bus.h>
   33 #include <sys/kernel.h>
   34 #include <sys/module.h>
   35 #include <sys/malloc.h>
   36 #include <sys/rman.h>
   37 #include <sys/watchdog.h>
   38 
   39 #include <vm/vm.h>
   40 #include <vm/pmap.h>
   41 
   42 #include <machine/bus.h>
   43 #include <machine/cpu.h>
   44 #include <machine/intr.h>
   45 
   46 #include <dev/pci/pcivar.h>
   47 #include <dev/pci/pcireg.h>
   48 
   49 #include <dev/pci/pcib_private.h>
   50 #include "pcib_if.h"
   51 
   52 #include <dev/fdt/fdt_common.h>
   53 #include <dev/ofw/openfirm.h>
   54 #include <dev/ofw/ofw_bus.h>
   55 #include <dev/ofw/ofw_bus_subr.h>
   56 
   57 #include <machine/bus.h>
   58 #include <machine/fdt.h>
   59 
   60 #define MEM_SYS         0
   61 #define MEM_CORE        1
   62 #define MEM_BASE        2
   63 #define MEM_CONF_BASE   3
   64 #define MEM_REGIONS     4
   65 
   66 #define SYS_PCICTL              0x00
   67 
   68 #define PCI_CORE_IMAP0          0x00
   69 #define PCI_CORE_IMAP1          0x04
   70 #define PCI_CORE_IMAP2          0x08
   71 #define PCI_CORE_SELFID         0x0C
   72 #define PCI_CORE_SMAP0          0x10
   73 #define PCI_CORE_SMAP1          0x14
   74 #define PCI_CORE_SMAP2          0x18
   75 
   76 #define VERSATILE_PCI_DEV       0x030010ee
   77 #define VERSATILE_PCI_CLASS     0x0b400000
   78 
   79 #define PCI_IO_WINDOW           0x44000000
   80 #define PCI_IO_SIZE             0x0c000000
   81 #define PCI_NPREFETCH_WINDOW    0x50000000
   82 #define PCI_NPREFETCH_SIZE      0x10000000
   83 #define PCI_PREFETCH_WINDOW     0x60000000
   84 #define PCI_PREFETCH_SIZE       0x10000000
   85 
   86 #define VERSATILE_PCI_IRQ_START 27
   87 #define VERSATILE_PCI_IRQ_END   30
   88 
   89 #ifdef DEBUG
   90 #define dprintf(fmt, args...) do { printf("%s(): ", __func__);   \
   91     printf(fmt,##args); } while (0)
   92 #else
   93 #define dprintf(fmt, args...)
   94 #endif
   95 
   96 
   97 #define versatile_pci_sys_read_4(reg)   \
   98         bus_read_4(sc->mem_res[MEM_SYS], (reg))
   99 #define versatile_pci_sys_write_4(reg, val)     \
  100         bus_write_4(sc->mem_res[MEM_SYS], (reg), (val))
  101 
  102 #define versatile_pci_core_read_4(reg)  \
  103         bus_read_4(sc->mem_res[MEM_CORE], (reg))
  104 #define versatile_pci_core_write_4(reg, val)    \
  105         bus_write_4(sc->mem_res[MEM_CORE], (reg), (val))
  106 
  107 #define versatile_pci_read_4(reg)       \
  108         bus_read_4(sc->mem_res[MEM_BASE], (reg))
  109 #define versatile_pci_write_4(reg, val) \
  110         bus_write_4(sc->mem_res[MEM_BASE], (reg), (val))
  111 
  112 #define versatile_pci_conf_read_4(reg)  \
  113         bus_read_4(sc->mem_res[MEM_CONF_BASE], (reg))
  114 #define versatile_pci_conf_write_4(reg, val)    \
  115         bus_write_4(sc->mem_res[MEM_CONF_BASE], (reg), (val))
  116 #define versatile_pci_conf_write_2(reg, val)    \
  117         bus_write_2(sc->mem_res[MEM_CONF_BASE], (reg), (val))
  118 #define versatile_pci_conf_write_1(reg, val)    \
  119         bus_write_1(sc->mem_res[MEM_CONF_BASE], (reg), (val))
  120 
  121 struct versatile_pci_softc {
  122         struct resource*        mem_res[MEM_REGIONS];
  123         struct resource*        irq_res;
  124         void*                   intr_hl;
  125 
  126         int                     pcib_slot;
  127 
  128         /* Bus part */
  129         int                     busno;
  130         struct rman             io_rman;
  131         struct rman             irq_rman;
  132         struct rman             mem_rman;
  133 
  134         struct mtx              mtx;
  135 };
  136 
  137 static struct resource_spec versatile_pci_mem_spec[] = {
  138         { SYS_RES_MEMORY, 0, RF_ACTIVE },
  139         { SYS_RES_MEMORY, 1, RF_ACTIVE },
  140         { SYS_RES_MEMORY, 2, RF_ACTIVE },
  141         { SYS_RES_MEMORY, 3, RF_ACTIVE },
  142         { -1, 0, 0 }
  143 };
  144 
  145 static int
  146 versatile_pci_probe(device_t dev)
  147 {
  148 
  149         if (!ofw_bus_status_okay(dev))
  150                 return (ENXIO);
  151 
  152         if (ofw_bus_is_compatible(dev, "versatile,pci")) {
  153                 device_set_desc(dev, "Versatile PCI controller");
  154                 return (BUS_PROBE_DEFAULT);
  155         }
  156 
  157         return (ENXIO);
  158 }
  159 
  160 static int
  161 versatile_pci_attach(device_t dev)
  162 {
  163         struct versatile_pci_softc *sc = device_get_softc(dev);
  164         int err;
  165         int slot;
  166         uint32_t vendordev_id, class_id;
  167         uint32_t val;
  168 
  169         /* Request memory resources */
  170         err = bus_alloc_resources(dev, versatile_pci_mem_spec,
  171                 sc->mem_res);
  172         if (err) {
  173                 device_printf(dev, "Error: could not allocate memory resources\n");
  174                 return (ENXIO);
  175         }
  176 
  177         /*
  178          * Setup memory windows
  179          */
  180         versatile_pci_core_write_4(PCI_CORE_IMAP0, (PCI_IO_WINDOW >> 28));
  181         versatile_pci_core_write_4(PCI_CORE_IMAP1, (PCI_NPREFETCH_WINDOW >> 28));
  182         versatile_pci_core_write_4(PCI_CORE_IMAP2, (PCI_PREFETCH_WINDOW >> 28));
  183 
  184         /*
  185          * XXX: this is SDRAM offset >> 28
  186          * Unused as of QEMU 1.5
  187          */
  188         versatile_pci_core_write_4(PCI_CORE_SMAP0, (PCI_IO_WINDOW >> 28));
  189         versatile_pci_core_write_4(PCI_CORE_SMAP1, (PCI_NPREFETCH_WINDOW >> 28));
  190         versatile_pci_core_write_4(PCI_CORE_SMAP2, (PCI_NPREFETCH_WINDOW >> 28));
  191 
  192         versatile_pci_sys_write_4(SYS_PCICTL, 1);
  193 
  194         for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
  195                 vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
  196                 class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
  197                 if ((vendordev_id == VERSATILE_PCI_DEV) &&
  198                     (class_id == VERSATILE_PCI_CLASS))
  199                         break;
  200         }
  201 
  202         if (slot == (PCI_SLOTMAX + 1)) {
  203                 bus_release_resources(dev, versatile_pci_mem_spec,
  204                     sc->mem_res);
  205                 device_printf(dev, "Versatile PCI core not found\n");
  206                 return (ENXIO);
  207         }
  208 
  209         sc->pcib_slot = slot;
  210         device_printf(dev, "PCI core at slot #%d\n", slot);
  211 
  212         versatile_pci_core_write_4(PCI_CORE_SELFID, slot);
  213         val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
  214         val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_MWRICEN);
  215         versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
  216 
  217         /* Again SDRAM start >> 28  */
  218         versatile_pci_write_4((slot << 11) + PCIR_BAR(0), 0);
  219         versatile_pci_write_4((slot << 11) + PCIR_BAR(1), 0);
  220         versatile_pci_write_4((slot << 11) + PCIR_BAR(2), 0);
  221 
  222         /* Prepare resource managers */
  223         sc->mem_rman.rm_type = RMAN_ARRAY;
  224         sc->mem_rman.rm_descr = "versatile PCI memory window";
  225         if (rman_init(&sc->mem_rman) != 0 || 
  226             rman_manage_region(&sc->mem_rman, PCI_NPREFETCH_WINDOW, 
  227                 PCI_NPREFETCH_WINDOW + PCI_NPREFETCH_SIZE - 1) != 0) {
  228                 panic("versatile_pci_attach: failed to set up memory rman");
  229         }
  230 
  231         bootverbose = 1;
  232         sc->io_rman.rm_type = RMAN_ARRAY;
  233         sc->io_rman.rm_descr = "versatile PCI IO window";
  234         if (rman_init(&sc->io_rman) != 0 || 
  235             rman_manage_region(&sc->io_rman, PCI_IO_WINDOW, 
  236                 PCI_IO_WINDOW + PCI_IO_SIZE - 1) != 0) {
  237                 panic("versatile_pci_attach: failed to set up I/O rman");
  238         }
  239 
  240         sc->irq_rman.rm_type = RMAN_ARRAY;
  241         sc->irq_rman.rm_descr = "versatile PCI IRQs";
  242         if (rman_init(&sc->irq_rman) != 0 ||
  243             rman_manage_region(&sc->irq_rman, VERSATILE_PCI_IRQ_START, 
  244                 VERSATILE_PCI_IRQ_END) != 0) {
  245                 panic("versatile_pci_attach: failed to set up IRQ rman");
  246         }
  247 
  248         mtx_init(&sc->mtx, device_get_nameunit(dev), "versatilepci",
  249                         MTX_SPIN);
  250 
  251         val = versatile_pci_conf_read_4((12 << 11) + PCIR_COMMAND);
  252 
  253         for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
  254                 vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR);
  255                 class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID);
  256 
  257                 if (slot == sc->pcib_slot)
  258                         continue;
  259 
  260                 if ((vendordev_id == 0xffffffff) &&
  261                     (class_id == 0xffffffff))
  262                         continue;
  263 
  264                 val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND);
  265                 val |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
  266                 versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val);
  267         }
  268 
  269         device_add_child(dev, "pci", -1);
  270         return (bus_generic_attach(dev));
  271 }
  272 
  273 static int
  274 versatile_pci_read_ivar(device_t dev, device_t child, int which,
  275     uintptr_t *result)
  276 {
  277         struct versatile_pci_softc *sc = device_get_softc(dev);
  278 
  279         switch (which) {
  280         case PCIB_IVAR_DOMAIN:
  281                 *result = 0;
  282                 return (0);
  283         case PCIB_IVAR_BUS:
  284                 *result = sc->busno;
  285                 return (0);
  286         }
  287 
  288         return (ENOENT);
  289 }
  290 
  291 static int
  292 versatile_pci_write_ivar(device_t dev, device_t child, int which,
  293     uintptr_t result)
  294 {
  295         struct versatile_pci_softc * sc = device_get_softc(dev);
  296 
  297         switch (which) {
  298         case PCIB_IVAR_BUS:
  299                 sc->busno = result;
  300                 return (0);
  301         }
  302 
  303         return (ENOENT);
  304 }
  305 
  306 static struct resource *
  307 versatile_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
  308     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
  309 {
  310 
  311         struct versatile_pci_softc *sc = device_get_softc(bus);
  312         struct resource *rv;
  313         struct rman *rm;
  314 
  315         dprintf("Alloc resources %d, %08lx..%08lx, %ld\n", type, start, end, count);
  316 
  317         switch (type) {
  318         case SYS_RES_IOPORT:
  319                 rm = &sc->io_rman;
  320                 break;
  321         case SYS_RES_IRQ:
  322                 rm = &sc->irq_rman;
  323                 break;
  324         case SYS_RES_MEMORY:
  325                 rm = &sc->mem_rman;
  326                 break;
  327         default:
  328                 return (NULL);
  329         }
  330 
  331         rv = rman_reserve_resource(rm, start, end, count, flags, child);
  332 
  333         if (rv == NULL)
  334                 return (NULL);
  335 
  336         rman_set_rid(rv, *rid);
  337 
  338         if (flags & RF_ACTIVE) {
  339                 if (bus_activate_resource(child, type, *rid, rv)) {
  340                         rman_release_resource(rv);
  341                         return (NULL);
  342                 }
  343         }
  344         return (rv);
  345 }
  346 
  347 static int
  348 versatile_pci_activate_resource(device_t bus, device_t child, int type, int rid,
  349     struct resource *r)
  350 {
  351         vm_offset_t vaddr;
  352         int res;
  353 
  354         switch(type) {
  355         case SYS_RES_MEMORY:
  356         case SYS_RES_IOPORT:
  357                 vaddr = (vm_offset_t)pmap_mapdev(rman_get_start(r),
  358                                 rman_get_size(r));
  359                 rman_set_bushandle(r, vaddr);
  360                 rman_set_bustag(r, fdtbus_bs_tag);
  361                 res = rman_activate_resource(r);
  362                 break;
  363         case SYS_RES_IRQ:
  364                 res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
  365                     child, type, rid, r));
  366                 break;
  367         default:
  368                 res = ENXIO;
  369                 break;
  370         }
  371 
  372         return (res);
  373 }
  374 
  375 static int
  376 versatile_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
  377             int flags, driver_filter_t *filt, driver_intr_t *handler,
  378             void *arg, void **cookiep)
  379 {
  380 
  381         return BUS_SETUP_INTR(device_get_parent(bus), bus, ires, flags,
  382             filt, handler, arg, cookiep);
  383 }
  384 
  385 static int
  386 versatile_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
  387     void *cookie)
  388 {
  389 
  390         return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, ires, cookie);
  391 }
  392 
  393 
  394 
  395 static int
  396 versatile_pci_maxslots(device_t dev)
  397 {
  398 
  399         return (PCI_SLOTMAX);
  400 }
  401 
  402 static int
  403 versatile_pci_route_interrupt(device_t pcib, device_t device, int pin)
  404 {
  405 
  406         return (27 + ((pci_get_slot(device) + pin - 1) & 3));
  407 }
  408 
  409 static uint32_t
  410 versatile_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
  411     u_int reg, int bytes)
  412 {
  413         struct versatile_pci_softc *sc = device_get_softc(dev);
  414         uint32_t data;
  415         uint32_t shift, mask;
  416         uint32_t addr;
  417 
  418         if (sc->pcib_slot == slot) {
  419                 switch (bytes) {
  420                         case 4: 
  421                                 return (0xffffffff);
  422                                 break;
  423                         case 2:
  424                                 return (0xffff);
  425                                 break;
  426                         case 1:
  427                                 return (0xff);
  428                                 break;
  429                 }
  430         }
  431 
  432         addr = (bus << 16) | (slot << 11) | (func << 8) | (reg & ~3);
  433 
  434         /* register access is 32-bit aligned */
  435         shift = (reg & 3) * 8;
  436 
  437         /* Create a mask based on the width, post-shift */
  438         if (bytes == 2)
  439                 mask = 0xffff;
  440         else if (bytes == 1)
  441                 mask = 0xff;
  442         else
  443                 mask = 0xffffffff;
  444 
  445         dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, 
  446             func, reg, bytes);
  447 
  448         mtx_lock_spin(&sc->mtx);
  449         data = versatile_pci_conf_read_4(addr);
  450         mtx_unlock_spin(&sc->mtx);
  451 
  452         /* get request bytes from 32-bit word */
  453         data = (data >> shift) & mask;
  454 
  455         dprintf("%s: read 0x%x\n", __func__, data);
  456 
  457         return (data);
  458 }
  459 
  460 static void
  461 versatile_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
  462     u_int reg, uint32_t data, int bytes)
  463 {
  464 
  465         struct versatile_pci_softc *sc = device_get_softc(dev);
  466         uint32_t addr;
  467 
  468         dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
  469             func, reg, bytes);
  470 
  471         if (sc->pcib_slot == slot)
  472                 return;
  473 
  474         addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
  475         mtx_lock_spin(&sc->mtx);
  476         switch (bytes) {
  477                 case 4: 
  478                         versatile_pci_conf_write_4(addr, data);
  479                         break;
  480                 case 2:
  481                         versatile_pci_conf_write_2(addr, data);
  482                         break;
  483                 case 1:
  484                         versatile_pci_conf_write_1(addr, data);
  485                         break;
  486         }
  487         mtx_unlock_spin(&sc->mtx);
  488 }
  489 
  490 static device_method_t versatile_pci_methods[] = {
  491         DEVMETHOD(device_probe,         versatile_pci_probe),
  492         DEVMETHOD(device_attach,        versatile_pci_attach),
  493 
  494         /* Bus interface */
  495         DEVMETHOD(bus_read_ivar,        versatile_pci_read_ivar),
  496         DEVMETHOD(bus_write_ivar,       versatile_pci_write_ivar),
  497         DEVMETHOD(bus_alloc_resource,   versatile_pci_alloc_resource),
  498         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
  499         DEVMETHOD(bus_activate_resource, versatile_pci_activate_resource),
  500         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
  501         DEVMETHOD(bus_setup_intr,       versatile_pci_setup_intr),
  502         DEVMETHOD(bus_teardown_intr,    versatile_pci_teardown_intr),
  503 
  504         /* pcib interface */
  505         DEVMETHOD(pcib_maxslots,        versatile_pci_maxslots),
  506         DEVMETHOD(pcib_read_config,     versatile_pci_read_config),
  507         DEVMETHOD(pcib_write_config,    versatile_pci_write_config),
  508         DEVMETHOD(pcib_route_interrupt, versatile_pci_route_interrupt),
  509 
  510         DEVMETHOD_END
  511 };
  512 
  513 static driver_t versatile_pci_driver = {
  514         "pcib",
  515         versatile_pci_methods,
  516         sizeof(struct versatile_pci_softc),
  517 };
  518 
  519 static devclass_t versatile_pci_devclass;
  520 
  521 DRIVER_MODULE(versatile_pci, simplebus, versatile_pci_driver, versatile_pci_devclass, 0, 0);

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