zy7_devcfg.c

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    1 /*-
    2  * Copyright (c) 2013 Thomas Skibo
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: releng/10.0/sys/arm/xilinx/zy7_devcfg.c 250015 2013-04-28 07:00:36Z wkoszek $
   27  */
   28 
   29 /* 
   30  * Zynq-7000 Devcfg driver.  This allows programming the PL (FPGA) section
   31  * of Zynq.
   32  *
   33  * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
   34  * (v1.4) November 16, 2012.  Xilinx doc UG585.  PL Configuration is
   35  * covered in section 6.4.5.
   36  */
   37 
   38 #include <sys/cdefs.h>
   39 __FBSDID("$FreeBSD: releng/10.0/sys/arm/xilinx/zy7_devcfg.c 250015 2013-04-28 07:00:36Z wkoszek $");
   40 
   41 #include <sys/param.h>
   42 #include <sys/systm.h>
   43 #include <sys/conf.h>
   44 #include <sys/kernel.h>
   45 #include <sys/module.h>
   46 #include <sys/sysctl.h>
   47 #include <sys/lock.h>
   48 #include <sys/mutex.h>
   49 #include <sys/resource.h>
   50 #include <sys/rman.h>
   51 #include <sys/uio.h>
   52 
   53 #include <machine/bus.h>
   54 #include <machine/resource.h>
   55 #include <machine/stdarg.h>
   56 
   57 #include <dev/fdt/fdt_common.h>
   58 #include <dev/ofw/ofw_bus.h>
   59 #include <dev/ofw/ofw_bus_subr.h>
   60 
   61 #include <arm/xilinx/zy7_slcr.h>
   62 
   63 struct zy7_devcfg_softc {
   64         device_t        dev;
   65         struct mtx      sc_mtx;
   66         struct resource *mem_res;
   67         struct resource *irq_res;
   68         struct cdev     *sc_ctl_dev;
   69         void            *intrhandle;
   70 
   71         bus_dma_tag_t   dma_tag;
   72         bus_dmamap_t    dma_map;
   73 
   74         int             is_open;
   75 };
   76 
   77 static struct zy7_devcfg_softc *zy7_devcfg_softc_p;
   78 
   79 #define DEVCFG_SC_LOCK(sc)              mtx_lock(&(sc)->sc_mtx)
   80 #define DEVCFG_SC_UNLOCK(sc)            mtx_unlock(&(sc)->sc_mtx)
   81 #define DEVCFG_SC_LOCK_INIT(sc) \
   82         mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
   83             "zy7_devcfg", MTX_DEF)
   84 #define DEVCFG_SC_LOCK_DESTROY(sc)      mtx_destroy(&(sc)->sc_mtx);
   85 #define DEVCFG_SC_ASSERT_LOCKED(sc)     mtx_assert(&(sc)->sc_mtx, MA_OWNED);
   86 
   87 #define RD4(sc, off)            (bus_read_4((sc)->mem_res, (off)))
   88 #define WR4(sc, off, val)       (bus_write_4((sc)->mem_res, (off), (val)))
   89 
   90 SYSCTL_NODE(_hw, OID_AUTO, fpga, CTLFLAG_RD, 0, \
   91             "Xilinx Zynq-7000 PL (FPGA) section");
   92 
   93 static int zy7_devcfg_sysctl_pl_done(SYSCTL_HANDLER_ARGS);
   94 SYSCTL_PROC(_hw_fpga, OID_AUTO, pl_done, CTLTYPE_INT | CTLFLAG_RD, NULL, 0,
   95             zy7_devcfg_sysctl_pl_done, "I", "PL section config DONE signal");
   96 
   97 static int zy7_en_level_shifters = 1;
   98 SYSCTL_INT(_hw_fpga, OID_AUTO, en_level_shifters, CTLFLAG_RW,
   99            &zy7_en_level_shifters, 0,
  100            "Enable PS-PL level shifters after device config");
  101 
  102 static int zy7_ps_vers = 0;
  103 SYSCTL_INT(_hw, OID_AUTO, ps_vers, CTLFLAG_RD, &zy7_ps_vers, 0,
  104            "Zynq-7000 PS version");
  105 
  106 
  107 /* cdev entry points. */
  108 static int zy7_devcfg_open(struct cdev *, int, int, struct thread *);
  109 static int zy7_devcfg_write(struct cdev *, struct uio *, int);
  110 static int zy7_devcfg_close(struct cdev *, int, int, struct thread *);
  111 
  112 
  113 struct cdevsw zy7_devcfg_cdevsw = {
  114         .d_version =    D_VERSION,
  115         .d_open =       zy7_devcfg_open,
  116         .d_write =      zy7_devcfg_write,
  117         .d_close =      zy7_devcfg_close,
  118         .d_name =       "devcfg",
  119 };
  120 
  121 /* Devcfg block registers. */
  122 #define ZY7_DEVCFG_CTRL                 0x0000
  123 #define   ZY7_DEVCFG_CTRL_FORCE_RST             (1<<31)
  124 #define   ZY7_DEVCFG_CTRL_PCFG_PROG_B           (1<<30)
  125 #define   ZY7_DEVCFG_CTRL_PCFG_POR_CNT_4K       (1<<29)
  126 #define   ZY7_DEVCFG_CTRL_PCAP_PR               (1<<27)
  127 #define   ZY7_DEVCFG_CTRL_PCAP_MODE             (1<<26)
  128 #define   ZY7_DEVCFG_CTRL_QTR_PCAP_RATE_EN      (1<<25)
  129 #define   ZY7_DEVCFG_CTRL_MULTIBOOT_EN          (1<<24)
  130 #define   ZY7_DEVCFG_CTRL_JTAG_CHAIN_DIS        (1<<23)
  131 #define   ZY7_DEVCFG_CTRL_USER_MODE             (1<<15)
  132 #define   ZY7_DEVCFG_CTRL_RESVD_WR11            (3<<13) /* always write 11 */
  133 #define   ZY7_DEVCFG_CTRL_PCFG_AES_FUSE         (1<<12)
  134 #define   ZY7_DEVCFG_CTRL_PCFG_AES_EN_MASK      (7<<9)  /* all 1's or 0's */
  135 #define   ZY7_DEVCFG_CTRL_SEU_EN                (1<<8)
  136 #define   ZY7_DEVCFG_CTRL_SEC_EN                (1<<7)
  137 #define   ZY7_DEVCFG_CTRL_SPNIDEN               (1<<6)
  138 #define   ZY7_DEVCFG_CTRL_SPIDEN                (1<<5)
  139 #define   ZY7_DEVCFG_CTRL_NIDEN                 (1<<4)
  140 #define   ZY7_DEVCFG_CTRL_DBGEN                 (1<<3)
  141 #define   ZY7_DEVCFG_CTRL_DAP_EN_MASK           (7<<0)  /* all 1's to enable */
  142 
  143 #define ZY7_DEVCFG_LOCK                 0x004
  144 #define   ZY7_DEVCFG_LOCK_AES_FUSE_LOCK         (1<<4)
  145 #define   ZY7_DEVCFG_LOCK_AES_EN                (1<<3)
  146 #define   ZY7_DEVCFG_LOCK_SEU_LOCK              (1<<2)
  147 #define   ZY7_DEVCFG_LOCK_SEC_LOCK              (1<<1)
  148 #define   ZY7_DEVCFG_LOCK_DBG_LOCK              (1<<0)
  149 
  150 #define ZY7_DEVCFG_CFG                  0x008
  151 #define   ZY7_DEVCFG_CFG_RFIFO_TH_MASK          (3<<10)
  152 #define   ZY7_DEVCFG_CFG_WFIFO_TH_MASK          (3<<8)
  153 #define   ZY7_DEVCFG_CFG_RCLK_EDGE              (1<<7)
  154 #define   ZY7_DEVCFG_CFG_WCLK_EDGE              (1<<6)
  155 #define   ZY7_DEVCFG_CFG_DIS_SRC_INC            (1<<5)
  156 #define   ZY7_DEVCFG_CFG_DIS_DST_INC            (1<<4)
  157 
  158 #define ZY7_DEVCFG_INT_STATUS           0x00C
  159 #define ZY7_DEVCFG_INT_MASK             0x010
  160 #define   ZY7_DEVCFG_INT_PSS_GTS_USR_B          (1<<31)
  161 #define   ZY7_DEVCFG_INT_PSS_FST_CFG_B          (1<<30)
  162 #define   ZY7_DEVCFG_INT_PSS_GPWRDWN_B          (1<<29)
  163 #define   ZY7_DEVCFG_INT_PSS_GTS_CFG_B          (1<<28)
  164 #define   ZY7_DEVCFG_INT_CFG_RESET_B            (1<<27)
  165 #define   ZY7_DEVCFG_INT_AXI_WTO                (1<<23) /* axi write timeout */
  166 #define   ZY7_DEVCFG_INT_AXI_WERR               (1<<22) /* axi write err */
  167 #define   ZY7_DEVCFG_INT_AXI_RTO                (1<<21) /* axi read timeout */
  168 #define   ZY7_DEVCFG_INT_AXI_RERR               (1<<20) /* axi read err */
  169 #define   ZY7_DEVCFG_INT_RX_FIFO_OV             (1<<18) /* rx fifo overflow */
  170 #define   ZY7_DEVCFG_INT_WR_FIFO_LVL            (1<<17) /* wr fifo < level */
  171 #define   ZY7_DEVCFG_INT_RD_FIFO_LVL            (1<<16) /* rd fifo >= level */
  172 #define   ZY7_DEVCFG_INT_DMA_CMD_ERR            (1<<15)
  173 #define   ZY7_DEVCFG_INT_DMA_Q_OV               (1<<14)
  174 #define   ZY7_DEVCFG_INT_DMA_DONE               (1<<13)
  175 #define   ZY7_DEVCFG_INT_DMA_PCAP_DONE          (1<<12)
  176 #define   ZY7_DEVCFG_INT_P2D_LEN_ERR            (1<<11)
  177 #define   ZY7_DEVCFG_INT_PCFG_HMAC_ERR          (1<<6)
  178 #define   ZY7_DEVCFG_INT_PCFG_SEU_ERR           (1<<5)
  179 #define   ZY7_DEVCFG_INT_PCFG_POR_B             (1<<4)
  180 #define   ZY7_DEVCFG_INT_PCFG_CFG_RST           (1<<3)
  181 #define   ZY7_DEVCFG_INT_PCFG_DONE              (1<<2)
  182 #define   ZY7_DEVCFG_INT_PCFG_INIT_PE           (1<<1)
  183 #define   ZY7_DEVCFG_INT_PCFG_INIT_NE           (1<<0)
  184 #define   ZY7_DEVCFG_INT_ERRORS                 0x00f0f860
  185 #define   ZY7_DEVCFG_INT_ALL                    0xf8f7f87f
  186 
  187 #define ZY7_DEVCFG_STATUS               0x014
  188 #define   ZY7_DEVCFG_STATUS_DMA_CMD_Q_F         (1<<31) /* cmd queue full */
  189 #define   ZY7_DEVCFG_STATUS_DMA_CMD_Q_E         (1<<30) /* cmd queue empty */
  190 #define   ZY7_DEVCFG_STATUS_DONE_COUNT_MASK     (3<<28)
  191 #define   ZY7_DEVCFG_STATUS_DONE_COUNT_SHIFT    28
  192 #define   ZY7_DEVCFG_STATUS_RX_FIFO_LVL_MASK    (0x1f<<20)
  193 #define   ZY7_DEVCFG_STATUS_RX_FIFO_LVL_SHIFT   20
  194 #define   ZY7_DEVCFG_STATUS_TX_FIFO_LVL_MASK    (0x7f<<12)
  195 #define   ZY7_DEVCFG_STATUS_TX_FIFO_LVL_SHIFT   12
  196 #define   ZY7_DEVCFG_STATUS_PSS_GTS_USR_B       (1<<11)
  197 #define   ZY7_DEVCFG_STATUS_PSS_FST_CFG_B       (1<<10)
  198 #define   ZY7_DEVCFG_STATUS_PSS_GPWRDWN_B       (1<<9)
  199 #define   ZY7_DEVCFG_STATUS_PSS_GTS_CFG_B       (1<<8)
  200 #define   ZY7_DEVCFG_STATUS_ILL_APB_ACCE        (1<<6)
  201 #define   ZY7_DEVCFG_STATUS_PSS_CFG_RESET_B     (1<<5)
  202 #define   ZY7_DEVCFG_STATUS_PCFG_INIT           (1<<4)
  203 #define   ZY7_DEVCFG_STATUS_EFUSE_BBRAM_KEY_DIS (1<<3)
  204 #define   ZY7_DEVCFG_STATUS_EFUSE_SEC_EN        (1<<2)
  205 #define   ZY7_DEVCFG_STATUS_EFUSE_JTAG_DIS      (1<<1)
  206 
  207 #define ZY7_DEVCFG_DMA_SRC_ADDR         0x018
  208 #define ZY7_DEVCFG_DMA_DST_ADDR         0x01c
  209 #define   ZY7_DEVCFG_DMA_ADDR_WAIT_PCAP 1
  210 #define   ZY7_DEVCFG_DMA_ADDR_ILLEGAL           0xffffffff
  211 
  212 #define ZY7_DEVCFG_DMA_SRC_LEN          0x020   /* in 4-byte words. */
  213 #define ZY7_DEVCFG_DMA_SRC_LEN_MAX              0x7ffffff
  214 #define ZY7_DEVCFG_DMA_DST_LEN          0x024
  215 #define ZY7_DEVCFG_ROM_SHADOW           0x028
  216 #define ZY7_DEVCFG_MULTIBOOT_ADDR       0x02c
  217 #define ZY7_DEVCFG_SW_ID                0x030
  218 #define ZY7_DEVCFG_UNLOCK               0x034
  219 #define ZY7_DEVCFG_UNLOCK_MAGIC                 0x757bdf0d
  220 #define ZY7_DEVCFG_MCTRL                0x080
  221 #define   ZY7_DEVCFG_MCTRL_PS_VERS_MASK         (0xf<<28)
  222 #define   ZY7_DEVCFG_MCTRL_PS_VERS_SHIFT        28
  223 #define   ZY7_DEVCFG_MCTRL_PCFG_POR_B           (1<<8)
  224 #define   ZY7_DEVCFG_MCTRL_INT_PCAP_LPBK        (1<<4)
  225 #define ZY7_DEVCFG_XADCIF_CFG           0x100
  226 #define ZY7_DEVCFG_XADCIF_INT_STAT      0x104
  227 #define ZY7_DEVCFG_XADCIF_INT_MASK      0x108
  228 #define ZY7_DEVCFG_XADCIF_MSTS          0x10c
  229 #define ZY7_DEVCFG_XADCIF_CMD_FIFO      0x110
  230 #define ZY7_DEVCFG_XADCIF_RD_FIFO       0x114
  231 #define ZY7_DEVCFG_XADCIF_MCTL          0x118
  232 
  233 
  234 /* Enable programming the PL through PCAP. */
  235 static void
  236 zy7_devcfg_init_hw(struct zy7_devcfg_softc *sc)
  237 {
  238 
  239         DEVCFG_SC_ASSERT_LOCKED(sc);
  240 
  241         /* Set devcfg control register. */
  242         WR4(sc, ZY7_DEVCFG_CTRL,
  243             ZY7_DEVCFG_CTRL_PCFG_PROG_B |
  244             ZY7_DEVCFG_CTRL_PCAP_PR |
  245             ZY7_DEVCFG_CTRL_PCAP_MODE |
  246             ZY7_DEVCFG_CTRL_USER_MODE |
  247             ZY7_DEVCFG_CTRL_RESVD_WR11 |
  248             ZY7_DEVCFG_CTRL_SPNIDEN |
  249             ZY7_DEVCFG_CTRL_SPIDEN |
  250             ZY7_DEVCFG_CTRL_NIDEN |
  251             ZY7_DEVCFG_CTRL_DBGEN |
  252             ZY7_DEVCFG_CTRL_DAP_EN_MASK);
  253 
  254         /* Turn off internal PCAP loopback. */
  255         WR4(sc, ZY7_DEVCFG_MCTRL, RD4(sc, ZY7_DEVCFG_MCTRL) &
  256             ~ZY7_DEVCFG_MCTRL_INT_PCAP_LPBK);
  257 }
  258 
  259 /* Clear previous configuration of the PL by asserting PROG_B. */
  260 static int
  261 zy7_devcfg_reset_pl(struct zy7_devcfg_softc *sc)
  262 {
  263         uint32_t devcfg_ctl;
  264         int tries, err;
  265 
  266         DEVCFG_SC_ASSERT_LOCKED(sc);
  267 
  268         devcfg_ctl = RD4(sc, ZY7_DEVCFG_CTRL);
  269 
  270         /* Deassert PROG_B (active low). */
  271         devcfg_ctl |= ZY7_DEVCFG_CTRL_PCFG_PROG_B;
  272         WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
  273 
  274         /* Wait for INIT_B deasserted (active low). */
  275         tries = 0;
  276         while ((RD4(sc, ZY7_DEVCFG_STATUS) &
  277                 ZY7_DEVCFG_STATUS_PCFG_INIT) == 0) {
  278                 if (++tries >= 100)
  279                         return (EIO);
  280                 DELAY(5);
  281         }
  282 
  283         /* Reassert PROG_B. */
  284         devcfg_ctl &= ~ZY7_DEVCFG_CTRL_PCFG_PROG_B;
  285         WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
  286 
  287         /* Wait for INIT_B asserted. */
  288         tries = 0;
  289         while ((RD4(sc, ZY7_DEVCFG_STATUS) &
  290                 ZY7_DEVCFG_STATUS_PCFG_INIT) != 0) {
  291                 if (++tries >= 100)
  292                         return (EIO);
  293                 DELAY(5);
  294         }
  295 
  296         /* Clear sticky bits and set up INIT_B positive edge interrupt. */
  297         WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
  298         WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE);
  299 
  300         /* Deassert PROG_B again. */
  301         devcfg_ctl |= ZY7_DEVCFG_CTRL_PCFG_PROG_B;
  302         WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
  303 
  304         /* Wait for INIT_B deasserted indicating FPGA internal initialization
  305          * is complete.  This takes much longer than the previous waits for
  306          * INIT_B transition (on the order of 700us).
  307          */
  308         err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7in", hz);
  309         if (err != 0)
  310                 return (err);
  311 
  312         /* Clear sticky DONE bit in interrupt status. */
  313         WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
  314 
  315         return (0);
  316 }
  317 
  318 /* Callback function for bus_dmamap_load(). */
  319 static void
  320 zy7_dma_cb2(void *arg, bus_dma_segment_t *seg, int nsegs, int error)
  321 {
  322         if (!error && nsegs == 1)
  323                 *(bus_addr_t *)arg = seg[0].ds_addr;
  324 }
  325 
  326 
  327 static int
  328 zy7_devcfg_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
  329 {
  330         struct zy7_devcfg_softc *sc = dev->si_drv1;
  331         int err;
  332 
  333         DEVCFG_SC_LOCK(sc);
  334         if (sc->is_open) {
  335                 DEVCFG_SC_UNLOCK(sc);
  336                 return (EBUSY);
  337         }
  338 
  339         sc->dma_map = NULL;
  340         err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 4, 0,
  341                                  BUS_SPACE_MAXADDR_32BIT,
  342                                  BUS_SPACE_MAXADDR,
  343                                  NULL, NULL,
  344                                  PAGE_SIZE,
  345                                  1,
  346                                  PAGE_SIZE,
  347                                  0,
  348                                  busdma_lock_mutex,
  349                                  &sc->sc_mtx,
  350                                  &sc->dma_tag);
  351         if (err) {
  352                 DEVCFG_SC_UNLOCK(sc);
  353                 return (err);
  354         }
  355 
  356         sc->is_open = 1;
  357         DEVCFG_SC_UNLOCK(sc);
  358         return (0);
  359 }
  360 
  361 static int
  362 zy7_devcfg_write(struct cdev *dev, struct uio *uio, int ioflag)
  363 {
  364         struct zy7_devcfg_softc *sc = dev->si_drv1;
  365         void *dma_mem;
  366         bus_addr_t dma_physaddr;
  367         int segsz, err;
  368 
  369         DEVCFG_SC_LOCK(sc);
  370 
  371         /* First write?  Reset PL. */
  372         if (uio->uio_offset == 0 && uio->uio_resid > 0) {
  373                 zy7_devcfg_init_hw(sc);
  374                 zy7_slcr_preload_pl();
  375                 err = zy7_devcfg_reset_pl(sc);
  376                 if (err != 0) {
  377                         DEVCFG_SC_UNLOCK(sc);
  378                         return (err);
  379                 }
  380         }
  381 
  382         /* Allocate dma memory and load. */
  383         err = bus_dmamem_alloc(sc->dma_tag, &dma_mem, BUS_DMA_NOWAIT,
  384                                &sc->dma_map);
  385         if (err != 0) {
  386                 DEVCFG_SC_UNLOCK(sc);
  387                 return (err);
  388         }
  389         err = bus_dmamap_load(sc->dma_tag, sc->dma_map, dma_mem, PAGE_SIZE,
  390                               zy7_dma_cb2, &dma_physaddr, 0);
  391         if (err != 0) {
  392                 bus_dmamem_free(sc->dma_tag, dma_mem, sc->dma_map);
  393                 DEVCFG_SC_UNLOCK(sc);
  394                 return (err);
  395         }
  396 
  397         while (uio->uio_resid > 0) {
  398                 /* If DONE signal has been set, we shouldn't write anymore. */
  399                 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) &
  400                      ZY7_DEVCFG_INT_PCFG_DONE) != 0) {
  401                         err = EIO;
  402                         break;
  403                 }
  404 
  405                 /* uiomove the data from user buffer to our dma map. */
  406                 segsz = MIN(PAGE_SIZE, uio->uio_resid);
  407                 err = uiomove(dma_mem, segsz, uio);
  408                 if (err != 0)
  409                         break;
  410 
  411                 /* Flush the cache to memory. */
  412                 bus_dmamap_sync(sc->dma_tag, sc->dma_map,
  413                                 BUS_DMASYNC_PREWRITE);
  414 
  415                 /* Program devcfg's DMA engine.  The ordering of these
  416                  * register writes is critical.
  417                  */
  418                 if (uio->uio_resid > segsz)
  419                         WR4(sc, ZY7_DEVCFG_DMA_SRC_ADDR,
  420                             (uint32_t) dma_physaddr);
  421                 else
  422                         WR4(sc, ZY7_DEVCFG_DMA_SRC_ADDR,
  423                             (uint32_t) dma_physaddr |
  424                             ZY7_DEVCFG_DMA_ADDR_WAIT_PCAP);
  425                 WR4(sc, ZY7_DEVCFG_DMA_DST_ADDR, ZY7_DEVCFG_DMA_ADDR_ILLEGAL);
  426                 WR4(sc, ZY7_DEVCFG_DMA_SRC_LEN, (segsz+3)/4);
  427                 WR4(sc, ZY7_DEVCFG_DMA_DST_LEN, 0);
  428 
  429                 /* Now clear done bit and set up DMA done interrupt. */
  430                 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
  431                 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_DMA_DONE);
  432 
  433                 /* Wait for DMA done interrupt. */
  434                 err = mtx_sleep(sc->dma_map, &sc->sc_mtx, PCATCH,
  435                                 "zy7dma", hz);
  436                 if (err != 0)
  437                         break;
  438 
  439                 bus_dmamap_sync(sc->dma_tag, sc->dma_map,
  440                                 BUS_DMASYNC_POSTWRITE);
  441 
  442                 /* Check DONE signal. */
  443                 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) &
  444                      ZY7_DEVCFG_INT_PCFG_DONE) != 0)
  445                         zy7_slcr_postload_pl(zy7_en_level_shifters);
  446         }
  447 
  448         bus_dmamap_unload(sc->dma_tag, sc->dma_map);
  449         bus_dmamem_free(sc->dma_tag, dma_mem, sc->dma_map);
  450         DEVCFG_SC_UNLOCK(sc);
  451         return (err);
  452 }
  453 
  454 static int
  455 zy7_devcfg_close(struct cdev *dev, int fflag, int devtype, struct thread *td)
  456 {
  457         struct zy7_devcfg_softc *sc = dev->si_drv1;
  458 
  459         DEVCFG_SC_LOCK(sc);
  460         sc->is_open = 0;
  461         bus_dma_tag_destroy(sc->dma_tag);
  462         DEVCFG_SC_UNLOCK(sc);
  463 
  464         return (0);
  465 }
  466 
  467 
  468 static void
  469 zy7_devcfg_intr(void *arg)
  470 {
  471         struct zy7_devcfg_softc *sc = (struct zy7_devcfg_softc *)arg;
  472         uint32_t istatus, imask;
  473 
  474         DEVCFG_SC_LOCK(sc);
  475 
  476         istatus = RD4(sc, ZY7_DEVCFG_INT_STATUS);
  477         imask = ~RD4(sc, ZY7_DEVCFG_INT_MASK);
  478 
  479         /* Turn interrupt off. */
  480         WR4(sc, ZY7_DEVCFG_INT_MASK, ~0);
  481 
  482         if ((istatus & imask) == 0) {
  483                 DEVCFG_SC_UNLOCK(sc);
  484                 return;
  485         }
  486 
  487         /* DMA done? */
  488         if ((istatus & ZY7_DEVCFG_INT_DMA_DONE) != 0)
  489                 wakeup(sc->dma_map);
  490 
  491         /* INIT_B positive edge? */
  492         if ((istatus & ZY7_DEVCFG_INT_PCFG_INIT_PE) != 0)
  493                 wakeup(sc);
  494 
  495         DEVCFG_SC_UNLOCK(sc);
  496 }
  497 
  498 /* zy7_devcfg_sysctl_pl_done() returns status of the PL_DONE signal.
  499  */
  500 static int
  501 zy7_devcfg_sysctl_pl_done(SYSCTL_HANDLER_ARGS)
  502 {
  503         struct zy7_devcfg_softc *sc = zy7_devcfg_softc_p;
  504         int pl_done = 0;
  505 
  506         if (sc) {
  507                 DEVCFG_SC_LOCK(sc);
  508 
  509                 /* PCFG_DONE bit is sticky.  Clear it before checking it. */
  510                 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_PCFG_DONE);
  511                 pl_done = ((RD4(sc, ZY7_DEVCFG_INT_STATUS) &
  512                             ZY7_DEVCFG_INT_PCFG_DONE) != 0);
  513 
  514                 DEVCFG_SC_UNLOCK(sc);
  515         }
  516         return (sysctl_handle_int(oidp, &pl_done, 0, req));
  517 }
  518 
  519 static int
  520 zy7_devcfg_probe(device_t dev)
  521 {
  522         if (!ofw_bus_is_compatible(dev, "xlnx,zy7_devcfg"))
  523                 return (ENXIO);
  524 
  525         device_set_desc(dev, "Zynq devcfg block");
  526         return (0);
  527 }
  528 
  529 static int zy7_devcfg_detach(device_t dev);
  530 
  531 static int
  532 zy7_devcfg_attach(device_t dev)
  533 {
  534         struct zy7_devcfg_softc *sc = device_get_softc(dev);
  535         int rid, err;
  536 
  537         /* Allow only one attach. */
  538         if (zy7_devcfg_softc_p != NULL)
  539                 return (ENXIO);
  540 
  541         sc->dev = dev;
  542 
  543         DEVCFG_SC_LOCK_INIT(sc);
  544 
  545         /* Get memory resource. */
  546         rid = 0;
  547         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
  548                                              RF_ACTIVE);
  549         if (sc->mem_res == NULL) {
  550                 device_printf(dev, "could not allocate memory resources.\n");
  551                 zy7_devcfg_detach(dev);
  552                 return (ENOMEM);
  553         }
  554 
  555         /* Allocate IRQ. */
  556         rid = 0;
  557         sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
  558                                              RF_ACTIVE);
  559         if (sc->irq_res == NULL) {
  560                 device_printf(dev, "cannot allocate IRQ\n");
  561                 zy7_devcfg_detach(dev);
  562                 return (ENOMEM);
  563         }
  564 
  565         /* Activate the interrupt. */
  566         err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
  567                              NULL, zy7_devcfg_intr, sc, &sc->intrhandle);
  568         if (err) {
  569                 device_printf(dev, "cannot setup IRQ\n");
  570                 zy7_devcfg_detach(dev);
  571                 return (err);
  572         }
  573 
  574         /* Create /dev/devcfg */
  575         sc->sc_ctl_dev = make_dev(&zy7_devcfg_cdevsw, 0,
  576                           UID_ROOT, GID_WHEEL, 0600, "devcfg");
  577         if (sc->sc_ctl_dev == NULL) {
  578                 device_printf(dev, "failed to create /dev/devcfg");
  579                 zy7_devcfg_detach(dev);
  580                 return (ENXIO);
  581         }
  582         sc->sc_ctl_dev->si_drv1 = sc;
  583 
  584         zy7_devcfg_softc_p = sc;
  585 
  586         /* Unlock devcfg registers. */
  587         WR4(sc, ZY7_DEVCFG_UNLOCK, ZY7_DEVCFG_UNLOCK_MAGIC);
  588 
  589         /* Make sure interrupts are completely disabled. */
  590         WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
  591         WR4(sc, ZY7_DEVCFG_INT_MASK, 0xffffffff);
  592 
  593         /* Get PS_VERS for SYSCTL. */
  594         zy7_ps_vers = (RD4(sc, ZY7_DEVCFG_MCTRL) &
  595                        ZY7_DEVCFG_MCTRL_PS_VERS_MASK) >>
  596                 ZY7_DEVCFG_MCTRL_PS_VERS_SHIFT;
  597 
  598         return (0);
  599 }
  600 
  601 static int
  602 zy7_devcfg_detach(device_t dev)
  603 {
  604         struct zy7_devcfg_softc *sc = device_get_softc(dev);
  605 
  606         if (device_is_attached(dev))
  607                 bus_generic_detach(dev);
  608 
  609         /* Get rid of /dev/devcfg0. */
  610         if (sc->sc_ctl_dev != NULL)
  611                 destroy_dev(sc->sc_ctl_dev);
  612 
  613         /* Teardown and release interrupt. */
  614         if (sc->irq_res != NULL) {
  615                 if (sc->intrhandle)
  616                         bus_teardown_intr(dev, sc->irq_res, sc->intrhandle);
  617                 bus_release_resource(dev, SYS_RES_IRQ,
  618                              rman_get_rid(sc->irq_res), sc->irq_res);
  619         }
  620 
  621         /* Release memory resource. */
  622         if (sc->mem_res != NULL)
  623                 bus_release_resource(dev, SYS_RES_MEMORY,
  624                              rman_get_rid(sc->mem_res), sc->mem_res);
  625 
  626         zy7_devcfg_softc_p = NULL;
  627 
  628         DEVCFG_SC_LOCK_DESTROY(sc);
  629 
  630         return (0);
  631 }
  632 
  633 static device_method_t zy7_devcfg_methods[] = {
  634         /* device_if */
  635         DEVMETHOD(device_probe,         zy7_devcfg_probe),
  636         DEVMETHOD(device_attach,        zy7_devcfg_attach),
  637         DEVMETHOD(device_detach,        zy7_devcfg_detach),
  638 
  639         DEVMETHOD_END
  640 };
  641 
  642 static driver_t zy7_devcfg_driver = {
  643         "zy7_devcfg",
  644         zy7_devcfg_methods,
  645         sizeof(struct zy7_devcfg_softc),
  646 };
  647 static devclass_t zy7_devcfg_devclass;
  648 
  649 DRIVER_MODULE(zy7_devcfg, simplebus, zy7_devcfg_driver, zy7_devcfg_devclass, \
  650               0, 0);
  651 MODULE_DEPEND(zy7_devcfg, zy7_slcr, 1, 1, 1);
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FreeBSD/Linux Kernel Cross Reference sys/arm/xilinx/zy7_devcfg.c

FreeBSD/Linux Kernel Cross Reference
sys/arm/xilinx/zy7_devcfg.c
