The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/xilinx/zy7_mp.c

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    1 /*-
    2  * Copyright (c) 2013 Thomas Skibo.  All rights reserved.
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions
    6  * are met:
    7  * 1. Redistributions of source code must retain the above copyright
    8  *    notice, this list of conditions and the following disclaimer.
    9  * 2. Redistributions in binary form must reproduce the above copyright
   10  *    notice, this list of conditions and the following disclaimer in the
   11  *    documentation and/or other materials provided with the distribution.
   12  *
   13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   14  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   16  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   17  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   18  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   19  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   20  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   23  */
   24 
   25 #include "opt_platform.h"
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD$");
   29 #include <sys/param.h>
   30 #include <sys/systm.h>
   31 #include <sys/bus.h>
   32 #include <sys/lock.h>
   33 #include <sys/mutex.h>
   34 #include <sys/smp.h>
   35 
   36 #include <vm/vm.h>
   37 #include <vm/pmap.h>
   38 
   39 #include <machine/cpu.h>
   40 #include <machine/smp.h>
   41 #include <machine/fdt.h>
   42 #include <machine/intr.h>
   43 #include <machine/platformvar.h>
   44 
   45 #include <arm/xilinx/zy7_machdep.h>
   46 #include <arm/xilinx/zy7_reg.h>
   47 #include <arm/xilinx/zy7_slcr.h>
   48 
   49 #define ZYNQ7_CPU1_ENTRY                0xfffffff0
   50 
   51 #define SCU_CONTROL_REG                 0xf8f00000
   52 #define    SCU_CONTROL_ENABLE           1
   53 #define SCU_CONFIG_REG                  0xf8f00004
   54 #define    SCU_CONFIG_N_CPUS_MASK       3
   55 
   56 #define SLCR_PSS_IDCODE                 0xf8000530
   57 
   58 void
   59 zynq7_mp_setmaxid(platform_t plat)
   60 {
   61         bus_space_handle_t slcr_handle;
   62         int device_id;
   63         bus_space_handle_t scu_handle;
   64 
   65         if (mp_ncpus != 0)
   66                 return;
   67 
   68         /* Map in SLCR PSS_IDCODE register. */
   69         if (bus_space_map(fdtbus_bs_tag, SLCR_PSS_IDCODE, 4, 0,
   70             &slcr_handle) != 0)
   71                 panic("%s: Could not map SLCR IDCODE reg.\n", __func__);
   72 
   73         device_id = bus_space_read_4(fdtbus_bs_tag, slcr_handle, 0) &
   74             ZY7_SLCR_PSS_IDCODE_DEVICE_MASK;
   75 
   76         bus_space_unmap(fdtbus_bs_tag, slcr_handle, 4);
   77 
   78         /*
   79          * Zynq XC7z0xxS single core chips indicate incorrect number of CPUs in
   80          * SCU configuration register.
   81          */
   82         if (device_id == ZY7_SLCR_PSS_IDCODE_DEVICE_7Z007S ||
   83             device_id == ZY7_SLCR_PSS_IDCODE_DEVICE_7Z012S ||
   84             device_id == ZY7_SLCR_PSS_IDCODE_DEVICE_7Z014S) {
   85                 mp_maxid = 0;
   86                 mp_ncpus = 1;
   87                 return;
   88         }
   89 
   90         /* Map in SCU config register. */
   91         if (bus_space_map(fdtbus_bs_tag, SCU_CONFIG_REG, 4, 0,
   92             &scu_handle) != 0)
   93                 panic("zynq7_mp_setmaxid: Could not map SCU config reg.\n");
   94 
   95         mp_maxid = bus_space_read_4(fdtbus_bs_tag, scu_handle, 0) &
   96             SCU_CONFIG_N_CPUS_MASK;
   97         mp_ncpus = mp_maxid + 1;
   98 
   99         bus_space_unmap(fdtbus_bs_tag, scu_handle, 4);
  100 }
  101 
  102 void
  103 zynq7_mp_start_ap(platform_t plat)
  104 {
  105         bus_space_handle_t scu_handle;
  106         bus_space_handle_t ocm_handle;
  107         uint32_t scu_ctrl;
  108 
  109         /* Map in SCU control register. */
  110         if (bus_space_map(fdtbus_bs_tag, SCU_CONTROL_REG, 4,
  111             0, &scu_handle) != 0)
  112                 panic("%s: Could not map SCU control reg.\n", __func__);
  113 
  114         /* Set SCU enable bit. */
  115         scu_ctrl = bus_space_read_4(fdtbus_bs_tag, scu_handle, 0);
  116         scu_ctrl |= SCU_CONTROL_ENABLE;
  117         bus_space_write_4(fdtbus_bs_tag, scu_handle, 0, scu_ctrl);
  118 
  119         bus_space_unmap(fdtbus_bs_tag, scu_handle, 4);
  120 
  121         /* Map in magic location to give entry address to CPU1. */
  122         if (bus_space_map(fdtbus_bs_tag, ZYNQ7_CPU1_ENTRY, 4,
  123             0, &ocm_handle) != 0)
  124                 panic("%s: Could not map OCM\n", __func__);
  125 
  126         /* Write start address for CPU1. */
  127         bus_space_write_4(fdtbus_bs_tag, ocm_handle, 0,
  128             pmap_kextract((vm_offset_t)mpentry));
  129 
  130         bus_space_unmap(fdtbus_bs_tag, ocm_handle, 4);
  131 
  132         /*
  133          * The SCU is enabled above but I think the second CPU doesn't
  134          * turn on filtering until after the wake-up below. I think that's why
  135          * things don't work if I don't put these cache ops here.  Also, the
  136          * magic location, 0xfffffff0, isn't in the SCU's filtering range so it
  137          * needs a write-back too.
  138          */
  139         dcache_wbinv_poc_all();
  140 
  141         /* Wake up CPU1. */
  142         dsb();
  143         sev();
  144 }

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