The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/xilinx/zy7_reg.h

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    1 /*-
    2  * Copyright (c) 2012-2013 Thomas Skibo
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: releng/10.0/sys/arm/xilinx/zy7_reg.h 250015 2013-04-28 07:00:36Z wkoszek $
   27  */
   28 
   29 /*
   30  * Address regions of Zynq-7000.  
   31  * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
   32  * (v1.4) November 16, 2012.  Xilinx doc UG585.
   33  */
   34 
   35 #ifndef _ZY7_REG_H_
   36 #define _ZY7_REG_H_
   37 
   38 /* PL AXI buses:  General Purpose Port #0, M_AXI_GP0. */
   39 #define ZYNQ7_PLGP0_HWBASE      0x40000000
   40 #define ZYNQ7_PLGP0_SIZE        0x40000000
   41 
   42 /* PL AXI buses:  General Purpose Port #1, M_AXI_GP1. */
   43 #define ZYNQ7_PLGP1_HWBASE      0x80000000
   44 #define ZYNQ7_PLGP1_SIZE        0x40000000
   45 
   46 /* I/O Peripheral registers. */
   47 #define ZYNQ7_PSIO_VBASE        0xE0000000
   48 #define ZYNQ7_PSIO_HWBASE       0xE0000000
   49 #define ZYNQ7_PSIO_SIZE         0x00300000
   50 
   51 /* UART0 and UART1 */
   52 #define ZYNQ7_UART0_VBASE       (ZYNQ7_PSIO_VBASE)
   53 #define ZYNQ7_UART0_HWBASE      (ZYNQ7_PSIO_HWBASE)
   54 #define ZYNQ7_UART0_SIZE        0x1000
   55 
   56 #define ZYNQ7_UART1_VBASE       (ZYNQ7_PSIO_VBASE+0x1000)
   57 #define ZYNQ7_UART1_HWBASE      (ZYNQ7_PSIO_HWBASE+0x1000)
   58 #define ZYNQ7_UART1_SIZE        0x1000
   59 
   60 
   61 /* SMC Memories not mapped for now. */
   62 #define ZYNQ7_SMC_HWBASE        0xE1000000
   63 #define ZYNQ7_SMC_SIZE          0x05000000
   64 
   65 /* SLCR, PS system, and CPU private registers combined in this region. */
   66 #define ZYNQ7_PSCTL_VBASE       0xF8000000
   67 #define ZYNQ7_PSCTL_HWBASE      0xF8000000
   68 #define ZYNQ7_PSCTL_SIZE        0x01000000
   69 
   70 #define ZYNQ7_SLCR_VBASE        (ZYNQ7_PSCTL_VBASE)
   71 #define ZYNQ7_SLCR_HWBASE       (ZYNQ7_PSCTL_HWBASE)
   72 #define ZYNQ7_SLCR_SIZE         0x1000
   73 
   74 #define ZYNQ7_DEVCFG_VBASE      (ZYNQ7_PSCTL_VBASE+0x7000)
   75 #define ZYNQ7_DEVCFG_HWBASE     (ZYNQ7_PSCTL_HWBASE+0x7000)
   76 #define ZYNQ7_DEVCFG_SIZE       0x1000
   77 
   78 #endif /* _ZY7_REG_H_ */

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