The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/xilinx/zy7_reg.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2012-2013 Thomas Skibo
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  *
   28  * $FreeBSD$
   29  */
   30 
   31 /*
   32  * Address regions of Zynq-7000.  
   33  * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
   34  * (v1.4) November 16, 2012.  Xilinx doc UG585.
   35  */
   36 
   37 #ifndef _ZY7_REG_H_
   38 #define _ZY7_REG_H_
   39 
   40 /* PL AXI buses:  General Purpose Port #0, M_AXI_GP0. */
   41 #define ZYNQ7_PLGP0_HWBASE      0x40000000
   42 #define ZYNQ7_PLGP0_SIZE        0x40000000
   43 
   44 /* PL AXI buses:  General Purpose Port #1, M_AXI_GP1. */
   45 #define ZYNQ7_PLGP1_HWBASE      0x80000000
   46 #define ZYNQ7_PLGP1_SIZE        0x40000000
   47 
   48 /* I/O Peripheral registers. */
   49 #define ZYNQ7_PSIO_HWBASE       0xE0000000
   50 #define ZYNQ7_PSIO_SIZE         0x00300000
   51 
   52 /* UART0 and UART1 */
   53 #define ZYNQ7_UART0_HWBASE      (ZYNQ7_PSIO_HWBASE)
   54 #define ZYNQ7_UART0_SIZE        0x1000
   55 
   56 #define ZYNQ7_UART1_HWBASE      (ZYNQ7_PSIO_HWBASE+0x1000)
   57 #define ZYNQ7_UART1_SIZE        0x1000
   58 
   59 
   60 /* SMC Memories not mapped for now. */
   61 #define ZYNQ7_SMC_HWBASE        0xE1000000
   62 #define ZYNQ7_SMC_SIZE          0x05000000
   63 
   64 /* SLCR, PS system, and CPU private registers combined in this region. */
   65 #define ZYNQ7_PSCTL_HWBASE      0xF8000000
   66 #define ZYNQ7_PSCTL_SIZE        0x01000000
   67 
   68 #define ZYNQ7_SLCR_HWBASE       (ZYNQ7_PSCTL_HWBASE)
   69 #define ZYNQ7_SLCR_SIZE         0x1000
   70 
   71 #define ZYNQ7_DEVCFG_HWBASE     (ZYNQ7_PSCTL_HWBASE+0x7000)
   72 #define ZYNQ7_DEVCFG_SIZE       0x1000
   73 
   74 #endif /* _ZY7_REG_H_ */

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