zy7_slcr.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2013 Thomas Skibo
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  *
   28  * $FreeBSD$
   29  */
   30 
   31 /*
   32  * Zynq-700 SLCR driver.  Provides hooks for cpu_reset and PL control stuff.
   33  * In the future, maybe MIO control, clock control, etc. could go here.
   34  *
   35  * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
   36  * (v1.4) November 16, 2012.  Xilinx doc UG585.
   37  */
   38 
   39 #include <sys/cdefs.h>
   40 __FBSDID("$FreeBSD$");
   41 
   42 #include <sys/param.h>
   43 #include <sys/systm.h>
   44 #include <sys/conf.h>
   45 #include <sys/kernel.h>
   46 #include <sys/module.h>
   47 #include <sys/lock.h>
   48 #include <sys/mutex.h>
   49 #include <sys/resource.h>
   50 #include <sys/sysctl.h>
   51 #include <sys/rman.h>
   52 
   53 #include <machine/bus.h>
   54 #include <machine/resource.h>
   55 #include <machine/stdarg.h>
   56 
   57 #include <dev/ofw/ofw_bus.h>
   58 #include <dev/ofw/ofw_bus_subr.h>
   59 
   60 #include <arm/xilinx/zy7_slcr.h>
   61 
   62 struct zy7_slcr_softc {
   63         device_t        dev;
   64         struct mtx      sc_mtx;
   65         struct resource *mem_res;
   66 };
   67 
   68 static struct zy7_slcr_softc *zy7_slcr_softc_p;
   69 extern void (*zynq7_cpu_reset);
   70 
   71 #define ZSLCR_LOCK(sc)          mtx_lock(&(sc)->sc_mtx)
   72 #define ZSLCR_UNLOCK(sc)                mtx_unlock(&(sc)->sc_mtx)
   73 #define ZSLCR_LOCK_INIT(sc) \
   74         mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
   75             "zy7_slcr", MTX_DEF)
   76 #define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
   77 
   78 #define RD4(sc, off)            (bus_read_4((sc)->mem_res, (off)))
   79 #define WR4(sc, off, val)       (bus_write_4((sc)->mem_res, (off), (val)))
   80 
   81 #define ZYNQ_DEFAULT_PS_CLK_FREQUENCY   33333333        /* 33.3 Mhz */
   82 
   83 SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
   84     "Xilinx Zynq-7000");
   85 
   86 static char zynq_bootmode[64];
   87 SYSCTL_STRING(_hw_zynq, OID_AUTO, bootmode, CTLFLAG_RD, zynq_bootmode, 0,
   88               "Zynq boot mode");
   89 
   90 static char zynq_pssid[100];
   91 SYSCTL_STRING(_hw_zynq, OID_AUTO, pssid, CTLFLAG_RD, zynq_pssid, 0,
   92            "Zynq PSS IDCODE");
   93 
   94 static uint32_t zynq_reboot_status;
   95 SYSCTL_INT(_hw_zynq, OID_AUTO, reboot_status, CTLFLAG_RD, &zynq_reboot_status,
   96            0, "Zynq REBOOT_STATUS register");
   97 
   98 static int ps_clk_frequency;
   99 SYSCTL_INT(_hw_zynq, OID_AUTO, ps_clk_frequency, CTLFLAG_RD, &ps_clk_frequency,
  100            0, "Zynq PS_CLK Frequency");
  101 
  102 static int io_pll_frequency;
  103 SYSCTL_INT(_hw_zynq, OID_AUTO, io_pll_frequency, CTLFLAG_RD, &io_pll_frequency,
  104            0, "Zynq IO PLL Frequency");
  105 
  106 static int arm_pll_frequency;
  107 SYSCTL_INT(_hw_zynq, OID_AUTO, arm_pll_frequency, CTLFLAG_RD,
  108            &arm_pll_frequency, 0, "Zynq ARM PLL Frequency");
  109 
  110 static int ddr_pll_frequency;
  111 SYSCTL_INT(_hw_zynq, OID_AUTO, ddr_pll_frequency, CTLFLAG_RD,
  112            &ddr_pll_frequency, 0, "Zynq DDR PLL Frequency");
  113 
  114 static void
  115 zy7_slcr_unlock(struct zy7_slcr_softc *sc)
  116 {
  117 
  118         /* Unlock SLCR with magic number. */
  119         WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC);
  120 }
  121 
  122 static void
  123 zy7_slcr_lock(struct zy7_slcr_softc *sc)
  124 {
  125 
  126         /* Lock SLCR with magic number. */
  127         WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC);
  128 }
  129 
  130 static void
  131 zy7_slcr_cpu_reset(void)
  132 {
  133         struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
  134 
  135         /* Unlock SLCR registers. */
  136         zy7_slcr_unlock(sc);
  137 
  138         /* This has something to do with a work-around so the fsbl will load
  139          * the bitstream after soft-reboot.  It's very important.
  140          */
  141         WR4(sc, ZY7_SLCR_REBOOT_STAT,
  142             RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff);
  143 
  144         /* Soft reset */
  145         WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET);
  146 
  147         for (;;)
  148                 ;
  149 }
  150 
  151 /* Assert PL resets and disable level shifters in preparation of programming
  152  * the PL (FPGA) section.  Called from zy7_devcfg.c.
  153  */
  154 void
  155 zy7_slcr_preload_pl(void)
  156 {
  157         struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
  158 
  159         if (!sc)
  160                 return;
  161 
  162         ZSLCR_LOCK(sc);
  163 
  164         /* Unlock SLCR registers. */
  165         zy7_slcr_unlock(sc);
  166 
  167         /* Assert top level output resets. */
  168         WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL);
  169 
  170         /* Disable all level shifters. */
  171         WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0);
  172 
  173         /* Lock SLCR registers. */
  174         zy7_slcr_lock(sc);
  175 
  176         ZSLCR_UNLOCK(sc);
  177 }
  178 
  179 /* After PL configuration, enable level shifters and deassert top-level
  180  * PL resets.  Called from zy7_devcfg.c.  Optionally, the level shifters
  181  * can be left disabled but that's rare of an FPGA application. That option
  182  * is controlled by a sysctl in the devcfg driver.
  183  */
  184 void
  185 zy7_slcr_postload_pl(int en_level_shifters)
  186 {
  187         struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
  188 
  189         if (!sc)
  190                 return;
  191 
  192         ZSLCR_LOCK(sc);
  193 
  194         /* Unlock SLCR registers. */
  195         zy7_slcr_unlock(sc);
  196 
  197         if (en_level_shifters)
  198                 /* Enable level shifters. */
  199                 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL);
  200 
  201         /* Deassert top level output resets. */
  202         WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0);
  203 
  204         /* Lock SLCR registers. */
  205         zy7_slcr_lock(sc);
  206 
  207         ZSLCR_UNLOCK(sc);
  208 }
  209 
  210 /* Override cgem_set_refclk() in gigabit ethernet driver
  211  * (sys/dev/cadence/if_cgem.c).  This function is called to
  212  * request a change in the gem's reference clock speed.
  213  */
  214 int
  215 cgem_set_ref_clk(int unit, int frequency)
  216 {
  217         struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
  218         int div0, div1;
  219 
  220         if (!sc)
  221                 return (-1);
  222 
  223         /* Find suitable divisor pairs.  Round result to nearest khz
  224          * to test for match.
  225          */
  226         for (div1 = 1; div1 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) {
  227                 div0 = (io_pll_frequency + div1 * frequency / 2) /
  228                         div1 / frequency;
  229                 if (div0 > 0 && div0 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX &&
  230                     ((io_pll_frequency / div0 / div1) + 500) / 1000 ==
  231                     (frequency + 500) / 1000)
  232                         break;
  233         }
  234 
  235         if (div1 > ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX)
  236                 return (-1);
  237 
  238         ZSLCR_LOCK(sc);
  239 
  240         /* Unlock SLCR registers. */
  241         zy7_slcr_unlock(sc);
  242 
  243         /* Modify GEM reference clock. */
  244         WR4(sc, unit ? ZY7_SLCR_GEM1_CLK_CTRL : ZY7_SLCR_GEM0_CLK_CTRL,
  245             (div1 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT) |
  246             (div0 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT) |
  247             ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_IO_PLL |
  248             ZY7_SLCR_GEM_CLK_CTRL_CLKACT);
  249 
  250         /* Lock SLCR registers. */
  251         zy7_slcr_lock(sc);
  252 
  253         ZSLCR_UNLOCK(sc);
  254 
  255         return (0);
  256 }
  257 
  258 /* 
  259  * PL clocks management function
  260  */
  261 int 
  262 zy7_pl_fclk_set_source(int unit, int source)
  263 {
  264         struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
  265         uint32_t reg;
  266 
  267         if (!sc)
  268                 return (-1);
  269 
  270         ZSLCR_LOCK(sc);
  271 
  272         /* Unlock SLCR registers. */
  273         zy7_slcr_unlock(sc);
  274 
  275         /* Modify FPGAx source. */
  276         reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
  277         reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK);
  278         reg |= (source << ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT);
  279         WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);
  280 
  281         /* Lock SLCR registers. */
  282         zy7_slcr_lock(sc);
  283 
  284         ZSLCR_UNLOCK(sc);
  285 
  286         return (0);
  287 }
  288 
  289 int 
  290 zy7_pl_fclk_get_source(int unit)
  291 {
  292         struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
  293         uint32_t reg;
  294         int source;
  295 
  296         if (!sc)
  297                 return (-1);
  298 
  299         ZSLCR_LOCK(sc);
  300 
  301         /* Modify GEM reference clock. */
  302         reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
  303         source = (reg & ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK) >> 
  304             ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT;
  305 
  306         /* ZY7_PL_FCLK_SRC_IO is actually b0x */
  307         if ((source & 2) == 0)
  308                 source = ZY7_PL_FCLK_SRC_IO;
  309 
  310         ZSLCR_UNLOCK(sc);
  311 
  312         return (source);
  313 }
  314 
  315 int
  316 zy7_pl_fclk_set_freq(int unit, int frequency)
  317 {
  318         struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
  319         int div0, div1;
  320         int base_frequency;
  321         uint32_t reg;
  322         int source;
  323 
  324         if (!sc)
  325                 return (-1);
  326 
  327         source = zy7_pl_fclk_get_source(unit);
  328         switch (source) {
  329                 case ZY7_PL_FCLK_SRC_IO:
  330                         base_frequency = io_pll_frequency;
  331                         break;
  332 
  333                 case ZY7_PL_FCLK_SRC_ARM:
  334                         base_frequency = arm_pll_frequency;
  335                         break;
  336 
  337                 case ZY7_PL_FCLK_SRC_DDR:
  338                         base_frequency = ddr_pll_frequency;
  339                         break;
  340 
  341                 default:
  342                         return (-1);
  343         }
  344 
  345         /* Find suitable divisor pairs.  Round result to nearest khz
  346          * to test for match.
  347          */
  348         for (div1 = 1; div1 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX; div1++) {
  349                 div0 = (base_frequency + div1 * frequency / 2) /
  350                         div1 / frequency;
  351                 if (div0 > 0 && div0 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX &&
  352                     ((base_frequency / div0 / div1) + 500) / 1000 ==
  353                     (frequency + 500) / 1000)
  354                         break;
  355         }
  356 
  357         if (div1 > ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX)
  358                 return (-1);
  359 
  360         ZSLCR_LOCK(sc);
  361 
  362         /* Unlock SLCR registers. */
  363         zy7_slcr_unlock(sc);
  364 
  365         /* Modify FPGAx reference clock. */
  366         reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
  367         reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK |
  368             ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK);
  369         reg |= (div1 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT) |
  370             (div0 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT);
  371         WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);
  372 
  373         /* Lock SLCR registers. */
  374         zy7_slcr_lock(sc);
  375 
  376         ZSLCR_UNLOCK(sc);
  377 
  378         return (base_frequency / div0 / div1);
  379 }
  380 
  381 int
  382 zy7_pl_fclk_get_freq(int unit)
  383 {
  384         struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
  385         int div0, div1;
  386         int base_frequency;
  387         int frequency;
  388         uint32_t reg;
  389         int source;
  390 
  391         if (!sc)
  392                 return (-1);
  393 
  394         source = zy7_pl_fclk_get_source(unit);
  395         switch (source) {
  396                 case ZY7_PL_FCLK_SRC_IO:
  397                         base_frequency = io_pll_frequency;
  398                         break;
  399 
  400                 case ZY7_PL_FCLK_SRC_ARM:
  401                         base_frequency = arm_pll_frequency;
  402                         break;
  403 
  404                 case ZY7_PL_FCLK_SRC_DDR:
  405                         base_frequency = ddr_pll_frequency;
  406                         break;
  407 
  408                 default:
  409                         return (-1);
  410         }
  411 
  412         ZSLCR_LOCK(sc);
  413 
  414         /* Modify FPGAx reference clock. */
  415         reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
  416         div1 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK) >>
  417             ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT;
  418         div0 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK) >>
  419             ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT;
  420 
  421         ZSLCR_UNLOCK(sc);
  422 
  423         if (div0 == 0)
  424                 div0 = 1;
  425 
  426         if (div1 == 0)
  427                 div1 = 1;
  428 
  429         frequency = (base_frequency / div0 / div1);
  430         /* Round to KHz */
  431         frequency = (frequency + 500) / 1000;
  432         frequency = frequency * 1000;
  433 
  434         return (frequency);
  435 }
  436 
  437 int 
  438 zy7_pl_fclk_enable(int unit)
  439 {
  440         struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
  441 
  442         if (!sc)
  443                 return (-1);
  444 
  445         ZSLCR_LOCK(sc);
  446 
  447         /* Unlock SLCR registers. */
  448         zy7_slcr_unlock(sc);
  449 
  450         WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0);
  451         WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 0);
  452 
  453         /* Lock SLCR registers. */
  454         zy7_slcr_lock(sc);
  455 
  456         ZSLCR_UNLOCK(sc);
  457 
  458         return (0);
  459 }
  460 
  461 int 
  462 zy7_pl_fclk_disable(int unit)
  463 {
  464         struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
  465 
  466         if (!sc)
  467                 return (-1);
  468 
  469         ZSLCR_LOCK(sc);
  470 
  471         /* Unlock SLCR registers. */
  472         zy7_slcr_unlock(sc);
  473 
  474         WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0);
  475         WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 1);
  476 
  477         /* Lock SLCR registers. */
  478         zy7_slcr_lock(sc);
  479 
  480         ZSLCR_UNLOCK(sc);
  481 
  482         return (0);
  483 }
  484 
  485 int 
  486 zy7_pl_fclk_enabled(int unit)
  487 {
  488         struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
  489         uint32_t reg;
  490 
  491         if (!sc)
  492                 return (-1);
  493 
  494         ZSLCR_LOCK(sc);
  495         reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit));
  496         ZSLCR_UNLOCK(sc);
  497 
  498         return !(reg & 1);
  499 }
  500 
  501 int
  502 zy7_pl_level_shifters_enabled(void)
  503 {
  504         struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
  505 
  506         uint32_t reg;
  507 
  508         if (!sc)
  509                 return (-1);
  510 
  511         ZSLCR_LOCK(sc);
  512         reg = RD4(sc, ZY7_SLCR_LVL_SHFTR_EN);
  513         ZSLCR_UNLOCK(sc);
  514 
  515         return (reg == ZY7_SLCR_LVL_SHFTR_EN_ALL);
  516 }
  517 
  518 void
  519 zy7_pl_level_shifters_enable(void)
  520 {
  521         struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
  522 
  523         if (!sc)
  524                 return;
  525 
  526         ZSLCR_LOCK(sc);
  527         zy7_slcr_unlock(sc);
  528         WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL);
  529         zy7_slcr_lock(sc);
  530         ZSLCR_UNLOCK(sc);
  531 }
  532 
  533 void
  534 zy7_pl_level_shifters_disable(void)
  535 {
  536         struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
  537 
  538         if (!sc)
  539                 return;
  540 
  541         ZSLCR_LOCK(sc);
  542         zy7_slcr_unlock(sc);
  543         WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0);
  544         zy7_slcr_lock(sc);
  545         ZSLCR_UNLOCK(sc);
  546 }
  547 
  548 static int
  549 zy7_slcr_probe(device_t dev)
  550 {
  551 
  552         if (!ofw_bus_status_okay(dev))
  553                 return (ENXIO);
  554 
  555         if (!ofw_bus_is_compatible(dev, "xlnx,zy7_slcr"))
  556                 return (ENXIO);
  557 
  558         device_set_desc(dev, "Zynq-7000 slcr block");
  559         return (0);
  560 }
  561 
  562 static int
  563 zy7_slcr_attach(device_t dev)
  564 {
  565         struct zy7_slcr_softc *sc = device_get_softc(dev);
  566         int rid;
  567         phandle_t node;
  568         pcell_t cell;
  569         uint32_t bootmode;
  570         uint32_t pss_idcode;
  571         uint32_t arm_pll_ctrl;
  572         uint32_t ddr_pll_ctrl;
  573         uint32_t io_pll_ctrl;
  574         static char *bootdev_names[] = {
  575                 "JTAG", "Quad-SPI", "NOR", "(3?)",
  576                 "NAND", "SD Card", "(6?)", "(7?)"
  577         };
  578 
  579         /* Allow only one attach. */
  580         if (zy7_slcr_softc_p != NULL)
  581                 return (ENXIO);
  582 
  583         sc->dev = dev;
  584 
  585         ZSLCR_LOCK_INIT(sc);
  586 
  587         /* Get memory resource. */
  588         rid = 0;
  589         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
  590                                              RF_ACTIVE);
  591         if (sc->mem_res == NULL) {
  592                 device_printf(dev, "could not allocate memory resources.\n");
  593                 return (ENOMEM);
  594         }
  595 
  596         /* Hook up cpu_reset. */
  597         zy7_slcr_softc_p = sc;
  598         zynq7_cpu_reset = zy7_slcr_cpu_reset;
  599 
  600         /* Read info and set sysctls. */
  601         bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE);
  602         snprintf(zynq_bootmode, sizeof(zynq_bootmode),
  603                  "0x%x: boot device: %s", bootmode,
  604                  bootdev_names[bootmode & ZY7_SLCR_BOOT_MODE_BOOTDEV_MASK]);
  605 
  606         pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE);
  607         snprintf(zynq_pssid, sizeof(zynq_pssid),
  608                  "0x%x: manufacturer: 0x%x device: 0x%x "
  609                  "family: 0x%x sub-family: 0x%x rev: 0x%x",
  610                  pss_idcode,
  611                  (pss_idcode & ZY7_SLCR_PSS_IDCODE_MNFR_ID_MASK) >>
  612                  ZY7_SLCR_PSS_IDCODE_MNFR_ID_SHIFT,
  613                  (pss_idcode & ZY7_SLCR_PSS_IDCODE_DEVICE_MASK) >>
  614                  ZY7_SLCR_PSS_IDCODE_DEVICE_SHIFT,
  615                  (pss_idcode & ZY7_SLCR_PSS_IDCODE_FAMILY_MASK) >>
  616                  ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT,
  617                  (pss_idcode & ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK) >>
  618                  ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT,
  619                  (pss_idcode & ZY7_SLCR_PSS_IDCODE_REVISION_MASK) >>
  620                  ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT);
  621 
  622         zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT);
  623 
  624         /* Derive PLL frequencies from PS_CLK. */
  625         node = ofw_bus_get_node(dev);
  626         if (OF_getencprop(node, "clock-frequency", &cell, sizeof(cell)) > 0)
  627                 ps_clk_frequency = cell;
  628         else
  629                 ps_clk_frequency = ZYNQ_DEFAULT_PS_CLK_FREQUENCY;
  630 
  631         arm_pll_ctrl = RD4(sc, ZY7_SLCR_ARM_PLL_CTRL);
  632         ddr_pll_ctrl = RD4(sc, ZY7_SLCR_DDR_PLL_CTRL);
  633         io_pll_ctrl = RD4(sc, ZY7_SLCR_IO_PLL_CTRL);
  634 
  635         /* Determine ARM PLL frequency. */
  636         if (((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
  637              (arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
  638             ((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
  639              (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
  640                 /* PLL is bypassed. */
  641                 arm_pll_frequency = ps_clk_frequency;
  642         else
  643                 arm_pll_frequency = ps_clk_frequency *
  644                         ((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
  645                          ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
  646 
  647         /* Determine DDR PLL frequency. */
  648         if (((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
  649              (ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
  650             ((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
  651              (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
  652                 /* PLL is bypassed. */
  653                 ddr_pll_frequency = ps_clk_frequency;
  654         else
  655                 ddr_pll_frequency = ps_clk_frequency *
  656                         ((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
  657                          ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
  658 
  659         /* Determine IO PLL frequency. */
  660         if (((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
  661              (io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
  662             ((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
  663              (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
  664                 /* PLL is bypassed. */
  665                 io_pll_frequency = ps_clk_frequency;
  666         else
  667                 io_pll_frequency = ps_clk_frequency *
  668                         ((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
  669                          ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
  670 
  671         /* Lock SLCR registers. */
  672         zy7_slcr_lock(sc);
  673 
  674         return (0);
  675 }
  676 
  677 static int
  678 zy7_slcr_detach(device_t dev)
  679 {
  680         struct zy7_slcr_softc *sc = device_get_softc(dev);
  681 
  682         bus_generic_detach(dev);
  683 
  684         /* Release memory resource. */
  685         if (sc->mem_res != NULL)
  686                 bus_release_resource(dev, SYS_RES_MEMORY,
  687                              rman_get_rid(sc->mem_res), sc->mem_res);
  688 
  689         zy7_slcr_softc_p = NULL;
  690         zynq7_cpu_reset = NULL;
  691 
  692         ZSLCR_LOCK_DESTROY(sc);
  693 
  694         return (0);
  695 }
  696 
  697 static device_method_t zy7_slcr_methods[] = {
  698         /* device_if */
  699         DEVMETHOD(device_probe,         zy7_slcr_probe),
  700         DEVMETHOD(device_attach,        zy7_slcr_attach),
  701         DEVMETHOD(device_detach,        zy7_slcr_detach),
  702 
  703         DEVMETHOD_END
  704 };
  705 
  706 static driver_t zy7_slcr_driver = {
  707         "zy7_slcr",
  708         zy7_slcr_methods,
  709         sizeof(struct zy7_slcr_softc),
  710 };
  711 static devclass_t zy7_slcr_devclass;
  712 
  713 DRIVER_MODULE(zy7_slcr, simplebus, zy7_slcr_driver, zy7_slcr_devclass, 0, 0);
  714 MODULE_VERSION(zy7_slcr, 1);
Cache object: 921d25655ca3a229ef48e3951160e33b
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FreeBSD/Linux Kernel Cross Reference sys/arm/xilinx/zy7_slcr.c

FreeBSD/Linux Kernel Cross Reference
sys/arm/xilinx/zy7_slcr.c
