1 /*-
2 * Copyright (c) 2013 Thomas Skibo
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: releng/10.0/sys/arm/xilinx/zy7_slcr.h 250015 2013-04-28 07:00:36Z wkoszek $
27 */
28
29 /*
30 * Defines for Zynq-7000 SLCR registers.
31 *
32 * Most of these registers are initialized by the First Stage Boot
33 * Loader and are not modified by the kernel.
34 *
35 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
36 * (v1.4) November 16, 2012. Xilinx doc UG585. SLCR register definitions
37 * are in appendix B.28.
38 */
39
40
41 #ifndef _ZY7_SLCR_H_
42 #define _ZY7_SLCR_H_
43
44 #define ZY7_SCLR_SCL 0x0000
45 #define ZY7_SLCR_LOCK 0x0004
46 #define ZY7_SLCR_LOCK_MAGIC 0x767b
47 #define ZY7_SLCR_UNLOCK 0x0008
48 #define ZY7_SLCR_UNLOCK_MAGIC 0xdf0d
49 #define ZY7_SLCR_LOCKSTA 0x000c
50
51 /* PLL controls. */
52 #define ZY7_SLCR_ARM_PLL_CTRL 0x0100
53 #define ZY7_SLCR_DDR_PLL_CTRL 0x0104
54 #define ZY7_SLCR_IO_PLL_CTRL 0x0108
55 #define ZY7_SLCR_PLL_CTRL_RESET (1<<0)
56 #define ZY7_SLCR_PLL_CTRL_PWRDWN (1<<1)
57 #define ZY7_SLCR_PLL_CTRL_BYPASS_QUAL (1<<3)
58 #define ZY7_SLCR_PLL_CTRL_BYPASS_FORCE (1<<4)
59 #define ZY7_SLCR_PLL_CTRL_FDIV_SHIFT 12
60 #define ZY7_SLCR_PLL_CTRL_FDIV_MASK (0x7f<<12)
61 #define ZY7_SLCR_PLL_STATUS 0x010c
62 #define ZY7_SLCR_PLL_STAT_ARM_PLL_LOCK (1<<0)
63 #define ZY7_SLCR_PLL_STAT_DDR_PLL_LOCK (1<<1)
64 #define ZY7_SLCR_PLL_STAT_IO_PLL_LOCK (1<<2)
65 #define ZY7_SLCR_PLL_STAT_ARM_PLL_STABLE (1<<3)
66 #define ZY7_SLCR_PLL_STAT_DDR_PLL_STABLE (1<<4)
67 #define ZY7_SLCR_PLL_STAT_IO_PLL_STABLE (1<<5)
68 #define ZY7_SLCR_ARM_PLL_CFG 0x0110
69 #define ZY7_SLCR_DDR_PLL_CFG 0x0114
70 #define ZY7_SLCR_IO_PLL_CFG 0x0118
71 #define ZY7_SLCR_PLL_CFG_RES_SHIFT 4
72 #define ZY7_SLCR_PLL_CFG_RES_MASK (0xf<<4)
73 #define ZY7_SLCR_PLL_CFG_PLL_CP_SHIFT 8
74 #define ZY7_SLCR_PLL_CFG_PLL_CP_MASK (0xf<<8)
75 #define ZY7_SLCR_PLL_CFG_LOCK_CNT_SHIFT 12
76 #define ZY7_SLCR_PLL_CFG_LOCK_CNT_MASK (0x3ff<<12)
77
78 /* Clock controls. */
79 #define ZY7_SLCR_ARM_CLK_CTRL 0x0120
80 #define ZY7_SLCR_ARM_CLK_CTRL_CPU_PERI_CLKACT (1<<28)
81 #define ZY7_SLCR_ARM_CLK_CTRL_CPU_1XCLKACT (1<<27)
82 #define ZY7_SLCR_ARM_CLK_CTRL_CPU_2XCLKACT (1<<26)
83 #define ZY7_SLCR_ARM_CLK_CTRL_CPU_3OR2XCLKACT (1<<25)
84 #define ZY7_SLCR_ARM_CLK_CTRL_CPU_6OR4XCLKACT (1<<24)
85 #define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_MASK (3<<4)
86 #define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_ARM_PLL (0<<4)
87 #define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_DDR_PLL (2<<4)
88 #define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_IO_PLL (3<<4)
89 #define ZY7_SLCR_ARM_CLK_CTRL_DIVISOR_SHIFT 8
90 #define ZY7_SLCR_ARM_CLK_CTRL_DIVISOR_MASK (0x3f<<8)
91 #define ZY7_SLCR_DDR_CLK_CTRL 0x0124
92 #define ZY7_SLCR_DDR_CLK_CTRL_2XCLK_DIV_SHIFT 26
93 #define ZY7_SLCR_DDR_CLK_CTRL_2XCLK_DIV_MASK (0x3f<<26)
94 #define ZY7_SLCR_DDR_CLK_CTRL_3XCLK_DIV_SHIFT 20
95 #define ZY7_SLCR_DDR_CLK_CTRL_3XCLK_DIV_MASK (0x3f<<20)
96 #define ZY7_SLCR_DDR_CLK_CTRL_2XCLKACT (1<<1)
97 #define ZY7_SLCR_DDR_CLK_CTRL_3XCLKACT (1<<0)
98 #define ZY7_SLCR_DCI_CLK_CTRL 0x0128
99 #define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR1_SHIFT 20
100 #define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR1_MASK (0x3f<<20)
101 #define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR0_SHIFT 8
102 #define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR0_MASK (0x3f<<8)
103 #define ZY7_SLCR_DCI_CLK_CTRL_CLKACT (1<<0)
104 #define ZY7_SLCR_APER_CLK_CTRL 0x012c /* amba periph clk ctrl */
105 #define ZY7_SLCR_APER_CLK_CTRL_SMC_CPU_1XCLKACT (1<<24)
106 #define ZY7_SLCR_APER_CLK_CTRL_LQSPI_CPU_1XCLKACT (1<<23)
107 #define ZY7_SLCR_APER_CLK_CTRL_GPIO_CPU_1XCLKACT (1<<22)
108 #define ZY7_SLCR_APER_CLK_CTRL_UART1_CPU_1XCLKACT (1<<21)
109 #define ZY7_SLCR_APER_CLK_CTRL_UART0_CPU_1XCLKACT (1<<20)
110 #define ZY7_SLCR_APER_CLK_CTRL_I2C1_CPU_1XCLKACT (1<<19)
111 #define ZY7_SLCR_APER_CLK_CTRL_I2C0_CPU_1XCLKACT (1<<18)
112 #define ZY7_SLCR_APER_CLK_CTRL_CAN1_CPU_1XCLKACT (1<<17)
113 #define ZY7_SLCR_APER_CLK_CTRL_CAN0_CPU_1XCLKACT (1<<16)
114 #define ZY7_SLCR_APER_CLK_CTRL_SPI1_CPU_1XCLKACT (1<<15)
115 #define ZY7_SLCR_APER_CLK_CTRL_SPI0_CPU_1XCLKACT (1<<14)
116 #define ZY7_SLCR_APER_CLK_CTRL_SDI1_CPU_1XCLKACT (1<<11)
117 #define ZY7_SLCR_APER_CLK_CTRL_SDI0_CPU_1XCLKACT (1<<10)
118 #define ZY7_SLCR_APER_CLK_CTRL_GEM1_CPU_1XCLKACT (1<<7)
119 #define ZY7_SLCR_APER_CLK_CTRL_GEM0_CPU_1XCLKACT (1<<6)
120 #define ZY7_SLCR_APER_CLK_CTRL_USB1_CPU_1XCLKACT (1<<3)
121 #define ZY7_SLCR_APER_CLK_CTRL_USB0_CPU_1XCLKACT (1<<2)
122 #define ZY7_SLCR_APER_CLK_CTRL_DMA_CPU_1XCLKACT (1<<0)
123 #define ZY7_SLCR_USB0_CLK_CTRL 0x0130
124 #define ZY7_SLCR_USB1_CLK_CTRL 0x0134
125 #define ZY7_SLCR_GEM0_RCLK_CTRL 0x0138
126 #define ZY7_SLCR_GEM1_RCLK_CTRL 0x013c
127 #define ZY7_SLCR_GEM0_CLK_CTRL 0x0140
128 #define ZY7_SLCR_GEM1_CLK_CTRL 0x0144
129 #define ZY7_SLCR_SMC_CLK_CTRL 0x0148
130 #define ZY7_SLCR_LQSPI_CLK_CTRL 0x014c
131 #define ZY7_SLCR_SDIO_CLK_CTRL 0x0150
132 #define ZY7_SLCR_UART_CLK_CTRL 0x0154
133 #define ZY7_SLCR_SPI_CLK_CTRL 0x0158
134 #define ZY7_SLCR_CAN_CLK_CTRL 0x015c
135 #define ZY7_SLCR_CAN_MIOCLK_CTRL 0x0160
136 #define ZY7_SLCR_DBG_CLK_CTRL 0x0164
137 #define ZY7_SLCR_PCAP_CLK_CTRL 0x0168
138 #define ZY7_SLCR_TOPSW_CLK_CTRL 0x016c /* central intercnn clk ctrl */
139 #define ZY7_SLCR_FPGA0_CLK_CTRL 0x0170
140 #define ZY7_SLCR_FPGA1_CLK_CTRL 0x0180
141 #define ZY7_SLCR_FPGA2_CLK_CTRL 0x0190
142 #define ZY7_SLCR_FPGA3_CLK_CTRL 0x01a0
143 #define ZY7_SLCR_CLK_621_TRUE 0x01c4 /* cpu clock ratio mode */
144
145 /* Reset controls. */
146 #define ZY7_SLCR_PSS_RST_CTRL 0x0200
147 #define ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET (1<<0)
148 #define ZY7_SLCR_DDR_RST_CTRL 0x0204
149 #define ZY7_SLCR_TOPSW_RST_CTRL 0x0208
150 #define ZY7_SLCR_DMAC_RST_CTRL 0x020c
151 #define ZY7_SLCR_USB_RST_CTRL 0x0210
152 #define ZY7_SLCR_GEM_RST_CTRL 0x0214
153 #define ZY7_SLCR_SDIO_RST_CTRL 0x0218
154 #define ZY7_SLCR_SPI_RST_CTRL 0x021c
155 #define ZY7_SLCR_CAN_RST_CTRL 0x0220
156 #define ZY7_SLCR_I2C_RST_CTRL 0x0224
157 #define ZY7_SLCR_UART_RST_CTRL 0x0228
158 #define ZY7_SLCR_GPIO_RST_CTRL 0x022c
159 #define ZY7_SLCR_LQSPI_RST_CTRL 0x0230
160 #define ZY7_SLCR_SMC_RST_CTRL 0x0234
161 #define ZY7_SLCR_OCM_RST_CTRL 0x0238
162 #define ZY7_SLCR_DEVCI_RST_CTRL 0x023c
163 #define ZY7_SLCR_FPGA_RST_CTRL 0x0240
164 #define ZY7_SLCR_FPGA_RST_CTRL_FPGA3_OUT_RST (1<<3)
165 #define ZY7_SLCR_FPGA_RST_CTRL_FPGA2_OUT_RST (1<<2)
166 #define ZY7_SLCR_FPGA_RST_CTRL_FPGA1_OUT_RST (1<<1)
167 #define ZY7_SLCR_FPGA_RST_CTRL_FPGA0_OUT_RST (1<<0)
168 #define ZY7_SLCR_FPGA_RST_CTRL_RST_ALL 0xf
169 #define ZY7_SLCR_A9_CPU_RST_CTRL 0x0244
170 #define ZY7_SLCR_RS_AWDT_CTRL 0x024c
171
172 #define ZY7_SLCR_REBOOT_STAT 0x0258
173 #define ZY7_SLCR_REBOOT_STAT_STATE_MASK (0xff<<24)
174 #define ZY7_SLCR_REBOOT_STAT_POR (1<<22)
175 #define ZY7_SLCR_REBOOT_STAT_SRST_B (1<<21)
176 #define ZY7_SLCR_REBOOT_STAT_DBG_RST (1<<20)
177 #define ZY7_SLCR_REBOOT_STAT_SLC_RST (1<<19)
178 #define ZY7_SLCR_REBOOT_STAT_AWDT1_RST (1<<18)
179 #define ZY7_SLCR_REBOOT_STAT_AWDT0_RST (1<<17)
180 #define ZY7_SLCR_REBOOT_STAT_SWDT_RST (1<<16)
181 #define ZY7_SLCR_REBOOT_STAT_BOOTROM_ERR_CODE_MASK (0xffff)
182 #define ZY7_SLCR_BOOT_MODE 0x025c
183 #define ZY7_SLCR_BOOT_MODE_PLL_BYPASS (1<<4)
184 #define ZY7_SLCR_BOOT_MODE_JTAG_INDEP (1<<3)
185 #define ZY7_SLCR_BOOT_MODE_BOOTDEV_MASK 7
186 #define ZY7_SLCR_BOOT_MODE_BOOTDEV_JTAG 0
187 #define ZY7_SLCR_BOOT_MODE_BOOTDEV_QUAD_SPI 1
188 #define ZY7_SLCR_BOOT_MODE_BOOTDEV_NOR 2
189 #define ZY7_SLCR_BOOT_MODE_BOOTDEV_NAND 4
190 #define ZY7_SLCR_BOOT_MODE_BOOTDEV_SD_CARD 5
191 #define ZY7_SLCR_APU_CTRL 0x0300
192 #define ZY7_SLCR_WDT_CLK_SEL 0x0304
193
194 #define ZY7_SLCR_PSS_IDCODE 0x0530
195 #define ZY7_SLCR_PSS_IDCODE_REVISION_MASK (0xf<<28)
196 #define ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT 28
197 #define ZY7_SLCR_PSS_IDCODE_FAMILY_MASK (0x7f<<21)
198 #define ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT 21
199 #define ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK (0xf<<17)
200 #define ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT 17
201 #define ZY7_SLCR_PSS_IDCODE_DEVICE_MASK (0x1f<<12)
202 #define ZY7_SLCR_PSS_IDCODE_DEVICE_SHIFT 12
203 #define ZY7_SLCR_PSS_IDCODE_MNFR_ID_MASK (0x7ff<<1)
204 #define ZY7_SLCR_PSS_IDCODE_MNFR_ID_SHIFT 1
205
206 #define ZY7_SLCR_DDR_URGENT 0x0600
207 #define ZY7_SLCR_DDR_CAL_START 0x060c
208 #define ZY7_SLCR_DDR_REF_START 0x0614
209 #define ZY7_SLCR_DDR_CMD_STA 0x0618
210 #define ZY7_SLCR_DDR_URGENT_SEL 0x061c
211 #define ZY7_SLCR_DDR_DFI_STATUS 0x0620
212
213 /* MIO Pin controls */
214 #define ZY7_SLCR_MIO_PIN(n) (0x0700+(n)*4) /* 0-53 */
215 #define ZY7_SLCR_MIO_PIN_RCVR_DIS (1<<13)
216 #define ZY7_SLCR_MIO_PIN_PULLUP_EN (1<<12)
217 #define ZY7_SLCR_MIO_PIN_IO_TYPE_MASK (7<<9)
218 #define ZY7_SLCR_MIO_PIN_IO_TYPE_LVTTL (0<<9)
219 #define ZY7_SLCR_MIO_PIN_IO_TYPE_LVCMOS18 (1<<9)
220 #define ZY7_SLCR_MIO_PIN_IO_TYPE_LVCMOS25 (2<<9)
221 #define ZY7_SLCR_MIO_PIN_IO_TYPE_LVCMOS33 (3<<9)
222 #define ZY7_SLCR_MIO_PIN_IO_TYPE_HSTL (4<<9)
223 #define ZY7_SLCR_MIO_PIN_L2_SEL_MASK (3<<3)
224 #define ZY7_SLCR_MIO_PIN_L2_SEL_L3_MUX (0<<3)
225 #define ZY7_SLCR_MIO_PIN_L2_SEL_SRAM_NOR_CS0 (1<<3)
226 #define ZY7_SLCR_MIO_PIN_L2_SEL_NAND_CS (2<<3)
227 #define ZY7_SLCR_MIO_PIN_L2_SEL_SDIO0_PC (3<<3)
228 #define ZY7_SLCR_MIO_PIN_L1_SEL (1<<2)
229 #define ZY7_SLCR_MIO_PIN_L0_SEL (1<<1)
230 #define ZY7_SLCR_MIO_PIN_TRI_EN (1<<0)
231
232 #define ZY7_SLCR_MIO_LOOPBACK 0x0804
233 #define ZY7_SLCR_MIO_LOOPBACK_I2C0_I2C1 (1<<3)
234 #define ZY7_SLCR_MIO_LOOPBACK_CAN0_CAN1 (1<<2)
235 #define ZY7_SLCR_MIO_LOOPBACK_UA0_UA1 (1<<1)
236 #define ZY7_SLCR_MIO_LOOPBACK_SPI0_SPI1 (1<<0)
237 #define ZY7_SLCR_MIO_MST_TRI0 0x080c
238 #define ZY7_SLCR_MIO_MST_TRI1 0x0810
239 #define ZY7_SLCR_SD0_WP_CD_SEL 0x0830
240 #define ZY7_SLCR_SD1_WP_CD_SEL 0x0834
241
242 /* PS-PL level shifter control. */
243 #define ZY7_SLCR_LVL_SHFTR_EN 0x900
244 #define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_IN_EN_0 (1<<3) /* PL to PS */
245 #define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_OUT_EN_0 (1<<2) /* PS to PL */
246 #define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_IN_EN_1 (1<<1) /* PL to PS */
247 #define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_OUT_EN_1 (1<<0) /* PS to PL */
248 #define ZY7_SLCR_LVL_SHFTR_EN_ALL 0xf
249
250 #define ZY7_SLCR_OCM_CFG 0x0910
251
252 #define ZY7_SLCR_GPIOB_CTRL 0x0b00
253 #define ZY7_SLCR_GPIOB_CFG_CMOS18 0x0b04
254 #define ZY7_SLCR_GPIOB_CFG_CMOS25 0x0b08
255 #define ZY7_SLCR_GPIOB_CFG_CMOS33 0x0b0c
256 #define ZY7_SLCR_GPIOB_CFG_LVTTL 0x0b10
257 #define ZY7_SLCR_GPIOB_CFG_HSTL 0x0b14
258 #define ZY7_SLCR_GPIOB_DRVR_BIAS_CTRL 0x0b18
259
260 #define ZY7_SLCR_DDRIOB_ADDR0 0x0b40
261 #define ZY7_SLCR_DDRIOB_ADDR1 0x0b44
262 #define ZY7_SLCR_DDRIOB_DATA0 0x0b48
263 #define ZY7_SLCR_DDRIOB_DATA1 0x0b4c
264 #define ZY7_SLCR_DDRIOB_DIFF0 0x0b50
265 #define ZY7_SLCR_DDRIOB_DIFF1 0x0b54
266 #define ZY7_SLCR_DDRIOB_CLK 0x0b58
267 #define ZY7_SLCR_DDRIOB_DRIVE_SLEW_ADDR 0x0b5c
268 #define ZY7_SLCR_DDRIOB_DRIVE_SLEW_DATA 0x0b60
269 #define ZY7_SLCR_DDRIOB_DRIVE_SLEW_DIFF 0x0b64
270 #define ZY7_SLCR_DDRIOB_DRIVE_SLEW_CLK 0x0b68
271 #define ZY7_SLCR_DDRIOB_DDR_CTRL 0x0b6c
272 #define ZY7_SLCR_DDRIOB_DCI_CTRL 0x0b70
273 #define ZY7_SLCR_DDRIOB_DCI_STATUS 0x0b74
274
275 #ifdef _KERNEL
276 extern void zy7_slcr_preload_pl(void);
277 extern void zy7_slcr_postload_pl(int);
278 #endif
279 #endif /* _ZY7_SLCR_H_ */
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