1 /* $NetBSD: i80321_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $ */
2
3 /*-
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * PCI configuration support for i80321 I/O Processor chip.
40 */
41
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD: releng/10.4/sys/arm/xscale/i80321/i80321_pci.c 259329 2013-12-13 20:43:11Z ian $");
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/malloc.h>
48 #include <sys/bus.h>
49 #include <sys/kernel.h>
50 #include <sys/module.h>
51 #include <sys/rman.h>
52
53 #include <machine/bus.h>
54 #include <machine/cpu.h>
55 #include <machine/pcb.h>
56 #include <vm/vm.h>
57 #include <vm/pmap.h>
58 #include <vm/vm_extern.h>
59
60 #include <arm/xscale/i80321/i80321reg.h>
61 #include <arm/xscale/i80321/i80321var.h>
62 #include <arm/xscale/i80321/i80321_intr.h>
63
64 #include <dev/pci/pcib_private.h>
65 #include "pcib_if.h"
66
67 #include <dev/pci/pcireg.h>
68 extern struct i80321_softc *i80321_softc;
69
70 static int
71 i80321_pci_probe(device_t dev)
72 {
73 device_set_desc(dev, "i80321 PCI bus");
74 return (0);
75 }
76
77 static int
78 i80321_pci_attach(device_t dev)
79 {
80
81 uint32_t busno;
82 struct i80321_pci_softc *sc = device_get_softc(dev);
83
84 sc->sc_st = i80321_softc->sc_st;
85 sc->sc_atu_sh = i80321_softc->sc_atu_sh;
86 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
87 busno = PCIXSR_BUSNO(busno);
88 if (busno == 0xff)
89 busno = 0;
90 sc->sc_dev = dev;
91 sc->sc_busno = busno;
92 sc->sc_pciio = &i80321_softc->sc_pci_iot;
93 sc->sc_pcimem = &i80321_softc->sc_pci_memt;
94 sc->sc_mem = i80321_softc->sc_owin[0].owin_xlate_lo +
95 VERDE_OUT_XLATE_MEM_WIN_SIZE;
96
97 sc->sc_io = i80321_softc->sc_iow_vaddr;
98 /* Initialize memory and i/o rmans. */
99 sc->sc_io_rman.rm_type = RMAN_ARRAY;
100 sc->sc_io_rman.rm_descr = "I80321 PCI I/O Ports";
101 if (rman_init(&sc->sc_io_rman) != 0 ||
102 rman_manage_region(&sc->sc_io_rman,
103 sc->sc_io,
104 sc->sc_io +
105 VERDE_OUT_XLATE_IO_WIN_SIZE) != 0) {
106 panic("i80321_pci_probe: failed to set up I/O rman");
107 }
108 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
109 sc->sc_mem_rman.rm_descr = "I80321 PCI Memory";
110 if (rman_init(&sc->sc_mem_rman) != 0 ||
111 rman_manage_region(&sc->sc_mem_rman,
112 0, VERDE_OUT_XLATE_MEM_WIN_SIZE) != 0) {
113 panic("i80321_pci_probe: failed to set up memory rman");
114 }
115 sc->sc_irq_rman.rm_type = RMAN_ARRAY;
116 sc->sc_irq_rman.rm_descr = "i80321 PCI IRQs";
117 if (rman_init(&sc->sc_irq_rman) != 0 ||
118 rman_manage_region(&sc->sc_irq_rman, 26, 32) != 0)
119 panic("i80321_pci_probe: failed to set up IRQ rman");
120 device_add_child(dev, "pci",busno);
121 return (bus_generic_attach(dev));
122 }
123
124 static int
125 i80321_pci_maxslots(device_t dev)
126 {
127 return (PCI_SLOTMAX);
128 }
129
130
131
132 static int
133 i80321_pci_conf_setup(struct i80321_pci_softc *sc, int bus, int slot, int func,
134 int reg, uint32_t *addr)
135 {
136 uint32_t busno;
137
138 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
139 busno = PCIXSR_BUSNO(busno);
140 if (busno == 0xff)
141 busno = 0;
142
143 /*
144 * If the bus # is the same as our own, then use Type 0 cycles,
145 * else use Type 1.
146 *
147 * XXX We should filter out all non-private devices here!
148 * XXX How does private space interact with PCI-PCI bridges?
149 */
150 if (bus == busno) {
151 if (slot > (31 - 16))
152 return (1);
153 /*
154 * NOTE: PCI-X requires that that devices updated their
155 * PCIXSR on every config write with the device number
156 * specified in AD[15:11]. If we don't set this field,
157 * each device could end of thinking it is at device 0,
158 * which can cause a number of problems. Doing this
159 * unconditionally should be OK when only PCI devices
160 * are present.
161 */
162 bus &= 0xff;
163 slot &= 0x1f;
164 func &= 0x07;
165
166 *addr = (1U << (slot + 16)) |
167 (slot << 11) | (func << 8) | reg;
168 } else {
169 *addr = (bus << 16) | (slot << 11) | (func << 8) | reg | 1;
170 }
171
172 return (0);
173 }
174
175 static u_int32_t
176 i80321_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
177 u_int reg, int bytes)
178 {
179 struct i80321_pci_softc *sc = device_get_softc(dev);
180 uint32_t isr;
181 uint32_t addr;
182 u_int32_t ret = 0;
183 vm_offset_t va;
184 int err = 0;
185 if (i80321_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
186 return (-1);
187 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR,
188 addr);
189
190 va = sc->sc_atu_sh;
191 switch (bytes) {
192 case 1:
193 err = badaddr_read((void*)(va + ATU_OCCDR + (reg & 3)), 1, &ret);
194 break;
195 case 2:
196 err = badaddr_read((void*)(va + ATU_OCCDR + (reg & 3)), 2, &ret);
197 break;
198 case 4:
199 err = badaddr_read((void *)(va + ATU_OCCDR), 4, &ret);
200 break;
201 default:
202 printf("i80321_read_config: invalid size %d\n", bytes);
203 ret = -1;
204 }
205 if (err) {
206
207 isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR);
208 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR,
209 isr & (ATUISR_P_SERR_DET|ATUISR_PMA|ATUISR_PTAM|
210 ATUISR_PTAT|ATUISR_PMPE));
211 return (-1);
212 }
213 return (ret);
214 }
215
216 static void
217 i80321_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
218 u_int reg, u_int32_t data, int bytes)
219 {
220 struct i80321_pci_softc *sc = device_get_softc(dev);
221 uint32_t addr;
222
223 if (i80321_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
224 return;
225
226
227 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR,
228 addr);
229 switch (bytes) {
230 case 1:
231 bus_space_write_1(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR +
232 (reg & 3), data);
233 break;
234 case 2:
235 bus_space_write_2(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR +
236 (reg & 3), data);
237 break;
238 case 4:
239 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR, data);
240 break;
241 default:
242 printf("i80321_pci_write_config: Invalid size : %d\n", bytes);
243 }
244
245 }
246
247 static int
248 i80321_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
249 {
250 struct i80321_pci_softc *sc = device_get_softc(dev);
251 switch (which) {
252 case PCIB_IVAR_DOMAIN:
253 *result = 0;
254 return (0);
255 case PCIB_IVAR_BUS:
256 *result = sc->sc_busno;
257 return (0);
258
259 }
260 return (ENOENT);
261 }
262
263 static int
264 i80321_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
265 {
266 struct i80321_pci_softc * sc = device_get_softc(dev);
267
268 switch (which) {
269 case PCIB_IVAR_DOMAIN:
270 return (EINVAL);
271 case PCIB_IVAR_BUS:
272 sc->sc_busno = result;
273 return (0);
274 }
275 return (ENOENT);
276 }
277
278 static struct resource *
279 i80321_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
280 u_long start, u_long end, u_long count, u_int flags)
281 {
282 struct i80321_pci_softc *sc = device_get_softc(bus);
283 struct resource *rv;
284 struct rman *rm;
285 bus_space_tag_t bt = NULL;
286 bus_space_handle_t bh = 0;
287
288 switch (type) {
289 case SYS_RES_IRQ:
290 rm = &sc->sc_irq_rman;
291 break;
292 case SYS_RES_MEMORY:
293 rm = &sc->sc_mem_rman;
294 bt = sc->sc_pcimem;
295 bh = (start >= 0x80000000 && start < 0x84000000) ? 0x80000000 :
296 sc->sc_mem;
297 start &= (0x1000000 - 1);
298 end &= (0x1000000 - 1);
299 break;
300 case SYS_RES_IOPORT:
301 rm = &sc->sc_io_rman;
302 bt = sc->sc_pciio;
303 bh = sc->sc_io;
304 if (start < sc->sc_io) {
305 start = start - 0x90000000 + sc->sc_io;
306 end = end - 0x90000000 + sc->sc_io;
307 }
308 break;
309 default:
310 return (NULL);
311 }
312
313 rv = rman_reserve_resource(rm, start, end, count, flags, child);
314 if (rv == NULL)
315 return (NULL);
316 rman_set_rid(rv, *rid);
317 if (type != SYS_RES_IRQ) {
318 if (type == SYS_RES_MEMORY)
319 bh += (rman_get_start(rv));
320 rman_set_bustag(rv, bt);
321 rman_set_bushandle(rv, bh);
322 if (flags & RF_ACTIVE) {
323 if (bus_activate_resource(child, type, *rid, rv)) {
324 rman_release_resource(rv);
325 return (NULL);
326 }
327 }
328 }
329 return (rv);
330 }
331
332 static int
333 i80321_pci_activate_resource(device_t bus, device_t child, int type, int rid,
334 struct resource *r)
335 {
336 u_long p;
337 int error;
338
339 if (type == SYS_RES_MEMORY) {
340 error = bus_space_map(rman_get_bustag(r),
341 rman_get_bushandle(r), rman_get_size(r), 0, &p);
342 if (error)
343 return (error);
344 rman_set_bushandle(r, p);
345
346 }
347 return (rman_activate_resource(r));
348 }
349
350 static int
351 i80321_pci_setup_intr(device_t dev, device_t child,
352 struct resource *ires, int flags, driver_filter_t *filt,
353 driver_intr_t *intr, void *arg, void **cookiep)
354 {
355 return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
356 filt, intr, arg, cookiep));
357 }
358
359 static int
360 i80321_pci_teardown_intr(device_t dev, device_t child, struct resource *res,
361 void *cookie)
362 {
363 return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
364 }
365
366 static device_method_t i80321_pci_methods[] = {
367 /* Device interface */
368 DEVMETHOD(device_probe, i80321_pci_probe),
369 DEVMETHOD(device_attach, i80321_pci_attach),
370 DEVMETHOD(device_shutdown, bus_generic_shutdown),
371 DEVMETHOD(device_suspend, bus_generic_suspend),
372 DEVMETHOD(device_resume, bus_generic_resume),
373
374 /* Bus interface */
375 DEVMETHOD(bus_read_ivar, i80321_read_ivar),
376 DEVMETHOD(bus_write_ivar, i80321_write_ivar),
377 DEVMETHOD(bus_alloc_resource, i80321_pci_alloc_resource),
378 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
379 DEVMETHOD(bus_activate_resource, i80321_pci_activate_resource),
380 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
381 DEVMETHOD(bus_setup_intr, i80321_pci_setup_intr),
382 DEVMETHOD(bus_teardown_intr, i80321_pci_teardown_intr),
383
384 /* pcib interface */
385 DEVMETHOD(pcib_maxslots, i80321_pci_maxslots),
386 DEVMETHOD(pcib_read_config, i80321_pci_read_config),
387 DEVMETHOD(pcib_write_config, i80321_pci_write_config),
388 DEVMETHOD(pcib_route_interrupt, machdep_pci_route_interrupt),
389
390 DEVMETHOD_END
391 };
392
393 static driver_t i80321_pci_driver = {
394 "pcib",
395 i80321_pci_methods,
396 sizeof(struct i80321_pci_softc),
397 };
398
399 static devclass_t i80321_pci_devclass;
400
401 DRIVER_MODULE(ipci, iq, i80321_pci_driver, i80321_pci_devclass, 0, 0);
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