The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/xscale/i80321/i80321var.h

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    1 /*      $NetBSD: i80321var.h,v 1.8 2003/10/06 16:06:06 thorpej Exp $    */
    2 
    3 /*-
    4  * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
    5  * All rights reserved.
    6  *
    7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. All advertising materials mentioning features or use of this software
   18  *    must display the following acknowledgement:
   19  *      This product includes software developed for the NetBSD Project by
   20  *      Wasabi Systems, Inc.
   21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
   22  *    or promote products derived from this software without specific prior
   23  *    written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
   26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
   29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   35  * POSSIBILITY OF SUCH DAMAGE.
   36  *
   37  * $FreeBSD: releng/9.0/sys/arm/xscale/i80321/i80321var.h 171628 2007-07-27 14:53:06Z cognet $
   38  *
   39  */
   40 
   41 #ifndef _ARM_XSCALE_I80321VAR_H_
   42 #define _ARM_XSCALE_I80321VAR_H_
   43 
   44 #include <sys/queue.h>
   45 #include <dev/pci/pcivar.h>
   46 #include <sys/rman.h>
   47 
   48 extern struct bus_space i80321_bs_tag;
   49 
   50 struct i80321_softc {
   51         device_t                dev;
   52         bus_space_tag_t         sc_st;
   53         bus_space_handle_t      sc_sh;
   54         /* Handles for the various subregions. */
   55         bus_space_handle_t      sc_atu_sh;
   56         bus_space_handle_t      sc_mcu_sh;
   57         int                     sc_is_host;
   58 
   59         /*
   60          * We expect the board-specific front-end to have already mapped
   61          * the PCI I/O space .. it is only 64K, and I/O mappings tend to
   62          * be smaller than a page size, so it's generally more efficient
   63          * to map them all into virtual space in one fell swoop.
   64          */
   65         vm_offset_t             sc_iow_vaddr;           /* I/O window vaddr */
   66 
   67         /*
   68          * Variables that define the Inbound windows.  The base address of
   69          * 0-2 are configured by a host via BARs.  The xlate variable
   70          * defines the start of the local address space that it maps to.
   71          * The size variable defines the byte size.
   72          *
   73          * The first 3 windows are for incoming PCI memory read/write
   74          * cycles from a host.  The 4th window, not configured by the
   75          * host (as it outside the normal BAR range) is the inbound
   76          * window for PCI devices controlled by the i80321.
   77          */
   78         struct {
   79                 uint32_t iwin_base_hi;
   80                 uint32_t iwin_base_lo;
   81                 uint32_t iwin_xlate;
   82                 uint32_t iwin_size;
   83         } sc_iwin[4];
   84 
   85         /*
   86          * Variables that define the Outbound windows.
   87          */
   88         struct {
   89                 uint32_t owin_xlate_lo;
   90                 uint32_t owin_xlate_hi;
   91         } sc_owin[2];
   92 
   93         /*
   94          * This is the PCI address that the Outbound I/O
   95          * window maps to.
   96          */
   97         uint32_t                sc_ioout_xlate;
   98 
   99         /* Bus space, DMA, and PCI tags for the PCI bus (private devices). */
  100         struct bus_space        sc_pci_iot;
  101         struct bus_space        sc_pci_memt;
  102 
  103         /* GPIO state */
  104         uint8_t sc_gpio_dir;    /* GPIO pin direction (1 == output) */
  105         uint8_t sc_gpio_val;    /* GPIO output pin value */
  106         struct rman sc_irq_rman;
  107                         
  108 };
  109 
  110 
  111 struct i80321_pci_softc {
  112         device_t                sc_dev;
  113         bus_space_tag_t         sc_st;
  114         bus_space_handle_t      sc_atu_sh;
  115         bus_space_tag_t         sc_pciio;
  116         bus_space_tag_t         sc_pcimem;
  117         int                     sc_busno;
  118         struct rman             sc_mem_rman;
  119         struct rman             sc_io_rman;
  120         struct rman             sc_irq_rman;
  121         uint32_t                sc_mem;
  122         uint32_t                sc_io;
  123 };
  124 
  125 void    i80321_sdram_bounds(bus_space_tag_t, bus_space_handle_t,
  126             vm_paddr_t *, vm_size_t *);
  127 
  128 void    i80321_attach(struct i80321_softc *);
  129 void    i80321_calibrate_delay(void);
  130 
  131 void    i80321_bs_init(bus_space_tag_t, void *);
  132 void    i80321_io_bs_init(bus_space_tag_t, void *);
  133 void    i80321_mem_bs_init(bus_space_tag_t, void *);
  134 extern int machdep_pci_route_interrupt(device_t pcib, device_t dev, int pin);
  135 
  136 
  137 #endif /* _ARM_XSCALE_I80321VAR_H_ */

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